github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-27 08:33:17 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/i915: move DDI_CLK_VALFREQ next to other Cx0 PHY registers

Browse Source 
Relocate DDI_CLK_VALFREQ register definition next to other Cx0 PHY
register macros.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-3-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2024-12-13 13:51:11 +02:00
parent 4821e26ab8
commit 2db03b5c01
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
View File

@ -9,6 +9,11 @@
#include "i915_reg_defs.h"
#include "intel_display_limits.h"
/* DDI Buffer Control */
#define _DDI_CLK_VALFREQ_A 0x64030
#define _DDI_CLK_VALFREQ_B 0x64130
#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
/*
* Wrapper macro to convert from port number to the index used in some of the
* registers. For Display version 20 and above it converts the port number to a

5
drivers/gpu/drm/i915/i915_reg.h
View File

@ -1067,11 +1067,6 @@
#define CLKGATE_DIS_PSL_EXT(pipe) \
_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
/* DDI Buffer Control */
#define _DDI_CLK_VALFREQ_A 0x64030
#define _DDI_CLK_VALFREQ_B 0x64130
#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
/*
* Display engine regs
*/