From 2d9a3c11254e304a1d14057b0b555ec87baffe3d Mon Sep 17 00:00:00 2001
From: Joseph Chen <chenjh@rock-chips.com>
Date: Tue, 2 Jan 2018 19:54:56 +0800
Subject: [PATCH] rockchip: sip: sm_nsec_ctx adds fiq spsr, sp and lr

due to optee os bugfix patch for FIQ:
	cf6a4d8 arm: sm: [bugfix] save/restore fiq core registers

we have to update sm_nsec_ctx to keep same with optee os, otherwise
FIQ debugger "bt" command is abnormal.

Change-Id: I950cfacd1c34abd88fbee2862c593b5fa59387bd
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
---
 include/linux/rockchip/rockchip_sip.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h
index 1a6b50212e77..e4342a894854 100644
--- a/include/linux/rockchip/rockchip_sip.h
+++ b/include/linux/rockchip/rockchip_sip.h
@@ -205,6 +205,9 @@ struct sm_nsec_ctx {
 	u32 irq_spsr;
 	u32 irq_sp;
 	u32 irq_lr;
+	u32 fiq_spsr;
+	u32 fiq_sp;
+	u32 fiq_lr;
 	u32 svc_spsr;
 	u32 svc_sp;
 	u32 svc_lr;