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wifi: rtw89: Turbo mode for RTL8851BU/RTL8852BU
RTL8851BU and RTL8852BU currently have much lower TX speed than expected, ~100 and ~300 Mbps, respectively. This is because part of the chip's memory is allocated for some unknown firmware features instead of the TX buffers. The vendor drivers have a module parameter called "rtw_quota_turbo_en", which can be used to choose between full TX speed or the unknown firmware features. It is on by default. Change the relevant chip parameters to implement the turbo mode. Do it only for USB because PCI is already fast even without the turbo mode. It's unclear if SDIO will need it or not. Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/88cce107-ff52-496f-bb77-b930e4182b67@gmail.com
This commit is contained in:
Bitterblue Smith
Ping-Ke Shih
parent
7c6084d7fa
commit
2d85152020
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@ -1729,8 +1729,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* 8852C PCIE SCC */
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.wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
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.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
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/* 8852B USB2.0/USB3.0 SCC */
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.wde_size25 = {RTW89_WDE_PG_64, 162, 94,},
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/* 8852B USB2.0/USB3.0 SCC turbo */
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.wde_size30 = {RTW89_WDE_PG_64, 220, 36,},
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/* 8852C USB2.0 */
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.wde_size31 = {RTW89_WDE_PG_64, 384, 0,},
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/* PCIE */
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@ -1754,10 +1754,10 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
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.ple_size20_v1 = {RTW89_PLE_PG_128, 2554, 182, 40960,},
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.ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,},
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/* 8852B USB2.0 SCC */
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.ple_size32 = {RTW89_PLE_PG_128, 620, 20,},
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/* 8852B USB3.0 SCC */
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.ple_size33 = {RTW89_PLE_PG_128, 632, 8,},
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/* 8851B USB2.0 SCC turbo */
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.ple_size27 = {RTW89_PLE_PG_128, 1396, 12,},
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/* 8852B USB3.0 SCC turbo */
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.ple_size31 = {RTW89_PLE_PG_128, 1392, 16,},
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/* 8852C USB2.0 */
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.ple_size34 = {RTW89_PLE_PG_128, 3374, 18,},
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/* PCIE 64 */
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@ -1780,8 +1780,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.wde_qt18 = {3228, 60, 0, 40,},
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.wde_qt19_v1 = {613, 6, 0, 20,},
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.wde_qt23 = {958, 48, 0, 16,},
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/* 8852B USB2.0/USB3.0 SCC */
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.wde_qt25 = {152, 2, 0, 8,},
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/* 8852B USB2.0/USB3.0 SCC turbo */
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.wde_qt30 = {210, 2, 0, 8,},
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/* 8852C USB2.0 */
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.wde_qt31 = {338, 6, 0, 40,},
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.ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,},
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@ -1799,6 +1799,9 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* 8852A USB SCC */
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.ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,},
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.ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,},
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/* 8852B USB3.0 SCC turbo */
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.ple_qt27 = {1040, 0, 16, 48, 13, 13, 178, 0, 32, 14, 8, 0,},
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.ple_qt28 = {1040, 0, 32, 48, 43, 13, 208, 0, 62, 14, 24, 0,},
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/* USB 52C USB3.0 */
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.ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
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.ple_qt42_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,},
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@ -1817,13 +1820,9 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* PCIE 64 */
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.ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
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.ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,},
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/* USB2.0 52B SCC */
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.ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,},
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/* USB2.0 52B 92K */
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.ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,},
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/* USB3.0 52B 92K */
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.ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,},
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.ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,},
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/* 8851B USB2.0 SCC turbo */
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.ple_qt61 = {858, 0, 16, 48, 4, 13, 370, 0, 32, 14, 8, 0, 0,},
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.ple_qt62 = {858, 0, 32, 48, 37, 13, 403, 0, 65, 14, 24, 0, 0,},
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/* USB2.0 52C */
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.ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,},
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/* USB2.0 52C */
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@ -2004,7 +2003,7 @@ static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,
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{
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u32 size = rtwdev->chip->fifo_size;
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if (mode == RTW89_QTA_SCC)
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if (mode == RTW89_QTA_SCC && rtwdev->hci.type != RTW89_HCI_TYPE_USB)
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size -= rtwdev->chip->dle_scc_rsvd_size;
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return size;
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@ -938,7 +938,7 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_size wde_size18_v1;
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const struct rtw89_dle_size wde_size19;
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const struct rtw89_dle_size wde_size23;
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const struct rtw89_dle_size wde_size25;
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const struct rtw89_dle_size wde_size30;
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const struct rtw89_dle_size wde_size31;
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const struct rtw89_dle_size ple_size0;
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const struct rtw89_dle_size ple_size1;
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@ -953,8 +953,8 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_size ple_size19;
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const struct rtw89_dle_size ple_size20_v1;
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const struct rtw89_dle_size ple_size22_v1;
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const struct rtw89_dle_size ple_size32;
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const struct rtw89_dle_size ple_size33;
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const struct rtw89_dle_size ple_size27;
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const struct rtw89_dle_size ple_size31;
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const struct rtw89_dle_size ple_size34;
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const struct rtw89_wde_quota wde_qt0;
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const struct rtw89_wde_quota wde_qt1;
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@ -968,7 +968,7 @@ struct rtw89_mac_size_set {
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const struct rtw89_wde_quota wde_qt18;
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const struct rtw89_wde_quota wde_qt19_v1;
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const struct rtw89_wde_quota wde_qt23;
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const struct rtw89_wde_quota wde_qt25;
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const struct rtw89_wde_quota wde_qt30;
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const struct rtw89_wde_quota wde_qt31;
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const struct rtw89_ple_quota ple_qt0;
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const struct rtw89_ple_quota ple_qt1;
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@ -980,6 +980,8 @@ struct rtw89_mac_size_set {
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const struct rtw89_ple_quota ple_qt18;
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const struct rtw89_ple_quota ple_qt25;
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const struct rtw89_ple_quota ple_qt26;
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const struct rtw89_ple_quota ple_qt27;
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const struct rtw89_ple_quota ple_qt28;
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const struct rtw89_ple_quota ple_qt42;
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const struct rtw89_ple_quota ple_qt42_v2;
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const struct rtw89_ple_quota ple_qt43;
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@ -991,10 +993,8 @@ struct rtw89_mac_size_set {
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const struct rtw89_ple_quota ple_qt57;
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const struct rtw89_ple_quota ple_qt58;
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const struct rtw89_ple_quota ple_qt59;
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const struct rtw89_ple_quota ple_qt72;
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const struct rtw89_ple_quota ple_qt73;
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const struct rtw89_ple_quota ple_qt74;
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const struct rtw89_ple_quota ple_qt75;
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const struct rtw89_ple_quota ple_qt61;
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const struct rtw89_ple_quota ple_qt62;
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const struct rtw89_ple_quota ple_qt78;
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const struct rtw89_ple_quota ple_qt79;
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const struct rtw89_ple_quota ple_qt_52a_wow;
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@ -52,25 +52,25 @@ static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = {
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};
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static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_usb[] = {
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{18, 152, grp_0}, /* ACH 0 */
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{18, 152, grp_0}, /* ACH 1 */
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{18, 152, grp_0}, /* ACH 2 */
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{18, 152, grp_0}, /* ACH 3 */
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{18, 210, grp_0}, /* ACH 0 */
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{18, 210, grp_0}, /* ACH 1 */
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{18, 210, grp_0}, /* ACH 2 */
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{18, 210, grp_0}, /* ACH 3 */
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{0, 0, grp_0}, /* ACH 4 */
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{0, 0, grp_0}, /* ACH 5 */
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{0, 0, grp_0}, /* ACH 6 */
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{0, 0, grp_0}, /* ACH 7 */
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{18, 152, grp_0}, /* B0MGQ */
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{18, 152, grp_0}, /* B0HIQ */
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{18, 210, grp_0}, /* B0MGQ */
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{18, 210, grp_0}, /* B0HIQ */
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{0, 0, grp_0}, /* B1MGQ */
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{0, 0, grp_0}, /* B1HIQ */
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{0, 0, 0} /* FWCMDQ */
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};
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static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_usb = {
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152, /* Group 0 */
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210, /* Group 0 */
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0, /* Group 1 */
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152, /* Public Max */
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210, /* Public Max */
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0 /* WP threshold */
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};
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@ -111,10 +111,10 @@ static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
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};
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static const struct rtw89_dle_mem rtw8851b_dle_mem_usb2[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
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&rtw89_mac_size.ple_size32, &rtw89_mac_size.wde_qt25,
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&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt72,
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&rtw89_mac_size.ple_qt73},
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
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&rtw89_mac_size.ple_size27, &rtw89_mac_size.wde_qt30,
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&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt61,
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&rtw89_mac_size.ple_qt62},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
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&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
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&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
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@ -124,10 +124,10 @@ static const struct rtw89_dle_mem rtw8851b_dle_mem_usb2[] = {
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};
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static const struct rtw89_dle_mem rtw8851b_dle_mem_usb3[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
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&rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
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&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
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&rtw89_mac_size.ple_qt75},
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
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&rtw89_mac_size.ple_size31, &rtw89_mac_size.wde_qt30,
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&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt27,
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&rtw89_mac_size.ple_qt28},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
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&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
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&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
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@ -50,25 +50,25 @@ static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = {
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};
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static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_usb[] = {
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{18, 152, grp_0}, /* ACH 0 */
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{18, 152, grp_0}, /* ACH 1 */
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{18, 152, grp_0}, /* ACH 2 */
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{18, 152, grp_0}, /* ACH 3 */
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{18, 210, grp_0}, /* ACH 0 */
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{18, 210, grp_0}, /* ACH 1 */
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{18, 210, grp_0}, /* ACH 2 */
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{18, 210, grp_0}, /* ACH 3 */
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{0, 0, grp_0}, /* ACH 4 */
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{0, 0, grp_0}, /* ACH 5 */
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{0, 0, grp_0}, /* ACH 6 */
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{0, 0, grp_0}, /* ACH 7 */
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{18, 152, grp_0}, /* B0MGQ */
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{18, 152, grp_0}, /* B0HIQ */
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{18, 210, grp_0}, /* B0MGQ */
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{18, 210, grp_0}, /* B0HIQ */
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{0, 0, grp_0}, /* B1MGQ */
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{0, 0, grp_0}, /* B1HIQ */
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{0, 0, 0} /* FWCMDQ */
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};
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static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_usb = {
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152, /* Group 0 */
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210, /* Group 0 */
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0, /* Group 1 */
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152, /* Public Max */
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210, /* Public Max */
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0 /* WP threshold */
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};
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@ -109,10 +109,10 @@ static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
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};
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static const struct rtw89_dle_mem rtw8852b_dle_mem_usb3[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
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&rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
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&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
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&rtw89_mac_size.ple_qt75},
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
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&rtw89_mac_size.ple_size31, &rtw89_mac_size.wde_qt30,
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&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt27,
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&rtw89_mac_size.ple_qt28},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
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&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
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&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
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