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ARM: dts: tacoma: Add phase corrections for eMMC

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The degree values were reversed out from the magic tap values of 7 (in)
and 15 + inversion (out) initially suggested by Aspeed.

With the patch tacoma survives several gigabytes of reads and writes
using dd while without it locks up randomly during the boot process.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210625061017.1149942-1-andrew@aj.id.au
Fixes: 2fc88f9235 ("mmc: sdhci-of-aspeed: Expose clock phase controls")
Fixes: 961216c135 ("ARM: dts: aspeed: Add Rainier system")
Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Andrew Jeffery 2021-06-25 15:40:17 +09:30 committed by Joel Stanley
parent 812bae32e5
commit 2d6608b57c
1 changed files with 1 additions and 0 deletions
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arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
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@ -186,6 +186,7 @@ &emmc_controller {
&emmc {
status = "okay";
clk-phase-mmc-hs200 = <36>, <270>;
};
&fsim0 {