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dt-bindings: dma: xlnx,axi-dma: Convert to DT schema
Convert the bindings document for Xilinx DMA. No changes to existing binding description. Signed-off-by: Abin Joseph <abin.joseph@amd.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260309033444.3472359-1-abin.joseph@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Abin Joseph
Vinod Koul
parent
dece5b9185
commit
2d5c2952b9
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@ -1,111 +0,0 @@
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Xilinx AXI VDMA engine, it does transfers between memory and video devices.
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It can be configured to have one channel or two channels. If configured
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as two channels, one is to transmit to the video device and another is
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to receive from the video device.
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Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
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target devices. It can be configured to have one channel or two channels.
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If configured as two channels, one is to transmit to the device and another
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is to receive from the device.
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Xilinx AXI CDMA engine, it does transfers between memory-mapped source
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address and a memory-mapped destination address.
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Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
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target devices. It can be configured to have up to 16 independent transmit
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and receive channels.
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Required properties:
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- compatible: Should be one of-
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"xlnx,axi-vdma-1.00.a"
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"xlnx,axi-dma-1.00.a"
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"xlnx,axi-cdma-1.00.a"
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"xlnx,axi-mcdma-1.00.a"
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- #dma-cells: Should be <1>, see "dmas" property below
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- reg: Should contain VDMA registers location and length.
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- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
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- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
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- dma-channel child node: Should have at least one channel and can have up to
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two channels per device. This node specifies the properties of each
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DMA channel (see child node properties below).
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- clocks: Input clock specifier. Refer to common clock bindings.
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- clock-names: List of input clocks
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For VDMA:
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Required elements: "s_axi_lite_aclk"
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Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
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"m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
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For CDMA:
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Required elements: "s_axi_lite_aclk", "m_axi_aclk"
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For AXIDMA and MCDMA:
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Required elements: "s_axi_lite_aclk"
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Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
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"m_axi_sg_aclk"
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Required properties for VDMA:
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- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
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Optional properties for AXI DMA and MCDMA:
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- xlnx,sg-length-width: Should be set to the width in bits of the length
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register as configured in h/w. Takes values {8...26}. If the property
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is missing or invalid then the default value 23 is used. This is the
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maximum value that is supported by all IP versions.
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Optional properties for AXI DMA:
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- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
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- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
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0-255. Setting this value to zero disables the delay timer interrupt.
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1 timeout interval = 125 * clock period of SG clock.
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Optional properties for VDMA:
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- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
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It takes following values:
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{1}, flush both channels
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{2}, flush mm2s channel
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{3}, flush s2mm channel
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Required child node properties:
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- compatible:
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For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
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"xlnx,axi-vdma-s2mm-channel".
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For CDMA: It should be "xlnx,axi-cdma-channel".
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For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"
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or "xlnx,axi-dma-s2mm-channel".
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- interrupts: Should contain per channel VDMA interrupts.
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- xlnx,datawidth: Should contain the stream data width, take values
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{32,64...1024}.
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Optional child node properties:
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- xlnx,include-dre: Tells hardware is configured for Data
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Realignment Engine.
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Optional child node properties for VDMA:
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- xlnx,genlock-mode: Tells Genlock synchronization is
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enabled/disabled in hardware.
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- xlnx,enable-vert-flip: Tells vertical flip is
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enabled/disabled in hardware(S2MM path).
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Optional child node properties for MCDMA:
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- dma-channels: Number of dma channels in child node.
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Example:
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++++++++
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axi_vdma_0: axivdma@40030000 {
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compatible = "xlnx,axi-vdma-1.00.a";
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#dma_cells = <1>;
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reg = < 0x40030000 0x10000 >;
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dma-ranges = <0x00000000 0x00000000 0x40000000>;
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xlnx,num-fstores = <0x8>;
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xlnx,flush-fsync = <0x1>;
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xlnx,addrwidth = <0x20>;
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clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
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"m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
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dma-channel@40030000 {
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compatible = "xlnx,axi-vdma-mm2s-channel";
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interrupts = < 0 54 4 >;
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xlnx,datawidth = <0x40>;
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} ;
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dma-channel@40030030 {
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compatible = "xlnx,axi-vdma-s2mm-channel";
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interrupts = < 0 53 4 >;
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xlnx,datawidth = <0x40>;
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} ;
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} ;
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299
Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml
Normal file
299
Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml
Normal file
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@ -0,0 +1,299 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/xilinx/xlnx,axi-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx AXI VDMA, DMA, CDMA and MCDMA IP
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maintainers:
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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- Abin Joseph <abin.joseph@amd.com>
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description: >
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Xilinx AXI VDMA engine, it does transfers between memory and video devices.
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It can be configured to have one channel or two channels. If configured
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as two channels, one is to transmit to the video device and another is
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to receive from the video device.
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Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
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target devices. It can be configured to have one channel or two channels.
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If configured as two channels, one is to transmit to the device and another
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is to receive from the device.
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Xilinx AXI CDMA engine, it does transfers between memory-mapped source
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address and a memory-mapped destination address.
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Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
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target devices. It can be configured to have up to 16 independent transmit
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and receive channels.
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properties:
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compatible:
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enum:
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- xlnx,axi-cdma-1.00.a
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- xlnx,axi-dma-1.00.a
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- xlnx,axi-mcdma-1.00.a
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- xlnx,axi-vdma-1.00.a
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reg:
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maxItems: 1
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"#dma-cells":
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const: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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interrupts:
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items:
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- description: Interrupt for single channel (MM2S or S2MM)
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- description: Interrupt for dual channel configuration
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minItems: 1
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description:
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Interrupt lines for the DMA controller. Only used when
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xlnx,axistream-connected is present (DMA connected to AXI Stream
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IP). When child dma-channel nodes are present, interrupts are
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specified in the child nodes instead.
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clocks:
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minItems: 1
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maxItems: 5
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clock-names:
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minItems: 1
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maxItems: 5
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dma-ranges: true
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xlnx,addrwidth:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [32, 64]
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description: The DMA addressing size in bits.
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xlnx,num-fstores:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 32
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description: Should be the number of framebuffers as configured in h/w.
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xlnx,flush-fsync:
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type: boolean
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description: Tells which channel to Flush on Frame sync.
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xlnx,sg-length-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 8
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maximum: 26
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default: 23
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description:
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Width in bits of the length register as configured in hardware.
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xlnx,irq-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 255
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description:
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Tells the interrupt delay timeout value. Valid range is from 0-255.
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Setting this value to zero disables the delay timer interrupt.
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1 timeout interval = 125 * clock period of SG clock.
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xlnx,axistream-connected:
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type: boolean
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description: Tells whether DMA is connected to AXI stream IP.
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patternProperties:
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"^dma-channel(-mm2s|-s2mm)?$":
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type: object
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description:
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Should have at least one channel and can have up to two channels per
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device. This node specifies the properties of each DMA channel.
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properties:
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compatible:
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enum:
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- xlnx,axi-vdma-mm2s-channel
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- xlnx,axi-vdma-s2mm-channel
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- xlnx,axi-cdma-channel
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- xlnx,axi-dma-mm2s-channel
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- xlnx,axi-dma-s2mm-channel
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interrupts:
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maxItems: 1
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xlnx,datawidth:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [32, 64, 128, 256, 512, 1024]
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description: Should contain the stream data width, take values {32,64...1024}.
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xlnx,include-dre:
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type: boolean
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description: Tells hardware is configured for Data Realignment Engine.
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xlnx,genlock-mode:
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type: boolean
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description: Tells Genlock synchronization is enabled/disabled in hardware.
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xlnx,enable-vert-flip:
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type: boolean
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description:
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Tells vertical flip is enabled/disabled in hardware(S2MM path).
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dma-channels:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Number of dma channels in child node.
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required:
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- compatible
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- interrupts
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- xlnx,datawidth
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additionalProperties: false
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allOf:
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- $ref: ../dma-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: xlnx,axi-vdma-1.00.a
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then:
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properties:
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clock-names:
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items:
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- const: s_axi_lite_aclk
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- const: m_axi_mm2s_aclk
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- const: m_axi_s2mm_aclk
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- const: m_axis_mm2s_aclk
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- const: s_axis_s2mm_aclk
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minItems: 1
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interrupts: false
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patternProperties:
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"^dma-channel(-mm2s|-s2mm)?$":
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properties:
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compatible:
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enum:
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- xlnx,axi-vdma-mm2s-channel
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- xlnx,axi-vdma-s2mm-channel
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required:
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- xlnx,num-fstores
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- if:
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properties:
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compatible:
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contains:
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const: xlnx,axi-cdma-1.00.a
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then:
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properties:
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clock-names:
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items:
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- const: s_axi_lite_aclk
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- const: m_axi_aclk
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interrupts: false
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patternProperties:
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"^dma-channel(-mm2s|-s2mm)?$":
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properties:
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compatible:
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enum:
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- xlnx,axi-cdma-channel
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- if:
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properties:
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compatible:
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contains:
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enum:
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- xlnx,axi-dma-1.00.a
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- xlnx,axi-mcdma-1.00.a
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then:
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properties:
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clock-names:
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items:
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- const: s_axi_lite_aclk
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- const: m_axi_mm2s_aclk
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- const: m_axi_s2mm_aclk
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- const: m_axi_sg_aclk
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minItems: 1
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patternProperties:
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"^dma-channel(-mm2s|-s2mm)?(@[0-9a-f]+)?$":
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properties:
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compatible:
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enum:
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- xlnx,axi-dma-mm2s-channel
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- xlnx,axi-dma-s2mm-channel
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required:
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- "#dma-cells"
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|
- reg
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- xlnx,addrwidth
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- dma-ranges
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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dma-controller@40030000 {
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compatible = "xlnx,axi-vdma-1.00.a";
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reg = <0x40030000 0x10000>;
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#dma-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges = <0x0 0x0 0x40000000>;
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clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",
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"m_axi_s2mm_aclk", "m_axis_mm2s_aclk",
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"s_axis_s2mm_aclk";
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xlnx,num-fstores = <8>;
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|
xlnx,flush-fsync;
|
||||||
|
xlnx,addrwidth = <32>;
|
||||||
|
|
||||||
|
dma-channel-mm2s {
|
||||||
|
compatible = "xlnx,axi-vdma-mm2s-channel";
|
||||||
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
xlnx,datawidth = <64>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma-channel-s2mm {
|
||||||
|
compatible = "xlnx,axi-vdma-s2mm-channel";
|
||||||
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
xlnx,datawidth = <64>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
|
||||||
|
dma-controller@a4030000 {
|
||||||
|
compatible = "xlnx,axi-dma-1.00.a";
|
||||||
|
reg = <0xa4030000 0x10000>;
|
||||||
|
#dma-cells = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
dma-ranges = <0x0 0x0 0x40000000>;
|
||||||
|
clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>;
|
||||||
|
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",
|
||||||
|
"m_axi_s2mm_aclk", "m_axi_sg_aclk";
|
||||||
|
xlnx,addrwidth = <32>;
|
||||||
|
xlnx,sg-length-width = <14>;
|
||||||
|
|
||||||
|
dma-channel-mm2s {
|
||||||
|
compatible = "xlnx,axi-dma-mm2s-channel";
|
||||||
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
xlnx,datawidth = <64>;
|
||||||
|
xlnx,include-dre;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma-channel-s2mm {
|
||||||
|
compatible = "xlnx,axi-dma-s2mm-channel";
|
||||||
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
xlnx,datawidth = <64>;
|
||||||
|
xlnx,include-dre;
|
||||||
|
};
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue
Block a user