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ARM: 9523/1: topology: allocate the cacheinfo early on the boot CPU
ARM secondary CPUs allocate cacheinfo in detect_cache_attributes(), called from secondary_start_kernel() with interrupts disabled. With PREEMPT_RT, the allocation takes a sleeping lock and triggers "BUG: sleeping function called from invalid context". Call fetch_cache_info() for each possible CPU from init_cpu_topology() on the boot CPU, following commit5944ce092b("arch_topology: Build cacheinfo from primary CPU"). This supplies the arrays before secondary CPUs populate them. Suppress -ENOENT and -EOPNOTSUPP, which leave cache detection to the existing late path. The CLIDR fallback uses the boot CPU's cache geometry. A secondary CPU with more cache leaves can still require late reallocation and trigger the warning. Assisted-by: LLM Fixes:a9ff944778("ARM: 9433/2: implement cacheinfo support") Cc: stable@vger.kernel.org Tested-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Link: https://lore.kernel.org/r/20260912195552.76673-5-kmehltretter@gmail.com/ Signed-off-by: Karl Mehltretter <kmehltretter@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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@ -12,6 +12,7 @@
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*/
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#include <linux/arch_topology.h>
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#include <linux/cacheinfo.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/cpumask.h>
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@ -238,8 +239,20 @@ void store_cpu_topology(unsigned int cpuid)
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*/
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void __init init_cpu_topology(void)
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{
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int cpu, ret;
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reset_cpu_topology();
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smp_wmb();
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parse_dt_topology();
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for_each_possible_cpu(cpu) {
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ret = fetch_cache_info(cpu);
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if (!ret)
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continue;
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/* CPUs without a usable CLIDR return -EOPNOTSUPP. */
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if (ret != -ENOENT && ret != -EOPNOTSUPP)
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pr_err("Early cacheinfo failed, ret = %d\n", ret);
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return;
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}
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}
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