ARM: 9523/1: topology: allocate the cacheinfo early on the boot CPU

ARM secondary CPUs allocate cacheinfo in detect_cache_attributes(),
called from secondary_start_kernel() with interrupts disabled. With
PREEMPT_RT, the allocation takes a sleeping lock and triggers
"BUG: sleeping function called from invalid context".

Call fetch_cache_info() for each possible CPU from init_cpu_topology()
on the boot CPU, following commit 5944ce092b ("arch_topology: Build
cacheinfo from primary CPU"). This supplies the arrays before secondary
CPUs populate them. Suppress -ENOENT and -EOPNOTSUPP, which leave cache
detection to the existing late path.

The CLIDR fallback uses the boot CPU's cache geometry. A secondary CPU
with more cache leaves can still require late reallocation and trigger
the warning.

Assisted-by: LLM

Fixes: a9ff944778 ("ARM: 9433/2: implement cacheinfo support")
Cc: stable@vger.kernel.org
Tested-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Link: https://lore.kernel.org/r/20260912195552.76673-5-kmehltretter@gmail.com/
Signed-off-by: Karl Mehltretter <kmehltretter@gmail.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Karl Mehltretter 2026-09-21 21:46:11 +01:00 committed by Russell King
parent 2315f2c46e
commit 2d4234f999

View File

@ -12,6 +12,7 @@
*/
#include <linux/arch_topology.h>
#include <linux/cacheinfo.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
@ -238,8 +239,20 @@ void store_cpu_topology(unsigned int cpuid)
*/
void __init init_cpu_topology(void)
{
int cpu, ret;
reset_cpu_topology();
smp_wmb();
parse_dt_topology();
for_each_possible_cpu(cpu) {
ret = fetch_cache_info(cpu);
if (!ret)
continue;
/* CPUs without a usable CLIDR return -EOPNOTSUPP. */
if (ret != -ENOENT && ret != -EOPNOTSUPP)
pr_err("Early cacheinfo failed, ret = %d\n", ret);
return;
}
}