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arm64: dts: exynos: gs101: add syscon-poweroff and syscon-reboot nodes

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Reboot of gs101 SoC can be handled by setting the
bit(SWRESET_SYSTEM[1]) of SYSTEM_CONFIGURATION register(PMU + 0x3a00).

Poweroff of gs101 SoC can be handled by setting bit(DATA[8]) of
PAD_CTRL_PWR_HOLD register (PMU + 0x3e9c).

Tested using "reboot" and "poweroff -p" commands.

Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20240628223506.1237523-3-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Peter Griffin 2024-06-28 23:35:04 +01:00 committed by Krzysztof Kozlowski
parent d281814b8f
commit 2d0c7ae784
1 changed files with 15 additions and 0 deletions
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15
arch/arm64/boot/dts/exynos/google/gs101.dtsi
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@ -1394,6 +1394,21 @@ sysreg_apm: syscon@174204e0 {
pmu_system_controller: system-controller@17460000 {
compatible = "google,gs101-pmu", "syscon";
reg = <0x17460000 0x10000>;
poweroff: syscon-poweroff {
compatible = "syscon-poweroff";
regmap = <&pmu_system_controller>;
offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */
mask = <0x100>; /* reset value */
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&pmu_system_controller>;
offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
mask = <0x2>; /* SWRESET_SYSTEM */
value = <0x2>; /* reset value */
};
};
pinctrl_gpio_alive: pinctrl@174d0000 {