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arm64: dts: fsl-ls1028a: Drop CPU masks from GICv3 PPI interrupts

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Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers.  Drop the masks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Geert Uytterhoeven 2026-03-04 18:11:00 +01:00 committed by Frank Li
parent 130d90114c
commit 2cf0902ca8
1 changed files with 5 additions and 10 deletions
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15
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@ -114,14 +114,10 @@ optee: optee {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
@ -138,8 +134,7 @@ gic: interrupt-controller@6000000 {
<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;