From 2cc5ac6e859bcf3ec5d4c8725909918f8bb907a2 Mon Sep 17 00:00:00 2001 From: bui duc phuc Date: Tue, 9 Jun 2026 18:38:27 +0700 Subject: [PATCH] ARM: dts: renesas: r8a7740: Add FSI clocks Add the SPU bus clock, icka/b functional clocks, and xcka/b external clock inputs to the FSI device node. This prepares for subsequent driver changes that explicitly manage the SPU clock required for FSI register access on R-Mobile A1. Signed-off-by: bui duc phuc Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260609113836.45079-3-phucduc.bui@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index c7056b96ec0b..d4776a7877ff 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -501,7 +501,11 @@ sh_fsi2: sound@fe1f0000 { compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; + clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsib_clk>, <&fsiack_clk>, + <&fsibck_clk>; + clock-names = "fck", "spu", "icka", "ickb", "xcka", + "xckb"; power-domains = <&pd_a4mp>; status = "disabled"; }; @@ -722,6 +726,12 @@ vou_clk: vou@e6150088 { <0>; #clock-cells = <0>; }; + fsib_clk: fsib@e6150090 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150090 4>; + clocks = <&pllc1_div2_clk>, <&fsibck_clk>, <0>, <0>; + #clock-cells = <0>; + }; stpro_clk: stpro@e615009c { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>;