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dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528
EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY which behaves slightly differently because one slot is Gen1/Gen2 while the other is Gen1 only. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260425173642.406089-2-cjd@cjdns.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528
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maintainers:
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- Caleb James DeLisle <cjd@cjdns.fr>
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description:
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The PCIe PHY supports physical layer functionality for PCIe Gen1 and
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Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while
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port 1 is Gen1/Gen2 capable.
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properties:
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compatible:
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enum:
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- econet,en751221-pcie-gen1
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- econet,en751221-pcie-gen2
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- econet,en7528-pcie-gen1
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- econet,en7528-pcie-gen2
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reg:
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maxItems: 1
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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pcie-phy@1faf2000 {
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compatible = "econet,en7528-pcie-gen1";
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reg = <0x1faf2000 0x1000>;
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#phy-cells = <0>;
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};
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};
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...
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@ -9153,6 +9153,12 @@ F: drivers/irqchip/irq-econet-en751221.c
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F: include/dt-bindings/clock/econet,en751221-scu.h
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F: include/dt-bindings/reset/econet,en751221-scu.h
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ECONET PCIE PHY DRIVER
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M: Caleb James DeLisle <cjd@cjdns.fr>
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L: linux-mips@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
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ECRYPT FILE SYSTEM
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M: Tyler Hicks <code@tyhicks.com>
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L: ecryptfs@vger.kernel.org
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