dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528

EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY
which behaves slightly differently because one slot is Gen1/Gen2 while
the other is Gen1 only.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260425173642.406089-2-cjd@cjdns.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Caleb James DeLisle 2026-04-25 17:36:41 +00:00 committed by Vinod Koul
parent 864b3617df
commit 2cc066dbd3
2 changed files with 56 additions and 0 deletions

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@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528
maintainers:
- Caleb James DeLisle <cjd@cjdns.fr>
description:
The PCIe PHY supports physical layer functionality for PCIe Gen1 and
Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while
port 1 is Gen1/Gen2 capable.
properties:
compatible:
enum:
- econet,en751221-pcie-gen1
- econet,en751221-pcie-gen2
- econet,en7528-pcie-gen1
- econet,en7528-pcie-gen2
reg:
maxItems: 1
"#phy-cells":
const: 0
required:
- compatible
- reg
- "#phy-cells"
additionalProperties: false
examples:
- |
soc {
#address-cells = <1>;
#size-cells = <1>;
pcie-phy@1faf2000 {
compatible = "econet,en7528-pcie-gen1";
reg = <0x1faf2000 0x1000>;
#phy-cells = <0>;
};
};
...

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@ -9153,6 +9153,12 @@ F: drivers/irqchip/irq-econet-en751221.c
F: include/dt-bindings/clock/econet,en751221-scu.h
F: include/dt-bindings/reset/econet,en751221-scu.h
ECONET PCIE PHY DRIVER
M: Caleb James DeLisle <cjd@cjdns.fr>
L: linux-mips@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
ECRYPT FILE SYSTEM
M: Tyler Hicks <code@tyhicks.com>
L: ecryptfs@vger.kernel.org