media: ipu6: Make ipu7 gpreg stride configurable as per IPU version

IPU8's GPREG stride is 0x2000, not IPU7's hardcoded 0x1000. Add
csi2.gpreg_stride and use it in the two gpreg accessors instead of the
fixed value, wiring it up for both IPU7 and IPU8 in
ipu6_internal_pdata_init().

Signed-off-by: Divyamani Tripathi <divyamani.tripathi@intel.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
This commit is contained in:
Divyamani Tripathi 2026-10-01 10:31:31 +03:00 committed by Sakari Ailus
parent a187e02308
commit 2c6705d773
4 changed files with 14 additions and 2 deletions

View File

@ -373,6 +373,13 @@ static void ipu6_internal_pdata_init(struct ipu6_device *isp)
if (IS_IPU7(isp)) {
isys_ipdata.csi2.gpreg = IPU7_IS_IO_CSI2_GPREGS_BASE;
isys_ipdata.csi2.gpreg_stride = IPU7_IS_IO_CSI2_GPREGS_STRIDE;
isys_ipdata.csi2.nports = 4;
}
if (IS_IPU8(isp)) {
isys_ipdata.csi2.gpreg = IPU8_IS_IO_CSI2_GPREGS_BASE;
isys_ipdata.csi2.gpreg_stride = IPU8_IS_IO_CSI2_GPREGS_STRIDE;
isys_ipdata.csi2.nports = 4;
}
}

View File

@ -147,6 +147,7 @@ struct ipu6_isys_internal_csi2_pdata {
u32 fw_access_port_ofs;
/* IPU7-specific field */
u32 gpreg;
u32 gpreg_stride;
};
struct ipu6_isys_internal_tpg_pdata {

View File

@ -167,7 +167,8 @@ static void gpreg_write(struct ipu6_isys *isys, u32 id, u32 addr, u32 data)
{
void __iomem *isys_base = isys->pdata->base;
u32 gpreg = isys->pdata->ipdata->csi2.gpreg;
void __iomem *base = isys_base + gpreg + 0x1000 * id;
void __iomem *base = isys_base + gpreg +
isys->pdata->ipdata->csi2.gpreg_stride * id;
struct device *dev = &isys->adev->auxdev.dev;
dev_dbg(dev, "gpreg write: reg 0x%lx = data 0x%08x",
@ -344,7 +345,8 @@ static int ipu7_isys_phy_ready(struct ipu6_isys *isys, u32 id)
{
void __iomem *isys_base = isys->pdata->base;
u32 gpreg_offset = isys->pdata->ipdata->csi2.gpreg;
void __iomem *gpreg = isys_base + gpreg_offset + 0x1000 * id;
void __iomem *gpreg = isys_base + gpreg_offset +
isys->pdata->ipdata->csi2.gpreg_stride * id;
struct device *dev = &isys->adev->auxdev.dev;
u32 phy_ready;
u32 reg, rext;

View File

@ -968,7 +968,9 @@
/* software config the phy */
#define IPU7_IS_IO_CSI2_GPREGS_BASE (IPU7_IS_IO_BASE + 0x53400)
#define IPU7_IS_IO_CSI2_GPREGS_STRIDE 0x1000
#define IPU8_IS_IO_CSI2_GPREGS_BASE (IPU7_IS_IO_BASE + 0x40e00)
#define IPU8_IS_IO_CSI2_GPREGS_STRIDE 0x2000
#define IPU7_CSI_ADAPT_LAYER_SRST 0x0
#define IPU7_MPF_SRST_RST 0x4
#define IPU7_CSI_ERR_IRQ_CTRL_SRST 0x8