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ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x
Memory access must be blocked before hardware reset is asserted and before power is gated, otherwise a serious hardware fault is inevitable. Add reset for memory clients to the GR2D, GR3D and Host1x nodes. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -123,8 +123,8 @@ host1x@50000000 {
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interrupt-names = "syncpt", "host1x";
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clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
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clock-names = "host1x";
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>;
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reset-names = "host1x", "mc";
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iommus = <&mc TEGRA_SWGROUP_HC>;
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power-domains = <&pd_heg>;
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operating-points-v2 = <&host1x_dvfs_opp_table>;
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@ -190,8 +190,8 @@ gr2d@54140000 {
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reg = <0x54140000 0x00040000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_GR2D>;
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resets = <&tegra_car 21>;
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reset-names = "2d";
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resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>;
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reset-names = "2d", "mc";
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power-domains = <&pd_heg>;
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operating-points-v2 = <&gr2d_dvfs_opp_table>;
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@ -205,8 +205,10 @@ gr3d@54180000 {
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<&tegra_car TEGRA30_CLK_GR3D2>;
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clock-names = "3d", "3d2";
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resets = <&tegra_car 24>,
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<&tegra_car 98>;
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reset-names = "3d", "3d2";
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<&tegra_car 98>,
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<&mc TEGRA30_MC_RESET_3D>,
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<&mc TEGRA30_MC_RESET_3D2>;
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reset-names = "3d", "3d2", "mc", "mc2";
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power-domains = <&pd_3d0>, <&pd_3d1>;
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power-domain-names = "3d0", "3d1";
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operating-points-v2 = <&gr3d_dvfs_opp_table>;
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