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drm/{i915, xe}: add shared header for VLV IOSF sideband units and registers

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Move vlv_iosf_sb_reg.h to include/drm/intel/vlv_iosf_sb_regs.h. Use
_regs.h suffix to align better with other register headers. Move enum
vlv_iosf_sb_unit there as well, breaking the final include tie related
to IOSF sideband between display and i915 core.

With this, we can completely remove the xe compat vls_iosf_sb*.h
headers.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/41b060b0d6453de39ca775eab10ee12b25c45b7d.1774957233.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2026-03-31 14:40:58 +03:00
parent 0563e28e08
commit 2c0c1e9a66
8 changed files with 19 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/display/intel_display_power_map.c
View File

@ -4,13 +4,13 @@
*/
#include <drm/drm_print.h>
#include <drm/intel/vlv_iosf_sb_regs.h>
#include "intel_display_core.h"
#include "intel_display_power_map.h"
#include "intel_display_power_well.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "vlv_iosf_sb_reg.h"
#define __LIST_INLINE_ELEMS(__elem_type, ...) \
((__elem_type[]) { __VA_ARGS__ })

1
drivers/gpu/drm/i915/display/intel_display_power_well.c
View File

@ -34,7 +34,6 @@
#include "intel_vga.h"
#include "skl_watermark.h"
#include "vlv_dpio_phy_regs.h"
#include "vlv_iosf_sb_reg.h"
#include "vlv_sideband.h"
/*

2
drivers/gpu/drm/i915/display/intel_parent.c
View File

@ -19,10 +19,10 @@
#include <drm/drm_print.h>
#include <drm/intel/display_parent_interface.h>
#include <drm/intel/vlv_iosf_sb_regs.h>
#include "intel_display_core.h"
#include "intel_parent.h"
#include "vlv_iosf_sb.h"
/* dpt */
struct intel_dpt *intel_parent_dpt_create(struct intel_display *display,

3
drivers/gpu/drm/i915/display/vlv_sideband.h
View File

@ -6,8 +6,7 @@
#include <linux/types.h>
#include "vlv_iosf_sb.h"
#include "vlv_iosf_sb_reg.h"
#include <drm/intel/vlv_iosf_sb_regs.h>
enum dpio_phy;
struct intel_display;

14
drivers/gpu/drm/i915/vlv_iosf_sb.h
View File

@ -8,23 +8,11 @@
#include <linux/types.h>
#include "vlv_iosf_sb_reg.h"
#include <drm/intel/vlv_iosf_sb_regs.h>
struct drm_device;
struct drm_i915_private;
enum vlv_iosf_sb_unit {
VLV_IOSF_SB_BUNIT,
VLV_IOSF_SB_CCK,
VLV_IOSF_SB_CCU,
VLV_IOSF_SB_DPIO,
VLV_IOSF_SB_DPIO_2,
VLV_IOSF_SB_FLISDSI,
VLV_IOSF_SB_GPIO,
VLV_IOSF_SB_NC,
VLV_IOSF_SB_PUNIT,
};
void vlv_iosf_sb_init(struct drm_i915_private *i915);
void vlv_iosf_sb_fini(struct drm_i915_private *i915);

42
drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb.h
View File

@ -1,42 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2013-2021 Intel Corporation
*/
#ifndef _VLV_IOSF_SB_H_
#define _VLV_IOSF_SB_H_
#include <linux/types.h>
#include "vlv_iosf_sb_reg.h"
struct drm_device;
enum vlv_iosf_sb_unit {
VLV_IOSF_SB_BUNIT,
VLV_IOSF_SB_CCK,
VLV_IOSF_SB_CCU,
VLV_IOSF_SB_DPIO,
VLV_IOSF_SB_DPIO_2,
VLV_IOSF_SB_FLISDSI,
VLV_IOSF_SB_GPIO,
VLV_IOSF_SB_NC,
VLV_IOSF_SB_PUNIT,
};
static inline void vlv_iosf_sb_get(struct drm_device *drm, unsigned long ports)
{
}
static inline u32 vlv_iosf_sb_read(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr)
{
return 0;
}
static inline int vlv_iosf_sb_write(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val)
{
return 0;
}
static inline void vlv_iosf_sb_put(struct drm_device *drm, unsigned long ports)
{
}
#endif /* _VLV_IOSF_SB_H_ */

6
drivers/gpu/drm/xe/compat-i915-headers/vlv_iosf_sb_reg.h
View File

@ -1,6 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2023 Intel Corporation
*/
#include "../../i915/vlv_iosf_sb_reg.h"

18
drivers/gpu/drm/i915/vlv_iosf_sb_reg.h → include/drm/intel/vlv_iosf_sb_regs.h
View File

@ -3,8 +3,20 @@
* Copyright © 2022 Intel Corporation
*/
#ifndef _VLV_IOSF_SB_REG_H_
#define _VLV_IOSF_SB_REG_H_
#ifndef _VLV_IOSF_SB_REGS_H_
#define _VLV_IOSF_SB_REGS_H_
enum vlv_iosf_sb_unit {
VLV_IOSF_SB_BUNIT,
VLV_IOSF_SB_CCK,
VLV_IOSF_SB_CCU,
VLV_IOSF_SB_DPIO,
VLV_IOSF_SB_DPIO_2,
VLV_IOSF_SB_FLISDSI,
VLV_IOSF_SB_GPIO,
VLV_IOSF_SB_NC,
VLV_IOSF_SB_PUNIT,
};
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
@ -177,4 +189,4 @@
#define CCK_FREQUENCY_STATUS_SHIFT 8
#define CCK_FREQUENCY_VALUES (0x1f << 0)
#endif /* _VLV_IOSF_SB_REG_H_ */
#endif /* _VLV_IOSF_SB_REGS_H_ */