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arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs

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The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper
interrupt partition maps and use the 4th interrupt cell to pass the
partition phandle for each ARM PMU node.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250228-topic-sm8650-pmu-ppi-partition-v4-2-78cffd35c73d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Neil Armstrong 2025-02-28 09:40:26 +01:00 committed by Bjorn Andersson
parent 9ce52e908b
commit 2c06e0797c
1 changed files with 17 additions and 3 deletions
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20
arch/arm64/boot/dts/qcom/sm8650.dtsi
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@ -1576,17 +1576,17 @@ opp-3302400000 {
pmu-a520 {
compatible = "arm,cortex-a520-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
};
pmu-a720 {
compatible = "arm,cortex-a720-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
};
pmu-x4 {
compatible = "arm,cortex-x4-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>;
};
psci {
@ -6754,6 +6754,20 @@ intc: interrupt-controller@17100000 {
#size-cells = <2>;
ranges;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>;
};
ppi_cluster2: interrupt-partition-2 {
affinity = <&cpu7>;
};
};
gic_its: msi-controller@17140000 {
compatible = "arm,gic-v3-its";
reg = <0 0x17140000 0 0x20000>;