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drm/msm/disp: simplify tiled RGB{,A,X} formats definitions
Define several additional macros, capturing tiled RGB format classes, in order to simplify defining particular RGB* format. Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688169/ Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-5-cae312379d49@oss.qualcomm.com Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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Dmitry Baryshkov
parent
8549e95a4b
commit
2bd6ae0edf
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@ -163,22 +163,83 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
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.tile_height = MDP_TILE_HEIGHT_DEFAULT \
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}
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#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
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alpha, bp, flg) \
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#define INTERLEAVED_RGB_FMT_TILED(fmt, bp, r, g, b, e0, e1, e2) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_INTERLEAVED, \
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.alpha_enable = alpha, \
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.alpha_enable = false, \
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.element = { (e0), (e1), (e2), 0 }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = 0, \
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.chroma_sample = CHROMA_FULL, \
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.unpack_count = 3, \
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.bpp = bp, \
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.fetch_mode = MDP_FETCH_UBWC, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
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MSM_FORMAT_FLAG_COMPRESSED, \
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.num_planes = 2, \
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.tile_height = MDP_TILE_HEIGHT_UBWC, \
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}
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#define INTERLEAVED_RGBA_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_INTERLEAVED, \
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.alpha_enable = true, \
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.element = { (e0), (e1), (e2), (e3) }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = CHROMA_FULL, \
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.unpack_count = uc, \
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.unpack_count = 4, \
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.bpp = bp, \
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.fetch_mode = MDP_FETCH_UBWC, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
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MSM_FORMAT_FLAG_COMPRESSED, \
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.num_planes = 2, \
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.tile_height = MDP_TILE_HEIGHT_UBWC, \
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}
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#define INTERLEAVED_RGBX_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_INTERLEAVED, \
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.alpha_enable = false, \
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.element = { (e0), (e1), (e2), (e3) }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = CHROMA_FULL, \
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.unpack_count = 4, \
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.bpp = bp, \
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.fetch_mode = MDP_FETCH_UBWC, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
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MSM_FORMAT_FLAG_COMPRESSED, \
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.num_planes = 2, \
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.tile_height = MDP_TILE_HEIGHT_UBWC, \
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}
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#define INTERLEAVED_RGBA_DX_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_INTERLEAVED, \
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.alpha_enable = true, \
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.element = { (e0), (e1), (e2), (e3) }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = CHROMA_FULL, \
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.unpack_count = 4, \
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.bpp = bp, \
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.fetch_mode = MDP_FETCH_UBWC, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
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MSM_FORMAT_FLAG_DX | \
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MSM_FORMAT_FLAG_COMPRESSED, \
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.num_planes = 2, \
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.tile_height = MDP_TILE_HEIGHT_UBWC, \
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}
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@ -525,58 +586,49 @@ static const struct msm_format mdp_formats[] = {
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* the data will be passed by user-space.
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*/
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static const struct msm_format mdp_formats_ubwc[] = {
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INTERLEAVED_RGB_FMT_TILED(BGR565,
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0, BPC5, BPC6, BPC5,
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C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
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false, 2, MSM_FORMAT_FLAG_COMPRESSED),
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INTERLEAVED_RGB_FMT_TILED(BGR565, 2,
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BPC5, BPC6, BPC5,
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C2_R_Cr, C0_G_Y, C1_B_Cb),
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INTERLEAVED_RGB_FMT_TILED(ABGR8888,
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INTERLEAVED_RGBA_FMT_TILED(ABGR8888, 4,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 4, MSM_FORMAT_FLAG_COMPRESSED),
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
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/* ARGB8888 and ABGR8888 purposely have the same color
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* ordering. The hardware only supports ABGR8888 UBWC
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* natively.
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*/
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INTERLEAVED_RGB_FMT_TILED(ARGB8888,
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INTERLEAVED_RGBA_FMT_TILED(ARGB8888, 4,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 4, MSM_FORMAT_FLAG_COMPRESSED),
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
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INTERLEAVED_RGB_FMT_TILED(XBGR8888,
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INTERLEAVED_RGBX_FMT_TILED(XBGR8888, 4,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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false, 4, MSM_FORMAT_FLAG_COMPRESSED),
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
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INTERLEAVED_RGB_FMT_TILED(XRGB8888,
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INTERLEAVED_RGBX_FMT_TILED(XRGB8888, 4,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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false, 4, MSM_FORMAT_FLAG_COMPRESSED),
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
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INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
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INTERLEAVED_RGBA_DX_FMT_TILED(ABGR2101010, 4,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
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INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
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INTERLEAVED_RGBA_DX_FMT_TILED(XBGR2101010, 4,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
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INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
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INTERLEAVED_RGBA_DX_FMT_TILED(XRGB2101010, 4,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
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/* XRGB2101010 and ARGB2101010 purposely have the same color
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* ordering. The hardware only supports ARGB2101010 UBWC
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* natively.
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*/
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INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
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INTERLEAVED_RGBA_DX_FMT_TILED(ARGB2101010, 4,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
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PSEUDO_YUV_FMT_TILED(NV12,
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0, BPC8, BPC8, BPC8,
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