From 628f6ac792c9a3dace4b6f50d6445f7d5a6af4f2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 3 Nov 2025 16:48:32 -0500 Subject: [PATCH 001/104] arm64: dts: imx8qm: add ddr perf device node Add ddr perf monitor device node for i.MX8QM. Change imx8-ss-ddr.dtsi's compatible string to fsl,imx8qxp-ddr-pmu. i.MX8QM overwrite to fsl,imx8qm-ddr-pmu. All fallback to fsl,imx8-ddr-pmu. Signed-off-by: Joakim Zhang Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8-ss-ddr.dtsi | 2 +- .../boot/dts/freescale/imx8qm-ss-ddr.dtsi | 19 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 ++ 3 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi index 7d5183c6c5be..37e68865b026 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi @@ -11,7 +11,7 @@ ddr_subsys: bus@5c000000 { ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; ddr_pmu0: ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; + compatible = "fsl,imx8qxp-ddr-pmu", "fsl,imx8-ddr-pmu"; reg = <0x5c020000 0x10000>; interrupts = ; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi new file mode 100644 index 000000000000..c831567cfbc1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * Dong Aisheng + */ + +&ddr_pmu0 { + compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu"; + interrupts = ; +}; + +&ddr_subsys { + ddr_pmu1: ddr-pmu@5c120000 { + compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu"; + reg = <0x5c120000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index cb66853b1cd3..9e7309a0ca51 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -635,6 +635,7 @@ vpu_dsp: dsp@556e8000 { #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" #include "imx8-ss-hsio.dtsi" }; @@ -647,5 +648,6 @@ vpu_dsp: dsp@556e8000 { #include "imx8qm-ss-lvds.dtsi" #include "imx8qm-ss-mipi.dtsi" #include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-ddr.dtsi" /delete-node/ &dsp; From 4688fd527c85f63890167b4705a3622488e73781 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 3 Nov 2025 16:48:33 -0500 Subject: [PATCH 002/104] arm64: dts: imx8dxl-ss-ddr: Add DB (system interconnects) pmu support for i.MX8DXL Add DB pmu related nodes. This pmu is in DB (system interconnects). Signed-off-by: Jacky Bai Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 22 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 7 ++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi index 3569abb5bb9b..adc6e394dbc5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -7,3 +7,25 @@ &ddr_pmu0 { compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu"; interrupts = ; }; + +&ddr_subsys { + db_pmu0: db-pmu@5ca40000 { + compatible = "fsl,imx8dxl-db-pmu"; + reg = <0x5ca40000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_4>, <&db_pmu0_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "cnt"; + }; + + db_pmu0_lpcg: clock-controller@5cae0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5cae0000 0x10000>; + #clock-cells = <1>; + clocks = <&db_ipg_clk>, <&db_ipg_clk>; + clock-indices = , ; + clock-output-names = "perf_lpcg_cnt_clk", + "perf_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_PERF>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 8d60827822ed..5106be2fde6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -236,6 +236,13 @@ xtal24m: clock-xtal24m { clock-output-names = "xtal_24MHz"; }; + db_ipg_clk: clock-db-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <456000000>; + clock-output-names = "db_ipg_clk"; + }; + /* sorted in register address */ #include "imx8-ss-cm40.dtsi" #include "imx8-ss-adma.dtsi" From c3ea38980ab48c8b86d2f940cd9714b5b8c62d9b Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Sun, 16 Nov 2025 09:35:57 +0800 Subject: [PATCH 003/104] arm64: dts: imx94: add basic NETC related nodes The NETC related nodes for i.MX94, this NETC has two PCIe buses, the bus 0 has 1 ENETC instance, one PTP timer, one RCEC and a switch, currently, the switch is not added due to the DT binding and the driver is not ready at the moment. The bus 1 has three ENETC instances, 2 PTP timers, 1 RCEC and one EMDIO. Signed-off-by: Wei Fang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx94.dtsi | 138 +++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 73184f03f8a3..4fdec712307f 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1191,6 +1191,144 @@ wdog3: watchdog@49220000 { }; }; + netc_blk_ctrl: system-controller@4ceb0000 { + compatible = "nxp,imx94-netc-blk-ctrl"; + reg = <0x0 0x4ceb0000 0x0 0x10000>, + <0x0 0x4cec0000 0x0 0x10000>, + <0x0 0x4c810000 0x0 0x7C>; + reg-names = "ierb", "prb", "netcmix"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + clocks = <&scmi_clk IMX94_CLK_ENET>; + clock-names = "ipg"; + power-domains = <&scmi_devpd IMX94_PD_NETC>; + status = "disabled"; + + netc_bus0: pcie@4ca00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4ca00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x0 0x0>; + msi-map = <0x00 &its 0x68 0x1>, //ENETC3 PF + <0x01 &its 0x61 0x1>, //Timer0 + <0x02 &its 0x64 0x1>, //Switch + <0x40 &its 0x69 0x1>, //ENETC3 VF0 + <0x80 &its 0x6a 0x1>, //ENETC3 VF1 + <0xC0 &its 0x6b 0x1>; //ENETC3 VF2 + /* Switch BAR0 - non-prefetchable memory */ + ranges = <0x02000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0x80000 + /* ENETC 3 and Timer 0 BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4cd40000 0x0 0x4cd40000 0x0 0x60000 + /* Switch and Timer 0 BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce00000 0x0 0x4ce00000 0x0 0x20000 + /* ENETC 3 VF0-2 BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4ce50000 0x0 0x4ce50000 0x0 0x30000 + /* ENETC 3 VF0-2 BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce80000 0x0 0x4ce80000 0x0 0x30000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 + GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + enetc3: ethernet@0,0 { + compatible = "pci1131,e110"; + reg = <0x0 0 0 0 0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + netc_timer0: ptp-timer@0,1 { + compatible = "pci1131,ee02"; + reg = <0x100 0 0 0 0>; + status = "disabled"; + }; + + rcec@1,0 { + reg = <0x800 0 0 0 0>; + interrupts = <1>; + }; + }; + + netc_bus1: pcie@4cb00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4cb00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x1 0x1>; + msi-map = <0x100 &its 0x65 0x1>, //ENETC0 PF + <0x101 &its 0x62 0x1>, //Timer1 + <0x140 &its 0x66 0x1>, //ENETC1 PF + <0x180 &its 0x67 0x1>, //ENETC2 PF + <0x181 &its 0x63 0x1>, //Timer2 + <0x1C0 &its 0x60 0x1>; //EMDIO + /* ENETC 0-2 BAR0 - non-prefetchable memory */ + ranges = <0x02000000 0x0 0x4cC80000 0x0 0x4cc80000 0x0 0xc0000 + /* Timer 1-2 and EMDIO BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4cda0000 0x0 0x4cda0000 0x0 0x60000 + /* Timer 1-2 and EMDIO BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce20000 0x0 0x4ce20000 0x0 0x30000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 + GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + + enetc0: ethernet@0,0 { + compatible = "pci1131,e101"; + reg = <0x10000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer1: ptp-timer@0,1 { + compatible = "pci1131,ee02"; + reg = <0x10100 0 0 0 0>; + status = "disabled"; + }; + + rcec@1,0 { + reg = <0x10800 0 0 0 0>; + interrupts = <1>; + }; + + enetc1: ethernet@8,0 { + compatible = "pci1131,e101"; + reg = <0x14000 0 0 0 0>; + status = "disabled"; + }; + + enetc2: ethernet@10,0 { + compatible = "pci1131,e101"; + reg = <0x18000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer2: ptp-timer@10,1 { + compatible = "pci1131,ee02"; + reg = <0x18100 0 0 0 0>; + status = "disabled"; + }; + + netc_emdio: mdio@18,0 { + compatible = "pci1131,ee00"; + reg = <0x1c000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>; From bfc1982c660161c4a768b6696dc24b9f608aeea0 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Sun, 16 Nov 2025 09:35:58 +0800 Subject: [PATCH 004/104] arm64: dts: imx943-evk: add ENETC, EMDIO and PTP Timer support Add ENETC instance 1~3, EMDIO and PTP Timer 0~1 support. The EMDIO provides MDIO bus for ENETCs to access their external PHYs. The PTP Timer provides current time with nanosecond resolution, precise periodic pulse, pulse on timeout, and time capture on external pulse support. It also provides PTP clock for ENETCs to implement time synchronization as required for IEEE 1588 and IEEE 802.1AS-2020. Signed-off-by: Wei Fang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 100 +++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index c8c3eff9df1a..8b348f2941fa 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -12,6 +12,9 @@ / { model = "NXP i.MX943 EVK board"; aliases { + ethernet0 = &enetc3; + ethernet1 = &enetc1; + ethernet2 = &enetc2; i2c2 = &lpi2c3; i2c3 = &lpi2c4; i2c5 = &lpi2c6; @@ -127,6 +130,30 @@ memory@80000000 { }; }; +&enetc1 { + clocks = <&scmi_clk IMX94_CLK_MAC4>; + clock-names = "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth3>; + phy-handle = <ðphy3>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc2 { + clocks = <&scmi_clk IMX94_CLK_MAC5>; + clock-names = "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth4>; + phy-handle = <ðphy4>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc3 { + status = "okay"; +}; + &lpi2c3 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c3>; @@ -396,6 +423,39 @@ &micfil { status = "okay"; }; +&netc_blk_ctrl { + assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>, + <&scmi_clk IMX94_CLK_MAC5>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>; + assigned-clock-rates = <250000000>, <250000000>; + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + ethphy3: ethernet-phy@6 { + reg = <0x6>; + realtek,clkout-disable; + }; + + ethphy4: ethernet-phy@7 { + reg = <0x7>; + realtek,clkout-disable; + }; +}; + +&netc_timer0 { + status = "okay"; +}; + +&netc_timer1 { + status = "okay"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>, @@ -431,6 +491,46 @@ &sai3 { }; &scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC 0x57e + IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO 0x97e + >; + }; + + pinctrl_eth3: eth3grp { + fsl,pins = < + IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3 0x50e + IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2 0x50e + IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1 0x50e + IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0 0x50e + IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL 0x51e + IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK 0x59e + IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL 0x51e + IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK 0x59e + IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0 0x51e + IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1 0x51e + IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2 0x51e + IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3 0x51e + >; + }; + + pinctrl_eth4: eth4grp { + fsl,pins = < + IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x50e + IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2 0x50e + IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1 0x50e + IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0 0x50e + IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL 0x51e + IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x59e + IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL 0x51e + IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x59e + IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0 0x51e + IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1 0x51e + IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2 0x51e + IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x51e + >; + }; pinctrl_ioexpander_int2: ioexpanderint2grp { fsl,pins = < From 3619c5b41ec57e2f6a9eefea1fdc759dbfdc1c67 Mon Sep 17 00:00:00 2001 From: Yashwanth Varakala Date: Mon, 17 Nov 2025 13:45:14 +0100 Subject: [PATCH 005/104] arm64: dts: imx8mp libra: add and update display overlays Add imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso devicetree display overlay for the i.MX8MP Libra RDK platform. The overlay enable LVDS display configuration. To keep the consistent style of panel and backlight nodes and labels. They are updated in imx8mp-libra base board devicetree and etml1010g3dra display overlay. Signed-off-by: Yashwanth Varakala Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 8 +++- ...8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso | 2 +- ...ibra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso | 44 +++++++++++++++++++ .../dts/freescale/imx8mp-libra-rdk-fpsc.dts | 4 +- 4 files changed, 53 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f30d3fd724d0..050f50890fd8 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -225,8 +225,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb -imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo -dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb +imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo +imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso index 1dcf249ca90d..02889d691c01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso @@ -34,7 +34,7 @@ &lvds_bridge { status = "okay"; }; -&panel0_lvds { +&panel_lvds0 { compatible = "edt,etml1010g3dra"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso new file mode 100644 index 000000000000..418c8536e791 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + pwms = <&pwm1 0 66667 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates = <0>, <465500000>; + status = "okay"; +}; + +&panel_lvds0 { + compatible = "powertip,ph128800t006-zhc01"; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts index 6f3a7b863dca..ec1f10022248 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts @@ -15,7 +15,7 @@ / { "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp"; model = "PHYTEC i.MX8MP Libra RDK FPSC"; - backlight_lvds0: backlight0 { + backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; pinctrl-0 = <&pinctrl_lvds0>; pinctrl-names = "default"; @@ -27,7 +27,7 @@ chosen { stdout-path = &uart4; }; - panel0_lvds: panel-lvds { + panel_lvds0: panel-lvds0 { /* compatible panel in overlay */ backlight = <&backlight_lvds0>; power-supply = <®_vdd_3v3>; From b105f62a35a9a2814675b7754a6aa8e4963f4df1 Mon Sep 17 00:00:00 2001 From: Yashwanth Varakala Date: Mon, 17 Nov 2025 13:45:15 +0100 Subject: [PATCH 006/104] arm64: dts: imx8mp libra: add peb-av-10 expansion board overlay Add an overlay of expansion board (PEB-AV-10) that supports multimedia interfaces, 3.5mm headphone jack, a USB-A port and LVDS, backlight connectors can be connected to the imx8mp libra. Audio works when no display is connected to expansion board. A separate overlay for Powertip display, based on peb-av-10.dtsi and intended for use with PEB-AV-10 expansion board, will be added later as display support is not yet available. Signed-off-by: Yashwanth Varakala Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 + .../imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi | 196 ++++++++++++++++++ .../imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso | 9 + 3 files changed, 208 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 050f50890fd8..18e6f8217ec4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -229,8 +229,11 @@ imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra-dtbs += imx8mp-libra-rdk-fpsc.dtb \ imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01-dtbs += imx8mp-libra-rdk-fpsc.dtb \ imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtbo +imx8mp-libra-rdk-fpsc-lvds-peb-av-10-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi new file mode 100644 index 000000000000..57bbbdd734e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include "imx8mp-pinfunc.h" + +&{/} { + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pinctrl-0 = <&pinctrl_lvds1>; + pinctrl-names = "default"; + power-supply = <®_vcc_12v>; + status = "disabled"; + }; + + panel_lvds1: panel-lvds1 { + backlight = <&backlight_lvds1>; + power-supply = <®_vdd_3v3>; + status = "disabled"; + + port { + panel1_in: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; + + reg_vcc_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VCC_12V"; + }; + + reg_vcc_1v8_audio: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC_1V8_Audio"; + }; + + reg_vcc_3v3_analog: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3_Analog"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,codec { + sound-dai = <&codec>; + }; + + dailink_master: simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: audio-codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + pinctrl-0 = <&pinctrl_tlv320>; + pinctrl-names = "default"; + #sound-dai-cells = <0>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_vcc_3v3_analog>; + DRVDD-supply = <®_vcc_3v3_analog>; + DVDD-supply = <®_vcc_1v8_audio>; + IOVDD-supply = <®_vdd_3v3>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_vdd_3v3>; + }; +}; + +&ldb_lvds_ch1 { + remote-endpoint = <&panel1_in>; +}; + +&pwm2 { + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; +}; + +&sai5 { + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-names = "default"; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", + "pll11k"; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2 + >; + }; + + pinctrl_lvds1: lvds1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x12 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x12 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 + >; + }; + + pinctrl_tlv320: tlv320grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso new file mode 100644 index 000000000000..803a199dffa3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include "imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi" From 0538ca1f102d87b2e98d38c7ca28915abee44777 Mon Sep 17 00:00:00 2001 From: Gregor Herburger Date: Mon, 17 Nov 2025 14:09:13 +0100 Subject: [PATCH 007/104] arm64: dts: ls1028a: Add mbls1028a and mbls1028a-ind devicetrees Add device trees for the MBLS1028A and the MBLS1028A-IND and the SoM TQMLS1028A. Signed-off-by: Gregor Herburger Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts | 68 +++++ .../fsl-ls1028a-tqmls1028a-mbls1028a.dts | 118 +++++++ .../fsl-ls1028a-tqmls1028a-mbls1028a.dtsi | 287 ++++++++++++++++++ .../dts/freescale/fsl-ls1028a-tqmls1028a.dtsi | 124 ++++++++ 5 files changed, 599 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 18e6f8217ec4..db3d56fc7db6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -16,6 +16,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-tqmls1028a-mbls1028a.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-tqmls1028a-mbls1028a-ind.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-tqmls1043a-mbls10xxa.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts new file mode 100644 index 000000000000..571b801c4f14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "fsl-ls1028a-tqmls1028a-mbls1028a.dtsi" + +/ { + model = "MBLS1028A-IND starterkit"; + compatible = "tq,ls1028a-tqmls1028a-mbls1028a-ind", "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; +}; + +&i2c5 { + gpio_exp_3v3: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + #gpio-cells = <2>; + gpio-controller; + + clk-intn-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + input; + line-name = "CLK_INT#"; + }; + + mpcie-waken-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "MPCIE_WAKE#"; + }; + + mpcie-disn-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_DIS#"; + }; + + mpcie-rstn-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_RST#"; + }; + + sata-perstn-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SATA_PERST#"; + }; + + dcdc-reset-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "DCDC_RESET"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts new file mode 100644 index 000000000000..02563f982ff8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include +#include "fsl-ls1028a-tqmls1028a-mbls1028a.dtsi" + +/ { + model = "MBLS1028A starterkit"; + compatible = "tq,ls1028a-tqmls1028a-mbls1028a", "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; + + gpio-beeper { + compatible = "gpio-beeper"; + gpios = <&gpio_exp_3v3 15 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-0 { + label = "S4"; + linux,code = ; + gpios = <&gpio_exp_3v3 11 GPIO_ACTIVE_LOW>; + }; + + button-1 { + label = "S5"; + linux,code = ; + gpios = <&gpio_exp_3v3 12 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio_exp_3v3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio_exp_3v3 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpio_exp_1v8 { + dcdc-reset-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "DCDC_RESET"; + output-low; + }; +}; + +&i2c5 { + gpio_exp_3v3: gpio@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3p3v>; + + clk-intn-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + input; + line-name = "CLK_INT#"; + }; + + mpcie-waken-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "MPCIE_WAKE#"; + }; + + mpcie-disn-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_DIS#"; + }; + + mpcie-rstn-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_RST#"; + }; + + sata-perstn-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SATA_PERST#"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi new file mode 100644 index 000000000000..cf338b2e8006 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +#include +#include +#include "fsl-ls1028a-tqmls1028a.dtsi" + +/ { + aliases { + crypto = &crypto; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + mmc0 = &esdhc; /* SD-Card */ + mmc1 = &esdhc1; /* eMMC */ + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = &duart0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 256 MiB */ + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&dspi2 { + bus-num = <2>; + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&esdhc { + cd-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + no-1-8-v; + bus-width = <4>; + status = "okay"; +}; + +/* When switched to baseboard-internal i2c bus, + * IIC5 has access to the following devices. + */ +&i2c4 { + /* TUSB8041 only supports 100 KHz, but it is not connected */ + clock-frequency = <400000>; + status = "okay"; + + /* SI5338 - set up in U-Boot */ + /* clockgen@70 */ +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + gpio_exp_1v8: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_1p8v>; + + ec1-intn-hog { + gpio-hog; + gpios = <0 0>; + input; + line-name = "EC1_INT#"; + }; + + sgmii-intn-hog { + gpio-hog; + gpios = <2 0>; + input; + line-name = "SGMII_INT#"; + }; + + qsgmii-intn-hog { + gpio-hog; + gpios = <4 0>; + input; + line-name = "QSGMII_INT#"; + }; + + qsgmii-rstn-hog { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "QSGMII_RESET#"; + }; + }; +}; + +&enetc_mdio_pf3 { + mdio0_rgmii_phy00: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + reset-gpios = <&gpio_exp_1v8 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <1>; + reset-deassert-us = <200>; + interrupt-parent = <&gpio_exp_1v8>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,clk-output-sel = ; + ti,fifo-depth = ; + }; + + mdio0_sgmii_phy03: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x03>; + reset-gpios = <&gpio_exp_1v8 3 GPIO_ACTIVE_LOW>; + /* + * Long reset to work around PHY incorrect strap pin sampling + * due to external capacitors for SGMII + */ + reset-assert-us = <2500>; + reset-deassert-us = <200>; + interrupt-parent = <&gpio_exp_1v8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + ti,clk-output-sel = ; + ti,fifo-depth = ; + }; + + qsgmii_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + qsgmii_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + qsgmii_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + qsgmii_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&enetc_port0 { + phy-handle = <&mdio0_sgmii_phy03>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <&mdio0_rgmii_phy00>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + +&mscc_felix { + status = "okay"; +}; + +/* l2switch ports */ +&mscc_felix_port0 { + phy-handle = <&qsgmii_phy1>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port1 { + phy-handle = <&qsgmii_phy2>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port2 { + phy-handle = <&qsgmii_phy3>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port3 { + phy-handle = <&qsgmii_phy4>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port4 { + ethernet = <&enetc_port2>; + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb0 { + /* dual role is implemented, but not a full featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3p3v>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3p3v>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi new file mode 100644 index 000000000000..dbf24dbc043b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +#include "fsl-ls1028a.dtsi" + +/ { + compatible = "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; + + reg_1p8v_som: regulator-1p8v-som { + compatible = "regulator-fixed"; + regulator-name = "1P8V_SOM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v_som: regulator-3p3v-som { + compatible = "regulator-fixed"; + regulator-name = "3P3V_SOM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + thermal-zones { + /* + * TQMLS1028A uses an external temperature sensor + * instead of TMU + */ + /delete-node/ ddr-controller; + + cluster-thermal { + thermal-sensors = <&sa56004_4c 1>; + }; + }; +}; + +&esdhc1 { + no-sdio; + no-sd; + non-removable; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width = <8>; + vmmc-supply = <®_3p3v_som>; + vqmmc-supply = <®_1p8v_som>; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <®_1p8v_som>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + js42_18: temperature-sensor@18 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x18>; + }; + + sa56004_4c: temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + #thermal-sensor-cells = <1>; + vcc-supply = <®_3p3v_som>; + }; + + se97_50: eeprom@50 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x50>; + pagesize = <16>; + vcc-supply = <®_3p3v_som>; + }; + + rtc1: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; + + m24c256_57: eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3p3v_som>; + }; +}; + +/* + * We use a separate sensor IC to measure core temperature. Disable the TMU + * as its driver can cause log spam outside of its measurement range (0-125C). + * + * Will have to be reevaluated if this DTS is ported to a mainline kernel, + * as both sensors of the TMU are referenced by the default LS1028A + * thermal-zones definitions there. + */ +&tmu { + status = "disabled"; +}; From 92ecc94b2786c71d52e193edad9fcb15cf1d923e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 20 Nov 2025 16:43:18 -0500 Subject: [PATCH 008/104] arm64: dts: mba8xx: replace 0 with IMX_LPCG_CLK_0 for lpcg indices Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the numerical value is identical, the LPCG input is defined as IMX_LPCG_CLK_, so using the symbolic constant improves clarity and consistency with the LPCG clock naming convention. Signed-off-by: Frank Li Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/mba8xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi index f534dab44e8e..e32519b156d9 100644 --- a/arch/arm64/boot/dts/freescale/mba8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8xx.dtsi @@ -232,7 +232,7 @@ &i2c1 { tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; - clocks = <&mclkout0_lpcg 0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; clock-names = "mclk"; iov-supply = <®_1v8>; ldoin-supply = <®_3v3>; @@ -343,7 +343,7 @@ &sai1 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&sai1_lpcg 0>; + <&sai1_lpcg IMX_LPCG_CLK_0>; assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; From 4ea67ed403d922e9ad6a1289967e6a0aa1b7e73f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 20 Nov 2025 16:53:50 -0500 Subject: [PATCH 009/104] arm64: dts: imx8qxp-mek: Add sensors under i2c1 bus Add sensors under i2c1 bus. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 523f48896b6b..50a97c0297c7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -485,12 +485,38 @@ i2c@2 { #size-cells = <0>; reg = <2>; + accelerometer@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; + + gyroscope@21 { + compatible = "nxp,fxas21002c"; + reg = <0x21>; + }; + pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; vdd-supply = <®_3v3>; vddio-supply = <®_3v3>; }; + + /* Ref SCH-54536 */ + inertial-meter@68 { + compatible = "invensense,icm20602"; + reg = <0x68>; + }; + + inertial-meter@69 { + compatible = "invensense,iam20380"; + reg = <0x69>; + }; + + pressure-sensor@77 { + compatible = "meas,ms5611"; + reg = <0x77>; + }; }; i2c@3 { @@ -520,6 +546,12 @@ light-sensor@44 { interrupt-parent = <&lsio_gpio1>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; }; + + /* Ref SCH-54536 */ + light-sensort@60 { + compatible = "vishay,vcnl4035"; + reg = <0x60>; + }; }; }; From 81c6b6ffbda1ad077896e719a23c09c8690f2a9b Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 21 Nov 2025 08:31:40 +0100 Subject: [PATCH 010/104] arm64: dts: tqma8xxs: replace 0 with IMX_LPCG_CLK_0 for lpcg indices Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the numerical value is identical, the LPCG input is defined as IMX_LPCG_CLK_, so using the symbolic constant improves clarity and consistency with the LPCG clock naming convention. Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/tqma8xxs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi index 2d0a329c2fa5..ebf20d5b5df9 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi @@ -406,7 +406,7 @@ &sai1 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&sai1_lpcg 0>; + <&sai1_lpcg IMX_LPCG_CLK_0>; assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; From 7834d199a7d7e49e4ccb6a2dd465febb683026f0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 21 Nov 2025 08:31:41 +0100 Subject: [PATCH 011/104] arm64: dts: tqma8xxs-mb-smarc-2: replace 0 with IMX_LPCG_CLK_0 for lpcg indices Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the numerical value is identical, the LPCG input is defined as IMX_LPCG_CLK_, so using the symbolic constant improves clarity and consistency with the LPCG clock naming convention. Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi index 3d20e3bf32ce..8bfe77113d64 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi @@ -130,7 +130,7 @@ &i2c0 { tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; - clocks = <&mclkout0_lpcg 0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; clock-names = "mclk"; iov-supply = <®_1v8>; ldoin-supply = <®_3v3>; From bb5b318f11e6f41c8cbb51848555f58b9ef175e6 Mon Sep 17 00:00:00 2001 From: Rogerio Pimentel Date: Sun, 23 Nov 2025 13:14:44 -0500 Subject: [PATCH 012/104] arm64: dts: add support for NXP i.MX8MP FRDM board The FRDM-i.MX8MP is an NXP development platform based on the i.MX8M Plus SoC, featuring a quad Cortex-A53, Cortex-M7 co-processor, 4GB LPDDR4, 32GB eMMC, Wi-Fi 6/Bluetooth 5.4/802.15.4 tri-radio, Ethernet, HDMI/MIPI display interfaces, camera connectors, and standard expansion headers. Based on the device tree found in the NXP repository at github https://github.com/nxp-imx-support/meta-imx-frdm and on imx8mp-evk board kernel mainline device tree. This is a basic device tree supporting: - Quad Cortex-A53 - 4GB LPDDR4 DRAM - PCA9450C PMIC with regulators - Two NXP PCAL6416 GPIO expanders - RGB LEDs via GPIO expander - I2C1, I2C2, I2C3 controllers - UART2 (console) and UART3 (with RTS/CTS) - USDHC3 (8-bit eMMC) - SNVS power key (onboard power button) Co-developed-by: Xiaofeng Wei Signed-off-by: Xiaofeng Wei Signed-off-by: Rogerio Pimentel Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 355 ++++++++++++++++++ 2 files changed, 356 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-frdm.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index db3d56fc7db6..862788fb3ea4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -214,6 +214,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts new file mode 100644 index 000000000000..55690f5e53d7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus FRDM board"; + compatible = "fsl,imx8mp-frdm", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + label = "red"; + gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "green"; + gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-2 { + label = "blue"; + gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0x40000000>; + }; +}; + +&A53_0 { + cpu-supply = <®_arm>; +}; + +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_arm: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6416_0: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416_0_int>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "CSI1_nRST", + "CSI2_nRST", + "DSI_CTP_RST", + "EXT_PWREN1", + "CAN_STBY", + "EXP_P0_5", + "EXP_P0_6", + "P0_7", + "LVDS0_BLT_EN", + "LVDS1_BLT_EN", + "LVDS0_CTP_RST", + "LVDS1_CTP_RST", + "SPK_PWREN", + "RLED_GPIO", + "GLED_GPIO", + "BLED_GPIO"; + }; + + pcal6416_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416_1_int>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "P0_0", + "P0_1", + "AUD_nINT", + "RTC_nINTA", + "USB1_SS_SEL", + "USB2_PWR_EN", + "SPI_EXP_SEL", + "P0_7", + "W2_HOST_WAKE_SD_3V3", + "W2_HOST_WAKE_BT_3V3", + "EXP_WIFI_BT_PDN_3V3", + "EXP_BT_RST_3V3", + "W2_RST_IND_3V3", + "SPI_nINT_3V3", + "KEYM_PCIE_nWAKE", + "P1_7"; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_pcal6416_0_int: pcal6416-0-int-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146 + >; + }; + + pinctrl_pcal6416_1_int: pcal6416-1-int-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; +}; From fb617c00e4ed993e85cb475a863a369fb9a27fe7 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Mon, 24 Nov 2025 01:22:42 -0800 Subject: [PATCH 013/104] arm64: dts: imx8mm: Add label to thermal-zones Add 'thermal_zones' as a label to the thermal-zones node. Without this label, it is not possible to add additional trip points in board files. For example, to add an active trip point for controlling a fan. Signed-off-by: Daniel Schultz Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index fc3cd639310e..9f49c0b386d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -234,7 +234,7 @@ timer { arm,no-tick-in-suspend; }; - thermal-zones { + thermal_zones: thermal-zones { cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; From a4f7357d5328cf6d005853a783229320d68d1f6a Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 26 Nov 2025 16:06:44 +0800 Subject: [PATCH 014/104] arm64: dts: imx943-evk: add flexcan support Add flexcan2 and flexcan4, and related phys support. Signed-off-by: Haibo Chen Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 44 ++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 8b348f2941fa..98938391497e 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -28,6 +28,22 @@ bt_sco_codec: bt-sco-codec { #sound-dai-cells = <1>; }; + flexcan2_phy: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&pcal6416_i2c6_u50 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + standby-gpios = <&pcal6416_i2c6_u50 4 GPIO_ACTIVE_LOW>; + }; + + flexcan4_phy: can-phy1 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&pcal6416_i2c3_u171 0 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + standby-gpios = <&pcal6416_i2c3_u171 1 GPIO_ACTIVE_LOW>; + }; + chosen { stdout-path = &lpuart1; }; @@ -154,6 +170,20 @@ &enetc3 { status = "okay"; }; +&flexcan2 { + phys = <&flexcan2_phy>; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan4 { + phys = <&flexcan4_phy>; + pinctrl-0 = <&pinctrl_flexcan4>; + pinctrl-names = "default"; + status = "okay"; +}; + &lpi2c3 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c3>; @@ -532,6 +562,20 @@ IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x51e >; }; + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX94_PAD_GPIO_IO34__CAN2_TX 0x39e + IMX94_PAD_GPIO_IO35__CAN2_RX 0x39e + >; + }; + + pinctrl_flexcan4: flexcan4grp { + fsl,pins = < + IMX94_PAD_GPIO_IO36__CAN4_TX 0x39e + IMX94_PAD_GPIO_IO37__CAN4_RX 0x39e + >; + }; + pinctrl_ioexpander_int2: ioexpanderint2grp { fsl,pins = < IMX94_PAD_CCM_CLKO4__GPIO4_IO3 0x31e From e00ac93be0121c866163094572d4517f2699ad3f Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 26 Nov 2025 04:42:18 -0800 Subject: [PATCH 015/104] arm64: dts: imx8ulp: add sim lpav node Add DT node for the SIM LPAV module. Reviewed-by: Daniel Baluta Reviewed-by: Frank Li Signed-off-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 13b01f3aa2a4..9b5d98766512 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -776,6 +776,23 @@ edma2: dma-controller@2d800000 { "ch28", "ch29", "ch30", "ch31"; }; + sim_lpav: clock-controller@2da50000 { + compatible = "fsl,imx8ulp-sim-lpav"; + reg = <0x2da50000 0x10000>; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; + clock-names = "bus", "core", "plat"; + #clock-cells = <1>; + #reset-cells = <1>; + + sim_lpav_mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; From adee0d6614349ab06e4a7766139803609a891fda Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 1 Dec 2025 15:58:43 +0900 Subject: [PATCH 016/104] arm64: dts: imx93-14x14-evk: Add bt-sco sound card support Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default. Signed-off-by: Chancel Liu Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-14x14-evk.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index f9eebd27d640..e47fee24471a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -27,6 +27,11 @@ aliases { serial0 = &lpuart1; }; + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + chosen { stdout-path = &lpuart1; }; @@ -168,6 +173,25 @@ reg_vref_1v8: regulator-adc-vref { regulator-max-microvolt = <1800000>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; @@ -371,6 +395,16 @@ &mu2 { status = "okay"; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -568,6 +602,15 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e From 4e6c3b68c1d51a74b65de9c2dfeb9734fbb8208a Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 1 Dec 2025 15:58:44 +0900 Subject: [PATCH 017/104] arm64: dts: imx93-14x14-evk: Add audio XCVR sound card Add audio XCVR sound card, which supports SPDIF TX & RX only, eARC RX, ARC RX are not supported. Signed-off-by: Chancel Liu Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-14x14-evk.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index e47fee24471a..61843b2c1b1b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -192,6 +192,19 @@ btcpu: simple-audio-card,cpu { }; }; + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; @@ -468,6 +481,17 @@ &wdog3 { status = "okay"; }; +&xcvr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + &iomuxc { pinctrl_flexcan1: flexcan1grp { fsl,pins = < @@ -611,6 +635,13 @@ MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e From b49f2dece02501c0684de70b7e00d1f7742aac88 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 1 Dec 2025 08:03:33 +0100 Subject: [PATCH 018/104] arm64: dts: tqmls1046a: Move BMAN/QMAN buffers to DRAM1 area DRAM1 is only 2GiB in size (0x00_8000_0000 - 0x01_0000_0000) which is already used by Linux kernel, etc. Move the allocation area of BMAN and QMAN to DRAM1 region. This frees the complete DRAM2 area for e.g. CMA. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi index fa543db99def..7059ab8bc9d4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi @@ -10,6 +10,18 @@ #include "fsl-ls1046a.dtsi" #include "tqmls10xxa.dtsi" +&bman_fbpr { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + +&qman_fqd { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + +&qman_pfdr { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + &qspi { num-cs = <2>; status = "okay"; From 21335bc94ac3a5ac1d5b4ef36a232256a3da2dbd Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 2 Dec 2025 14:04:33 +0800 Subject: [PATCH 019/104] arm64: dts: imx93-9x9-qsb: add CAN support overlay file CAN1 and Micfil share pins on imx93-9x9-qsb board, use TMUX1574RSVR to control the connection: put sel to high, select CAN1, put sel to low, select Micfil. In default, sel keep low. To support CAN1, need to put the sel to high. Besides, CAN1 use phy TJA1057GT/3. Signed-off-by: Haibo Chen Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx93-9x9-qsb-can1.dtso | 63 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 862788fb3ea4..f25bebabf558 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -382,7 +382,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb +imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso new file mode 100644 index 000000000000..0bf1e9d4bad2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&flexcan1 { + phys = <&flexcan_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; +}; + +/* micfi1 use the A port, conflict with can1 */ +&micfil { + status = "disabled"; +}; + +&pcal6524 { + /* + * mic-can-sel-hog have property 'output-low', dt overlay don't + * support /delete-property/. Both 'output-low' and 'output-high' + * will be exist under hog nodes if overlay file set 'output-high'. + * Workaround is disable this hog and create new hog with + * 'output-high'. + */ + mic-can-sel-hog { + status = "disabled"; + }; + + /* + * Config the MIC/CAN_SEL to high, chose B + * port, connect to CAN. + */ + mic-can-high-sel-hog { + gpio-hog; + gpios = <0x11 0x00>; + output-high; + }; +}; From c3085bef552f9cbf68b6b944bcad332c217fdf16 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:01 +0900 Subject: [PATCH 020/104] arm64: dts: imx91-11x11-evk: Refine label and node name of WM8962 Refine label with "wm8962" and node name with "codec" to follow devicetree specification. Signed-off-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index aca78768dbd4..90a4d1061d4a 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -132,7 +132,7 @@ &lpi2c1 { pinctrl-names = "default"; status = "okay"; - audio_codec: wm8962@1a { + wm8962: audio-codec@1a { compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clk IMX93_CLK_SAI3_GATE>; From 08a4d6fb6488136a96b390534f4f6d6e939a4622 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:02 +0900 Subject: [PATCH 021/104] arm64: dts: imx91-11x11-evk: Add bt-sco sound card support Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default. Signed-off-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91-11x11-evk.dts | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 90a4d1061d4a..c9cb122094e7 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -31,6 +31,11 @@ aliases { serial4 = &lpuart5; }; + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + chosen { stdout-path = &lpuart1; }; @@ -77,6 +82,25 @@ linux,cma { linux,cma-default; }; }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; }; &adc1 { @@ -372,6 +396,17 @@ bluetooth { }; }; +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { adp-disable; disable-over-current; @@ -528,6 +563,24 @@ MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1sleepgrp { + fsl,pins = < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e + >; + }; + pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e From 3529bf1c7d9e483967151ddb14c76a38c255a54e Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:03 +0900 Subject: [PATCH 022/104] arm64: dts: imx91-11x11-evk: Add WM8962 sound card support Add WM8962 sound card support which connects to SAI3. Signed-off-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91-11x11-evk.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index c9cb122094e7..6b26ecfd06c9 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -83,6 +83,22 @@ linux,cma { }; }; + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,name = "bt-sco-audio"; @@ -407,6 +423,17 @@ &sai1 { status = "okay"; }; +&sai3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-1 = <&pinctrl_sai3_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { adp-disable; disable-over-current; @@ -581,6 +608,26 @@ MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e + MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e + MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e + MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e + MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e + MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e + MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e + >; + }; + pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e From c85b67e2ab5f8f8a03d96cf8e082647066e312de Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:04 +0900 Subject: [PATCH 023/104] arm64: dts: imx91-11x11-evk: Add PDM microphone sound card support Add PDM micphone sound card support. This sound card supports recording sound from PDM microphone and convert the PDM format data to PCM data. Signed-off-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91-11x11-evk.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 6b26ecfd06c9..b0a295993dba 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -117,6 +117,20 @@ btcpu: simple-audio-card,cpu { dai-tdm-slot-width = <16>; }; }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; }; &adc1 { @@ -412,6 +426,16 @@ bluetooth { }; }; +&micfil { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-1 = <&pinctrl_pdm_sleep>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + &sai1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_sai1>; @@ -590,6 +614,22 @@ MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__PDM_CLK 0x31e + MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e + MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__GPIO1_IO8 0x51e + MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x51e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x51e + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e From 7b43479e4e1467ea3750d4cc5b12385ceec0364b Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:05 +0900 Subject: [PATCH 024/104] arm64: dts: imx91-11x11-evk: Add audio XCVR sound card support Add audio XCVR sound card, which supports SPDIF TX & RX only, eARC RX, ARC RX are not supported. Signed-off-by: Chancel Liu Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91-11x11-evk.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index b0a295993dba..03f460d62f7a 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -131,6 +131,19 @@ cpu { }; }; }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; }; &adc1 { @@ -523,6 +536,18 @@ &wdog3 { status = "okay"; }; +&xcvr { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-1 = <&pinctrl_spdif_sleep>; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -668,6 +693,20 @@ MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + + pinctrl_spdif_sleep: spdifsleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__GPIO2_IO22 0x51e + MX91_PAD_GPIO_IO23__GPIO2_IO23 0x51e + >; + }; + pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e From 749fdd12321d3fa0fb6118d315a8ec9b126f583f Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Fri, 5 Dec 2025 10:33:25 +0100 Subject: [PATCH 025/104] arm64: dts: imx8mp-phyboard-pollux: add fan-supply Add 5v regulator to gpio fan node. Reviewed-by: Frank Li Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 9687b4ded8f4..6203e39bc01b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -31,6 +31,7 @@ fan0: fan { compatible = "gpio-fan"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fan>; + fan-supply = <®_vcc_5v_sw>; gpio-fan,speed-map = <0 0 13000 1>; gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; From 26927206df533ef58c0123857fc4d17101e65b0a Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Fri, 5 Dec 2025 10:33:26 +0100 Subject: [PATCH 026/104] arm64: dts: imx8mp-phycore-som: add spi-nor supply vcc The spi flash on the SoM is missing its vcc supply definition. Add missing regulator which supplies the flash with 1.8V. Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 88831c0fbb7b..63adb1c4b3eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -28,6 +28,13 @@ reg_vdd_io: regulator-vdd-io { regulator-min-microvolt = <3300000>; regulator-name = "VDD_IO"; }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8"; + }; }; &A53_0 { @@ -83,6 +90,7 @@ som_flash: flash@0 { spi-max-frequency = <80000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <®_vdd_1v8>; }; }; From 18c783cf09aadf0eab9d6a75806f7aebe559080e Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Fri, 5 Dec 2025 10:33:27 +0100 Subject: [PATCH 027/104] arm64: dts: imx8mp-phyboard-pollux: Enable i2c3 The i2c3 of the phyBOARD-Pollux is used on the CSI1 interface to connect to imaging sensors. Thus define it so it can be easily enabled if required. Signed-off-by: Stefan Riedmueller Signed-off-by: Teresa Remmet Reviewed-by: Frank Li Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- .../freescale/imx8mp-phyboard-pollux-rdk.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 6203e39bc01b..7d34b820e321 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -228,6 +228,15 @@ led-3 { }; }; +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + &ldb_lvds_ch1 { remote-endpoint = <&panel1_in>; }; @@ -442,6 +451,20 @@ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2 + >; + }; + pinctrl_lvds1: lvds1grp { fsl,pins = < MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 From e4d60417f6f654bc5d3e0b074f48983861007d47 Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Fri, 5 Dec 2025 10:33:28 +0100 Subject: [PATCH 028/104] arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-05 expansion board PEB-WLBT-05 is an expansion board that provides WIFI and Bluetooth functionality. It features the Ezurio Sterling LWB module [1]. Add missing regulator to baseboard dts. [1] https://www.ezurio.com/wireless-modules/wifi-modules-bluetooth/sterling-lwb-24-ghz-wifi-4-bt-51-module Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 + .../imx8mp-phyboard-pollux-peb-wlbt-05.dtso | 108 ++++++++++++++++++ .../freescale/imx8mp-phyboard-pollux-rdk.dts | 7 ++ 3 files changed, 118 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f25bebabf558..e3027dc9e6c0 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -253,12 +253,15 @@ imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-ph128800t006.dtbo imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo +imx8mp-phyboard-pollux-wlbt-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-wlbt-05.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-wlbt.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-prt8ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso new file mode 100644 index 000000000000..0e98f4d94271 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include "imx8mp-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + wlbt_clock: clock-32768 { + compatible = "fixed-clock"; + clock-accuracy = <20000>; + clock-frequency = <32768>; + clock-output-names = "WIFIBT_SLOW_CLK"; + #clock-cells = <0>; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <250>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140 /* RTS */ + MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 /* CTS */ + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 /* RX */ + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 /* TX */ + >; + }; + + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x106 /* BT_DEV_WAKE_EXP */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x106 /* BT_REG_ON_EXP */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x106 /* BT_HOST_WAKE_EXP */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 /* SDIO_CLK */ + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 /* SDIO_CMD */ + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 /* SDIO_D0 */ + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 /* SDIO_D1 */ + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 /* SDIO_D2 */ + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 /* SDIO_D3 */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x106 /* WL_REG_ON_EXP */ + >; + }; +}; + +&uart3 { + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-0 = <&pinctrl_bluetooth>; + pinctrl-names = "default"; + clock-names = "lpo"; + clocks = <&wlbt_clock>; + device-wakeup-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + shutdown-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_vcc_3v3_sw>; + vddio-supply = <®_vcc_1v8_exp_con>; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; + bus-width = <4>; + max-frequency = <50000000>; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + vmmc-supply = <®_vcc_3v3_sw>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wifi>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 7d34b820e321..90ec73068a6d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -119,6 +119,13 @@ reg_vcc_3v3_sw: regulator-vcc-3v3-sw { regulator-max-microvolt = <3300000>; }; + reg_vcc_1v8_exp_con: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC_1V8_EXP_CON"; + }; + thermal-zones { soc-thermal { trips { From 8071668e66e523f36ea57b22f00a73ae63afc5f7 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 5 Dec 2025 19:22:54 +0100 Subject: [PATCH 029/104] arm64: dts: imx93-var-som-symphony: Update gpio aliases This patch introduces 2 simple aliases: Add a gpio3->gpio4 alias to allow flexible access to these GPIOs Add a gpio4 alias for the PCA9534 GPIO expander. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index c789c1f24bdc..00bdd3b91fdc 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -20,6 +20,8 @@ aliases { gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &pca9534; i2c0 = &lpi2c1; i2c1 = &lpi2c2; i2c2 = &lpi2c3; From 3860538ff7ee027f152d83084a036a84e2cb220b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 5 Dec 2025 19:22:55 +0100 Subject: [PATCH 030/104] arm64: dts: imx93-var-som-symphony: Add support for ft5x06 touch controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Symphony carrier board exposes a capacitive touch interface through an FFC/FPC connector. This interface is wired to an FT5x06 touch controller on the I2C bus when using Variscite’s 7-inch capacitive touch display. This patch adds the FT5x06 device node to describe the actual hardware connection and enables touch functionality on the Symphony board Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-var-som-symphony.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 00bdd3b91fdc..39bfbd0428a9 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -208,6 +208,21 @@ &lpi2c1 { sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; status = "okay"; + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio2>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + /* DS1337 RTC module */ rtc@68 { compatible = "dallas,ds1337"; @@ -272,6 +287,12 @@ &wdog3 { }; &iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e From e35fffafd8a4e960296b017a461081bd6bff7cda Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 5 Dec 2025 19:22:56 +0100 Subject: [PATCH 031/104] arm64: dts: imx93-var-som-symphony: Add USB support The Symphony carrier board includes a USB Type-C connector on the USB1 port through an NXP PTN5150 Type-C controller connected on the I2C bus. The PTN5150 provides cable orientation detection and role switching information to the USB controller. This patch adds the PTN5150 node, its interrupt line, the required pin muxing, and wires the controller to the USB1 OTG dual-role device using the USB role-switch framework. This patch adds also USB2 support, that remains in host-only mode, matching the hardware capabilities of the Symphony board. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-var-som-symphony.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 39bfbd0428a9..ee69d6b268a4 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -251,6 +251,22 @@ pca9534: gpio@20 { #gpio-cells = <2>; wakeup-source; }; + + /* USB Type-C Controller */ + ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_NONE>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; }; /* Console */ @@ -267,6 +283,29 @@ &lpuart6 { status = "okay"; }; +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + /* SD */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -351,6 +390,12 @@ MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e >; }; + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e From 4139384b586b916c8826483331f0054a65767f97 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 5 Dec 2025 19:22:57 +0100 Subject: [PATCH 032/104] arm64: dts: imx93-var-som-symphony: Enable LPSPI6 controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the LPSPI6 controller so it can be used by user applications through the board’s expansion connector. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-var-som-symphony.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index ee69d6b268a4..c0842fb3cfa3 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -276,6 +276,13 @@ &lpuart1 { status = "okay"; }; +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + /* J18.7, J18.9 */ &lpuart6 { pinctrl-names = "default"; @@ -384,6 +391,15 @@ MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e >; }; + pinctrl_lpspi6: lpspi6grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x31e + MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x31e + MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x31e + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e From 99bd26b4e5dc12854404bce585b33a9c28c30d3d Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 09:57:46 +0100 Subject: [PATCH 033/104] arm64: dts: freescale: imx8-apalis: Add ethernet alias Add alias for the apalis first ethernet interface, this ensures consistent interface naming (e.g. `end0`) and this is used by the firmware to correctly set the MAC address. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 9153dddfd3b8..6fc82b5eb58c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -6,6 +6,10 @@ #include / { + aliases { + ethernet0 = &fec1; + }; + chosen { stdout-path = &lpuart1; }; From 98b8de62e846617cdb75c0f480d35cb37d3bc447 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 11:17:49 +0100 Subject: [PATCH 034/104] arm64: dts: freescale: imx8mp-verdin: Remove obsolete TODO comments Remove obsolete TODO comments, I2S interface is supported since Linux v6.6. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index d43ba0087126..d31f8082394f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -832,10 +832,6 @@ &pwm3 { #pwm-cells = <3>; }; -/* TODO: Verdin I2S_1 */ - -/* TODO: Verdin I2S_2 */ - &snvs_pwrkey { status = "okay"; }; From 9cd778b49692bcdff5d709bd78190aa61a70193c Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 11:17:50 +0100 Subject: [PATCH 035/104] arm64: dts: freescale: imx8mp-verdin: enable hdmi_pai device Enable the hdmi_pai device on the various iMX8M Plus Verdin boards that feature the related HDMI interface. The hdmi_pai device, together with aud2htx module, hdmi_pai and hdmi controller compose the HDMI audio pipeline. See commit b21f87b8322f ("arm64: dts: imx8mp-evk: enable hdmi_pai device") for the equivalent change on the NXP i.MX8MP EVK board. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 1493319aa748..0e218e6b8e29 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -112,6 +112,10 @@ &gpio4 { }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index a38e7c947a42..72a4f846d694 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -121,6 +121,10 @@ &gpio_expander_21 { }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi index 11cf3bdc95c4..846b36706821 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi @@ -109,6 +109,10 @@ &flexcan2 { }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index cc389cda2af2..f3d28e23ba6c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -123,6 +123,10 @@ &gpio4 { }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; From 53fb7a3aa55e7ce3968fa74982847872b08a6830 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 11:17:51 +0100 Subject: [PATCH 036/104] arm64: dts: freescale: imx8mp-toradex-smarc: enable hdmi_pai device Enable the hdmi_pai device on the Toradex SMARC iMX8M Plus Development boards. The hdmi_pai device, together with aud2htx module, hdmi_pai and hdmi controller compose the HDMI audio pipeline. See commit b21f87b8322f ("arm64: dts: imx8mp-evk: enable hdmi_pai device") for the equivalent change on the NXP i.MX8MP EVK board. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts index 6f9dcd3a75c8..b31de307093c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts @@ -107,6 +107,10 @@ &gpio4 { pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; From 2b1f623fc83dcbd8820fed3cec73c9138e27a246 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:07 +0100 Subject: [PATCH 037/104] arm64: dts: tqma8mpql-mba8mpxl: Adjust copyright text format Replace personal mail address by mailing list. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 59642a8a2c44..0605cf2faf83 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2021-2022 TQ-Systems GmbH - * Author: Alexander Stein + * Copyright 2021-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein */ /dts-v1/; From 3494d778e8d1eff06f0636531379b2ae40e5a2e1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:08 +0100 Subject: [PATCH 038/104] arm64: dts: tqma8mpql-mba8mpxl: Fix Ethernet PHY IRQ support Ethernet PHY interrupt mode is level triggered. Adjust the mode accordingly. Reviewed-by: Andrew Lunn Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 0605cf2faf83..ff2bacf24bfd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -345,7 +345,7 @@ ethphy3: ethernet-phy@3 { reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -375,7 +375,7 @@ ethphy0: ethernet-phy@0 { reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; }; }; }; From 8401527abb5e3a00c867b6597b8e1b29c80c9824 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:09 +0100 Subject: [PATCH 039/104] arm64: dts: tqma8mpql-mba8mpxl: Fix HDMI CEC pad control settings As per datasheet of the HDMI protection IC the CEC_IC pin has been configured as open-drain. Fixes: 418d1d840e42 ("arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP") Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ff2bacf24bfd..03b75d4cf699 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -868,7 +868,7 @@ pinctrl_hdmi: hdmigrp { fsl,pins = , , , - ; + ; }; pinctrl_hoggpio2: hoggpio2grp { From 251f9c7ce592e3556a50a7547928262cbfd6d50e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:10 +0100 Subject: [PATCH 040/104] arm64: dts: tqma8mpql-mba8mpxl: Add HDMI audio output support Add the HDMI audio soundcard and enable necessary nodes. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 03b75d4cf699..ac889a69da69 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -248,6 +248,13 @@ sound { "Line Out Jack", "LOR"; }; + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + thermal-zones { soc-thermal { trips { @@ -290,6 +297,10 @@ map3 { }; }; +&aud2htx { + status = "okay"; +}; + &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -486,6 +497,10 @@ &gpio5 { "", "", "", ""; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; From 5c50503db36df8ed6d1e54f45ee6ea1bdbb5ca7d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:11 +0100 Subject: [PATCH 041/104] arm64: dts: tqma8mpql-mba8mpxl: Configure IEEE 1588 event out signal The event out signal on channel 2 is available on pad SAI2_RXD0 which is connected to X63 pin 13. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ac889a69da69..fdfe246c5640 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -807,7 +807,8 @@ pinctrl_eqos: eqosgrp { , , , - ; + , + ; }; pinctrl_eqos_event: eqosevtgrp { From 38bbf7903e8016587f62b614dffc757ff33889a1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:12 +0100 Subject: [PATCH 042/104] arm64: dts: tqma8mpql-mba8mp-ras314: Fix Ethernet PHY IRQ support Ethernet PHY interrupt mode is level triggered. Adjust the mode accordingly. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index f7346b3d35fe..67fe1f63fd93 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -190,7 +190,7 @@ ethphy3: ethernet-phy@3 { reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; @@ -222,7 +222,7 @@ ethphy0: ethernet-phy@0 { reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; From 53a5c1d98d1155ece4c9446c0fea55e17d08774a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:13 +0100 Subject: [PATCH 043/104] arm64: dts: tqma8mpql-mba8mp-ras314: Fix HDMI CEC pad control settings As per datasheet of the HDMI protection IC the CEC_IC pin has been configured as open-drain. Fixes: ddabb3ce3f90 ("arm64: dts: freescale: add TQMa8MPQL on MBa8MP-RAS314") Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index 67fe1f63fd93..30f0e81c4be0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -704,7 +704,7 @@ pinctrl_hdmi: hdmigrp { fsl,pins = , , , - ; + ; }; pinctrl_gpt1: gpt1grp { From ad7b5ed46c6815f2b9930d1a10b0cfa78695b495 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:14 +0100 Subject: [PATCH 044/104] arm64: dts: tqma8mpql-mba8mp-ras314: Add HDMI audio output support Add the HDMI audio soundcard and enable necessary nodes. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index 30f0e81c4be0..6e927ff1e967 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -159,6 +159,17 @@ sound { "Headphone Jack", "HPL", "Headphone Jack", "HPR"; }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; +}; + +&aud2htx { + status = "okay"; }; &ecspi3 { @@ -335,6 +346,10 @@ &gpt3 { status = "disabled"; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; From 4f0cee99186c452c7f51f41f6e8f63bf2f990428 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 9 Dec 2025 12:58:28 -0800 Subject: [PATCH 045/104] arm64: dts: imx8m{m,p}-venice-gw71xx: Add Magetometer Add support for the optional LIS2MDL magnetometer on GW71xx baseboards. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 15 +++++++++++++++ .../boot/dts/freescale/imx8mp-venice-gw71xx.dtsi | 15 +++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 429be2bab8a2..320806d3d073 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -92,6 +92,15 @@ accelerometer@19 { interrupt-parent = <&gpio4>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>; }; + + magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; }; /* off-board header */ @@ -174,6 +183,12 @@ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x159 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi index 4bf818873fe3..9317e62304e3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi @@ -101,6 +101,15 @@ accelerometer@19 { interrupt-parent = <&gpio4>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; }; + + magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio4>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + }; }; &pcie_phy { @@ -198,6 +207,12 @@ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x150 /* IRQ */ + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ From 51eea410b977a071ee99593427e08b421d250188 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Dec 2025 17:57:19 +0800 Subject: [PATCH 046/104] arm64: dts: imx95-15x15-evk: Use phys to replace xceiver-supply The TJA1051T/3 used on i.MX95-15x15-EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li Acked-by: Marc Kleine-Budde Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index c1e245ecea9c..b934295bac15 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -107,12 +107,11 @@ reg_audio_switch1: regulator-audio-switch1 { gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>; }; - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can2-stby"; - gpio = <&pcal6524 14 GPIO_ACTIVE_LOW>; + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 14 GPIO_ACTIVE_HIGH>; }; reg_m2_pwr: regulator-m2-pwr { @@ -318,7 +317,7 @@ &enetc_port1 { &flexcan2 { pinctrl-0 = <&pinctrl_flexcan2>; pinctrl-names = "default"; - xceiver-supply = <®_can2_stby>; + phys = <&flexcan2_phy>; status = "okay"; }; From 3563aaa006af39f4072e114c883f2363cd26b51f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Dec 2025 17:57:20 +0800 Subject: [PATCH 047/104] arm64: dts: imx8mp-evk: Use phys to replace xceiver-supply The TJA1048 used on i.MX8MP-EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li Acked-by: Marc Kleine-Budde Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 43 ++++++-------------- 1 file changed, 13 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index c6facb2ad9aa..7ededc1a0617 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -56,6 +56,16 @@ memory@40000000 { <0x1 0x00000000 0 0xc0000000>; }; + flexcan_phy: can-phy { + compatible = "nxp,tja1048"; + #phy-cells = <1>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_phy>; + standby-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + native-hdmi-connector { compatible = "hdmi-connector"; label = "HDMI OUT"; @@ -103,28 +113,6 @@ reg_audio_pwr: regulator-audio-pwr { enable-active-high; }; - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - regulator-name = "can1-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_pcie0: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -431,14 +419,14 @@ ethphy1: ethernet-phy@1 { &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; + phys = <&flexcan_phy 0>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; + phys = <&flexcan_phy 1>; status = "disabled";/* can2 pin conflict with pdm */ }; @@ -909,14 +897,9 @@ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 >; }; - pinctrl_flexcan1_reg: flexcan1reggrp { + pinctrl_flexcan_phy: flexcanphygrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ >; }; From 753f9460a645296f656bf7fd4a85f55c411561fb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Dec 2025 17:57:21 +0800 Subject: [PATCH 048/104] arm64: dts: imx93-11x11-evk: Use phys to replace xceiver-supply The TJA1057 used on i.MX93 EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li Acked-by: Marc Kleine-Budde Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index b94a24193e19..8dd5340e8141 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -81,6 +81,13 @@ vdevbuffer: vdevbuffer@a4020000 { }; + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>; + }; + reg_vdd_12v: regulator-vdd-12v { compatible = "regulator-fixed"; regulator-name = "VDD_12V"; @@ -106,14 +113,6 @@ reg_audio_pwr: regulator-audio-pwr { enable-active-high; }; - reg_can2_standby: regulator-can2-standby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&adp5585 6 GPIO_ACTIVE_LOW>; - }; - reg_m2_pwr: regulator-m2-pwr { compatible = "regulator-fixed"; regulator-name = "M.2-power"; @@ -302,7 +301,7 @@ ethphy2: ethernet-phy@2 { &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_standby>; + phys = <&flexcan_phy>; status = "okay"; }; From 057ffbb1cfffbbf56eee68b5ebdcfdfa89adad40 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:48 +0100 Subject: [PATCH 049/104] arm64: dts: imx8mp-var-som: Move USDHC2 support to Symphony carrier The VAR-SOM-MX8MP module does not include a microSD slot connected to USDHC2. The USDHC2 interface is routed only on the Symphony carrier board, and it may optionally be used or omitted depending on the customer's carrier design. Move the USDHC2 node, its regulators, pinctrl groups and related GPIOs from the SOM device tree to the Symphony carrier DTS, keeping the SOM description limited to hardware populated on the module. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-var-som-symphony.dts | 77 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-var-som.dtsi | 75 ------------------ 2 files changed, 77 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 36d3eb865202..ea3c193bb684 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -8,4 +8,81 @@ / { model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp"; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + regulator-name = "VSD_VSEL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0 1800000 0x1>; + vin-supply = <&ldo5>; + }; +}; + +/* SD-card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 29f080904482..949d9878f395 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -35,27 +35,6 @@ memory@40000000 { <0x1 0x00000000 0 0xc0000000>; }; - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; - - reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { - compatible = "regulator-gpio"; - regulator-name = "VSD_VSEL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - states = <3300000 0x0 1800000 0x1>; - vin-supply = <&ldo5>; - }; - reg_phy_supply: regulator-phy-supply { compatible = "regulator-fixed"; regulator-name = "phy-supply"; @@ -271,19 +250,6 @@ &uart2 { status = "okay"; }; -/* SD-card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - bus-width = <4>; - status = "okay"; -}; - /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -358,47 +324,6 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 >; }; - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 From 5ea98ce8b11969bae1441b5648b73242a9b99386 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:49 +0100 Subject: [PATCH 050/104] arm64: dts: imx8mp-var-som: Move PCA9534 GPIO expander to Symphony carrier The VAR-SOM-MX8MP module does not include the PCA9534 GPIO expander nor the LED connected to it. These components are present only on the Symphony carrier board and may vary across custom carrier designs. Move the PCA9534 GPIO expander node and the associated LED definition from the SOM device tree to the Symphony carrier DTS, ensuring the SOM dtsi describes only hardware present on the module. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-var-som-symphony.dts | 50 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-var-som.dtsi | 50 ------------------- 2 files changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index ea3c193bb684..361e6122bdc3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -9,6 +9,16 @@ / { model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp"; + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -31,6 +41,33 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { }; }; +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + + usb3-sata-sel-hog { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "usb3_sata_sel"; + }; + }; +}; + /* SD-card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -45,6 +82,19 @@ &usdhc2 { }; &iomuxc { + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 + >; + }; + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 949d9878f395..158a78ec9656 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -19,16 +19,6 @@ chosen { stdout-path = &uart2; }; - gpio-leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, @@ -216,33 +206,6 @@ ldo5: LDO5 { }; }; -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - /* GPIO expander */ - pca9534: gpio@20 { - compatible = "nxp,pca9534"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9534>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - - usb3-sata-sel-hog { - gpio-hog; - gpios = <4 0>; - output-low; - line-name = "usb3_sata_sel"; - }; - }; -}; - /* Console */ &uart2 { pinctrl-names = "default"; @@ -298,19 +261,6 @@ MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x400001c2 >; }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pca9534: pca9534grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 - >; - }; - pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 From e5b8c6103a41ada6c40ff052c572cc811b45b32c Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:50 +0100 Subject: [PATCH 051/104] arm64: dts: imx8mp-var-som: Move UART2 description to Symphony carrier The VAR-SOM-MX8MP module does not provide an onboard debug console. UART2 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART. Move the UART2 node from the SOM device tree to the imx8mp-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-var-som-symphony.dts | 18 ++++++++++++++++++ .../boot/dts/freescale/imx8mp-var-som.dtsi | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 361e6122bdc3..291f65e36865 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -9,6 +9,10 @@ / { model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp"; + chosen { + stdout-path = &uart2; + }; + gpio-leds { compatible = "gpio-leds"; @@ -68,6 +72,13 @@ usb3-sata-sel-hog { }; }; +/* Console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + /* SD-card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -95,6 +106,13 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 >; }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 158a78ec9656..5bba91dcef17 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -15,10 +15,6 @@ / { model = "Variscite VAR-SOM-MX8M Plus module"; - chosen { - stdout-path = &uart2; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, @@ -206,13 +202,6 @@ ldo5: LDO5 { }; }; -/* Console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -267,13 +256,6 @@ MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 From 84095b3bd0cc836a112c8a1774edc7ea6fa43f69 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:51 +0100 Subject: [PATCH 052/104] arm64: dts: imx8mp-var-som: Add WiFi and Bluetooth support Add device tree nodes for the WiFi and Bluetooth module mounted on the VAR-SOM-MX8MP. The module can be based on either the NXP IW612 or IW611 chipset, depending on the configuration chosen by the customer. Regardless of the chipset used, WiFi communicates over SDIO and Bluetooth over UART. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-var-som.dtsi | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 5bba91dcef17..2c49d53e30c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -21,6 +21,14 @@ memory@40000000 { <0x1 0x00000000 0 0xc0000000>; }; + iw61x_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 19 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; + reg_phy_supply: regulator-phy-supply { compatible = "regulator-fixed"; regulator-name = "phy-supply"; @@ -202,6 +210,33 @@ ldo5: LDO5 { }; }; +/* BT */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bluetooth>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + mmc-pwrseq = <&iw61x_pwrseq>; + status = "okay"; +}; + /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -222,6 +257,14 @@ &wdog1 { &iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0 + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0 + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0xc0 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -256,6 +299,48 @@ MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 @@ -309,4 +394,11 @@ pinctrl_wdog: wdoggrp { MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 >; }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0xc0 + >; + }; }; From cb452cc24ade40ebf3f0c592e1bad17c1b3cd693 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:52 +0100 Subject: [PATCH 053/104] arm64: dts: imx8mp-var-som: Add support for WM8904 audio codec The VAR-SOM-MX8MP can integrate the WM8904, a high-performance ultra-low-power stereo codec optimized for portable audio applications. This patch adds the WM8904 device to the appropriate I2C bus, enables the SAI peripheral, and introduces the sound node to expose the sound card to the system. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-var-som.dtsi | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 2c49d53e30c3..6da5df11c44a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -29,6 +29,14 @@ iw61x_pwrseq: wifi-pwrseq { <&gpio2 19 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ }; + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_phy_supply: regulator-phy-supply { compatible = "regulator-fixed"; regulator-name = "phy-supply"; @@ -46,6 +54,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; }; &A53_0 { @@ -208,6 +244,52 @@ ldo5: LDO5 { }; }; }; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <®_audio_supply>; + CPVDD-supply = <®_audio_supply>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <®_audio_supply>; + MICVDD-supply = <®_audio_supply>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <11536000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; }; /* BT */ @@ -299,6 +381,18 @@ MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 From e583afbe3568c654a221793019e77738ffd2946f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:53 +0100 Subject: [PATCH 054/104] arm64: dts: imx8mp-var-som: Add support for TSC2046 touchscreen The VAR-SOM-MX8MP integrates a TSC2046 resistive touchscreen controller. The controller is physically located on the SOM, and its signals are routed to the SOM pins, allowing carrier boards to make use of it. This patch adds the TSC2046 node and the appropriate SPI controller. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-var-som.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 6da5df11c44a..49467b48d0b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -100,6 +100,37 @@ &A53_3 { cpu-supply = <&buck2>; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + tsc2046: touchscreen@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -347,6 +378,15 @@ MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0xc0 >; }; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x12 + MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x12 + MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x12 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x12 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -381,6 +421,12 @@ MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 >; }; + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0xc0 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 From fcef3fa00fcecc88b45526f83ea4df73d0e7dc77 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:31:04 +0100 Subject: [PATCH 055/104] arm64: dts: imx8mm-tqma8mqml: remove virtual 3.3V regulator BUCK4 rail supplies the 3.3V rail. Use the actual regulator instead of a virtual fixed regulator. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index b82e9790ea20..16ed8ce5b5c4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -24,14 +24,6 @@ reg_vcc1v8: regulator-vcc1v8 { regulator-max-microvolt = <1800000>; }; - /* identical to buck4_reg, but should never change */ - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -223,14 +215,14 @@ eeprom1: eeprom@53 { read-only; reg = <0x53>; pagesize = <16>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; }; @@ -253,7 +245,7 @@ &usdhc3 { non-removable; no-sd; no-sdio; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <&buck4_reg>; vqmmc-supply = <®_vcc1v8>; status = "okay"; }; From c5d2ecfe495e102fc6c29b3c76dba6b88153d1e0 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:31:05 +0100 Subject: [PATCH 056/104] arm64: dts: imx8mm-tqma8mqml: remove virtual 1.8V regulator BUCK5 regulator supplies the 1.8V rail. Use the actual regulator instead of a virtual fixed regulator. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 16ed8ce5b5c4..6e63cf8beadc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -16,14 +16,6 @@ memory@40000000 { reg = <0x00000000 0x40000000 0 0x40000000>; }; - /* e-MMC IO, needed for HS modes */ - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -246,7 +238,7 @@ &usdhc3 { no-sd; no-sdio; vmmc-supply = <&buck4_reg>; - vqmmc-supply = <®_vcc1v8>; + vqmmc-supply = <&buck5_reg>; status = "okay"; }; From 7c9910ffdadb42428c96fa73715f292a445b3a37 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:31:06 +0100 Subject: [PATCH 057/104] arm64: dts: imx8mm-tqma8mqml: remove superfluous line Remove one empty line that is not needed. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 6e63cf8beadc..2e3860a5f4fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -195,7 +195,6 @@ ldo5_reg: LDO5 { }; }; - pcf85063: rtc@51 { compatible = "nxp,pcf85063a"; reg = <0x51>; From f7a65b08bcf5edb95697cf7a10435a1d051c9268 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:31:07 +0100 Subject: [PATCH 058/104] arm64: dts: imx8mm-tqma8mqml: fix LDO5 power off Fix SD card removal caused by automatic LDO5 power off after boot. To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled regulator that is supplied by LDO5. Since this is implemented on SoM but used on baseboards with SD-card interface, implement the functionality on SoM part and optionally enable it on baseboards if needed. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 13 ++++++----- .../boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 22 +++++++++++++++++++ 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index b941c8c4f7bb..8dcc5cbcb8f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -101,6 +101,10 @@ &pcie0 { status = "okay"; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MM_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; @@ -276,8 +280,7 @@ pinctrl_usdhc2: usdhc2grp { , , , - , - ; + ; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -286,8 +289,7 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { , , , - , - ; + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -296,7 +298,6 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { , , , - , - ; + ; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 2e3860a5f4fd..29b298af0d73 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -16,6 +16,20 @@ memory@40000000 { reg = <0x00000000 0x40000000 0 0x40000000>; }; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5_reg>; + status = "disabled"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -227,6 +241,10 @@ &pcie_phy { fsl,clkreq-unsupported; }; +&usdhc2 { + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -281,6 +299,10 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = ; }; + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = ; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = , , From cd09cbebfc8a4c76d74c2e7e1818a4c8cf3ca033 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:39:23 +0100 Subject: [PATCH 059/104] arm64: dts: imx8mn-tqma8mqnl: remove virtual 3.3V regulator BUCK4 rail supplies the 3.3V rail. Use the actual regulator instead of a virtual fixed regulator. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 1d23814e11cd..34d6415348f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -23,13 +23,6 @@ reg_vcc1v8: regulator-vcc1v8 { regulator-max-microvolt = <1800000>; }; - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXNL_VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -217,14 +210,14 @@ eeprom1: eeprom@53 { read-only; reg = <0x53>; pagesize = <16>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; }; @@ -242,7 +235,7 @@ &usdhc3 { non-removable; no-sd; no-sdio; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <&buck4_reg>; vqmmc-supply = <®_vcc1v8>; status = "okay"; }; From 8b6ffe54fde2375efdc034e253e71e8988da3c54 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:39:24 +0100 Subject: [PATCH 060/104] arm64: dts: imx8mn-tqma8mqnl: remove virtual 1.8V regulator BUCK5 regulator supplies the 1.8V rail. Use the actual regulator instead of a virtual fixed regulator. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 34d6415348f8..ac6ce5d814c5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -15,14 +15,6 @@ memory@40000000 { reg = <0x00000000 0x40000000 0 0x40000000>; }; - /* e-MMC IO, needed for HS modes */ - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXNL_VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -236,7 +228,7 @@ &usdhc3 { no-sd; no-sdio; vmmc-supply = <&buck4_reg>; - vqmmc-supply = <®_vcc1v8>; + vqmmc-supply = <&buck5_reg>; status = "okay"; }; From 8adc841d43ebceabec996c9dcff6e82d3e585268 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:39:25 +0100 Subject: [PATCH 061/104] arm64: dts: imx8mn-tqma8mqnl: fix LDO5 power off Fix SD card removal caused by automatic LDO5 power off after boot To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled regulator that is supplied by LDO5. Since this is implemented on SoM but used on baseboards with SD-card interface, implement the functionality on SoM part and optionally enable it on baseboards if needed. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts | 13 ++++++----- .../boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 22 +++++++++++++++++++ 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index d7f7f9aafb7d..0d009f4be804 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -69,6 +69,10 @@ &mipi_dsi { samsung,esc-clock-frequency = <20000000>; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MN_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; @@ -216,8 +220,7 @@ pinctrl_usdhc2: usdhc2grp { , , , - , - ; + ; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -226,8 +229,7 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { , , , - , - ; + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -236,8 +238,7 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { , , , - , - ; + ; }; pinctrl_usdhc2_gpio: usdhc2-gpiogrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index ac6ce5d814c5..31a3ca137e63 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -15,6 +15,20 @@ memory@40000000 { reg = <0x00000000 0x40000000 0 0x40000000>; }; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5_reg>; + status = "disabled"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -218,6 +232,10 @@ &mipi_dsi { vddio-supply = <&ldo3_reg>; }; +&usdhc2 { + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -272,6 +290,10 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = ; }; + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = ; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = , , From 30e6d444b8dc5ae1f5dee1f3cda3a49864cd10fb Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 17 Dec 2025 09:48:04 +0100 Subject: [PATCH 062/104] arm64: dts: mb-smarc-2: Add PCIe support TQMa8XxS on MB-SMARC-2 supports mPCIe on X44. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi | 10 ++++++++++ arch/arm64/boot/dts/freescale/tqma8xxs.dtsi | 14 +++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi index 8bfe77113d64..050ae23c4dc1 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi @@ -126,6 +126,12 @@ &flexcan3 { status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &i2c0 { tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; @@ -156,6 +162,10 @@ &lpuart3 { status = "okay"; }; +&pcieb { + status = "okay"; +}; + ®_sdvmmc { off-on-delay-us = <200000>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi index ebf20d5b5df9..bfc918f18d01 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi @@ -402,6 +402,14 @@ &mu1_m0 { status = "okay"; }; +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &sai1 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, @@ -646,9 +654,9 @@ pinctrl_i2c0_gpio_mipi_lvds0: mipi-lvds0-i2c0-gpiogrp { }; pinctrl_pcieb: pcieagrp { - fsl,pins = , - , - ; + fsl,pins = , + , + ; }; pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp { From eb2f28413e23c219188d3e1a2ce8bca9894f9832 Mon Sep 17 00:00:00 2001 From: Fabian Pflug Date: Thu, 18 Dec 2025 12:39:22 +0100 Subject: [PATCH 063/104] arm64: dts: freescale: add support for NXP i.MX93 FRDM The FRDM i.MX 93 development board is a low-cost and compact development board featuring the i.MX93 applications processor. It features: - Dual Cortex-A55 - 2 GB LPDDR4X / LPDDR4 - 32 GB eMMC5.1 - MicroSD slot - GbE RJ45 x 2 - USB2.0 1x Type C, 1x Type A This file is based upon the one provided by nxp in their own kernel and yocto meta layer for the device, but adapted for mainline. Signed-off-by: Haidong Zheng Signed-off-by: Danwei Luo Signed-off-by: Lei Xu Signed-off-by: Fabian Pflug Reviewed-by: Francesco Valla Tested-by: Francesco Valla Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx93-11x11-frdm.dts | 620 ++++++++++++++++++ 2 files changed, 621 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index e3027dc9e6c0..edb8332ed7e0 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -391,6 +391,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts new file mode 100644 index 000000000000..066c5139842b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts @@ -0,0 +1,620 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/dts-v1/; + +#include +#include "imx93.dtsi" + +/ { + compatible = "fsl,imx93-11x11-frdm", "fsl,imx93"; + model = "NXP i.MX93 11X11 FRDM board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; /* EMMC */ + mmc1 = &usdhc2; /* uSD */ + rtc0 = &pcf2131; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + vin-supply = <&buck4>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4010000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; +}; + +&adc1 { + vref-supply = <&buck5>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&cm33 { + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + /* does not boot with supplier set, because it is the bucks interrupt parent */ + /* vcc-supply = <&buck4>; */ + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + + buck1: BUCK1 { + regulator-name = "VDD_SOC_0V8"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "LPD4_x_VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <670000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { + regulator-name = "LPD4_x_VDD2_1V1"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1140000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { + regulator-name = "NVCC_BBSM_1V8"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_ANA_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <840000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + vcc-supply = <&buck4>; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&buck4>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; From be1e3ea0cf76f2fa613220253a630308d19ae5d0 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Thu, 18 Dec 2025 13:00:06 +0100 Subject: [PATCH 064/104] arm64: dts: imx8mm-phycore-som: Update eth phy impedance Update the DP83867 ethernet phy impedance settings to to optimize signal quality and reduce potential signal integrity issues. Signed-off-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 3d66c6701342..b764f7734868 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -83,6 +83,7 @@ ethphy0: ethernet-phy@0 { enet-phy-lane-no-swap; ti,clk-output-sel = ; ti,fifo-depth = ; + ti,min-output-impedance; ti,rx-internal-delay = ; ti,tx-internal-delay = ; reg = <0>; From b516a4dd6a1ff7ddbaf3ab30ddec88088a6ec9e6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Dec 2025 09:42:15 +0800 Subject: [PATCH 065/104] arm64: dts: freescale: Add initial device tree for i.MX952 i.MX952 is designed for AI-powered sensor fusion and vision sensing applications, it features 4 Corte-A55, 1 Cortex-M33, 1 Cortex-M7 and NXP eIQ NPU and advanced graphics, video and advanced security with edgelock. Product info could be found at: https://www.nxp.com/products/i.MX-952 The basic device tree includes: - clock, pin, power header files - device nodes: CPU[0-3], SCMI firmware, Interrupt Controller, Sys counter, eDMA, MU, SPI, UART, I2C, USB and etc Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-clock.h | 215 +++ .../arm64/boot/dts/freescale/imx952-pinfunc.h | 867 ++++++++++++ arch/arm64/boot/dts/freescale/imx952-power.h | 44 + arch/arm64/boot/dts/freescale/imx952.dtsi | 1248 +++++++++++++++++ 4 files changed, 2374 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx952-clock.h create mode 100644 arch/arm64/boot/dts/freescale/imx952-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx952-power.h create mode 100644 arch/arm64/boot/dts/freescale/imx952.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx952-clock.h b/arch/arm64/boot/dts/freescale/imx952-clock.h new file mode 100644 index 000000000000..7d6f6635dc07 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-clock.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2025 NXP + */ + +#ifndef __CLOCK_IMX952_H__ +#define __CLOCK_IMX952_H__ + +/* Clock Source */ +#define IMX952_CLK_EXT 0 +#define IMX952_CLK_OSC32K 1 +#define IMX952_CLK_OSC24M 2 +#define IMX952_CLK_FRO 3 +#define IMX952_CLK_SYSPLL1_VCO 4 +#define IMX952_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX952_CLK_SYSPLL1_PFD0 6 +#define IMX952_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX952_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX952_CLK_SYSPLL1_PFD1 9 +#define IMX952_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX952_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX952_CLK_SYSPLL1_PFD2 12 +#define IMX952_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX952_CLK_AUDIOPLL1_VCO 14 +#define IMX952_CLK_AUDIOPLL1 15 +#define IMX952_CLK_AUDIOPLL2_VCO 16 +#define IMX952_CLK_AUDIOPLL2 17 +#define IMX952_CLK_VIDEOPLL1_VCO 18 +#define IMX952_CLK_VIDEOPLL1 19 +#define IMX952_CLK_SRC_RESERVED20 20 +#define IMX952_CLK_SYSPLL1_PFD3_UNGATED 21 +#define IMX952_CLK_SYSPLL1_PFD3 22 +#define IMX952_CLK_SYSPLL1_PFD3_DIV2 23 +#define IMX952_CLK_ARMPLL_VCO 24 +#define IMX952_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX952_CLK_ARMPLL_PFD0 26 +#define IMX952_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX952_CLK_ARMPLL_PFD1 28 +#define IMX952_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX952_CLK_ARMPLL_PFD2 30 +#define IMX952_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX952_CLK_ARMPLL_PFD3 32 +#define IMX952_CLK_DRAMPLL_VCO 33 +#define IMX952_CLK_DRAMPLL 34 +#define IMX952_CLK_HSIOPLL_VCO 35 +#define IMX952_CLK_HSIOPLL 36 +#define IMX952_CLK_LDBPLL_VCO 37 +#define IMX952_CLK_LDBPLL 38 +#define IMX952_CLK_EXT1 39 +#define IMX952_CLK_EXT2 40 + +/* Clock ROOT */ +#define IMX952_CLK_ADC 41 +#define IMX952_CLK_RESERVED1 42 +#define IMX952_CLK_BUSAON 43 +#define IMX952_CLK_CAN1 44 +#define IMX952_CLK_RESERVED4 45 +#define IMX952_CLK_I3C1SLOW 46 +#define IMX952_CLK_LPI2C1 47 +#define IMX952_CLK_LPI2C2 48 +#define IMX952_CLK_LPSPI1 49 +#define IMX952_CLK_LPSPI2 50 +#define IMX952_CLK_LPTMR1 51 +#define IMX952_CLK_LPUART1 52 +#define IMX952_CLK_LPUART2 53 +#define IMX952_CLK_M33 54 +#define IMX952_CLK_M33SYSTICK 55 +#define IMX952_CLK_RESERVED15 56 +#define IMX952_CLK_PDM 57 +#define IMX952_CLK_SAI1 58 +#define IMX952_CLK_RESERVED18 59 +#define IMX952_CLK_TPM2 60 +#define IMX952_CLK_RESERVED20 61 +#define IMX952_CLK_CAMAPB 62 +#define IMX952_CLK_CAMAXI 63 +#define IMX952_CLK_CAMCM0 64 +#define IMX952_CLK_CAMISI 65 +#define IMX952_CLK_CAMPHYCFG 66 +#define IMX952_CLK_MIPIPHYPLLBYPASS 67 +#define IMX952_CLK_RESERVED27 68 +#define IMX952_CLK_MIPITESTBYTE 69 +#define IMX952_CLK_A55 70 +#define IMX952_CLK_A55MTRBUS 71 +#define IMX952_CLK_A55PERIPH 72 +#define IMX952_CLK_DRAMALT 73 +#define IMX952_CLK_DRAMAPB 74 +#define IMX952_CLK_DISPAPB 75 +#define IMX952_CLK_DISPAXI 76 +#define IMX952_CLK_DISPLPSPI 77 +#define IMX952_CLK_DISPOCRAM 78 +#define IMX952_CLK_DISPPHYCFG 79 +#define IMX952_CLK_DISP1PIX 80 +#define IMX952_CLK_DISPCDPHYAPB 81 +#define IMX952_CLK_RESERVED41 82 +#define IMX952_CLK_GPUAPB 83 +#define IMX952_CLK_GPU 84 +#define IMX952_CLK_HSIOACSCAN480M 85 +#define IMX952_CLK_HSIOACSCAN80M 86 +#define IMX952_CLK_HSIO 87 +#define IMX952_CLK_HSIOPCIEAUX 88 +#define IMX952_CLK_HSIOPCIETEST160M 89 +#define IMX952_CLK_HSIOPCIETEST400M 90 +#define IMX952_CLK_HSIOPCIETEST500M 91 +#define IMX952_CLK_HSIOUSBTEST50M 92 +#define IMX952_CLK_HSIOUSBTEST60M 93 +#define IMX952_CLK_BUSM7 94 +#define IMX952_CLK_M7 95 +#define IMX952_CLK_M7SYSTICK 96 +#define IMX952_CLK_BUSNETCMIX 97 +#define IMX952_CLK_ENET 98 +#define IMX952_CLK_ENETPHYTEST200M 99 +#define IMX952_CLK_ENETPHYTEST500M 100 +#define IMX952_CLK_ENETPHYTEST667M 101 +#define IMX952_CLK_ENETREF 102 +#define IMX952_CLK_ENETTIMER1 103 +#define IMX952_CLK_RESERVED63 104 +#define IMX952_CLK_SAI2 105 +#define IMX952_CLK_NOCAPB 106 +#define IMX952_CLK_NOC 107 +#define IMX952_CLK_NPUAPB 108 +#define IMX952_CLK_NPU 109 +#define IMX952_CLK_CCMCKO1 110 +#define IMX952_CLK_CCMCKO2 111 +#define IMX952_CLK_CCMCKO3 112 +#define IMX952_CLK_CCMCKO4 113 +#define IMX952_CLK_VPUAPB 114 +#define IMX952_CLK_VPU 115 +#define IMX952_CLK_RESERVED75 116 +#define IMX952_CLK_RESERVED76 117 +#define IMX952_CLK_AUDIOXCVR 118 +#define IMX952_CLK_BUSWAKEUP 119 +#define IMX952_CLK_CAN2 120 +#define IMX952_CLK_CAN3 121 +#define IMX952_CLK_CAN4 122 +#define IMX952_CLK_CAN5 123 +#define IMX952_CLK_FLEXIO1 124 +#define IMX952_CLK_FLEXIO2 125 +#define IMX952_CLK_XSPI1 126 +#define IMX952_CLK_RESERVED86 127 +#define IMX952_CLK_I3C2SLOW 128 +#define IMX952_CLK_LPI2C3 129 +#define IMX952_CLK_LPI2C4 130 +#define IMX952_CLK_LPI2C5 131 +#define IMX952_CLK_LPI2C6 132 +#define IMX952_CLK_LPI2C7 133 +#define IMX952_CLK_LPI2C8 134 +#define IMX952_CLK_LPSPI3 135 +#define IMX952_CLK_LPSPI4 136 +#define IMX952_CLK_LPSPI5 137 +#define IMX952_CLK_LPSPI6 138 +#define IMX952_CLK_LPSPI7 139 +#define IMX952_CLK_LPSPI8 140 +#define IMX952_CLK_LPTMR2 141 +#define IMX952_CLK_LPUART3 142 +#define IMX952_CLK_LPUART4 143 +#define IMX952_CLK_LPUART5 144 +#define IMX952_CLK_LPUART6 145 +#define IMX952_CLK_LPUART7 146 +#define IMX952_CLK_LPUART8 147 +#define IMX952_CLK_SAI3 148 +#define IMX952_CLK_SAI4 149 +#define IMX952_CLK_SAI5 150 +#define IMX952_CLK_SPDIF 151 +#define IMX952_CLK_SWOTRACE 152 +#define IMX952_CLK_TPM4 153 +#define IMX952_CLK_TPM5 154 +#define IMX952_CLK_TPM6 155 +#define IMX952_CLK_MIPIPHYDFT400 156 +#define IMX952_CLK_MIPIPHYDFT540 157 +#define IMX952_CLK_USDHC1 158 +#define IMX952_CLK_USDHC2 159 +#define IMX952_CLK_USDHC3 160 +#define IMX952_CLK_V2XPK 161 +#define IMX952_CLK_WAKEUPAXI 162 +#define IMX952_CLK_XSPISLVROOT 163 +#define IMX952_CLK_AUDMIX1 164 +#define IMX952_CLK_ASRC1 165 +#define IMX952_CLK_ASRC2 166 +#define IMX952_CLK_GPT1 167 +#define IMX952_CLK_GPT2 168 +#define IMX952_CLK_GPT3 169 +#define IMX952_CLK_GPT4 170 + +/* Clock GPR SEL */ +#define IMX952_CLK_GPR_SEL_EXT 171 +#define IMX952_CLK_GPR_SEL_A55C0 172 +#define IMX952_CLK_GPR_SEL_A55C1 173 +#define IMX952_CLK_GPR_SEL_A55C2 174 +#define IMX952_CLK_GPR_SEL_A55C3 175 +#define IMX952_CLK_GPR_SEL_A55P 176 +#define IMX952_CLK_GPR_SEL_DRAM 177 +#define IMX952_CLK_GPR_SEL_TEMPSENSE 178 + +/* Clock CGC */ +#define IMX952_CLK_CGC_NPU 179 +#define IMX952_CLK_CGC_GPU 180 +#define IMX952_CLK_CGC_CAMISI 181 +#define IMX952_CLK_CGC_CAMISP 182 +#define IMX952_CLK_CGC_CAMCSI0 183 +#define IMX952_CLK_CGC_CAMCSI1 184 +#define IMX952_CLK_CGC_CAMOCRAM 185 +#define IMX952_CLK_CGC_HSIOUSB 186 +#define IMX952_CLK_CGC_HSIOPCIE 187 +#define IMX952_CLK_CGC_DISPOCRAM 188 +#define IMX952_CLK_CGC_DISPSEERIS 189 +#define IMX952_CLK_CGC_DISPDSI 190 +#define IMX952_CLK_CGC_NOCGIC 191 +#define IMX952_CLK_CGC_NOCOCRAM 192 +#define IMX952_CLK_CGC_NETC 193 +#define IMX952_CLK_CGC_VPUENC 194 +#define IMX952_CLK_CGC_VPUJPEGENC 195 +#define IMX952_CLK_CGC_VPUJPEGDEC 196 +#define IMX952_CLK_CGC_VPUDEC 197 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx952-pinfunc.h b/arch/arm64/boot/dts/freescale/imx952-pinfunc.h new file mode 100644 index 000000000000..debe6ede2d70 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-pinfunc.h @@ -0,0 +1,867 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __DTS_IMX952_PINFUNC_H__ +#define __DTS_IMX952_PINFUNC_H__ + +/* + * The pin function ID is a tuple of + * + */ +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_TDI 0x0000 0x0230 0x05FC 0x00 0x00 +#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0230 0x0000 0x01 0x00 +#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0230 0x0000 0x02 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_CAN2_TX 0x0000 0x0230 0x0000 0x03 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_30 0x0000 0x0230 0x0000 0x04 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_GPIO3_IO_28 0x0000 0x0230 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x0000 0x0230 0x059C 0x06 0x00 + +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_TMS 0x0004 0x0234 0x0600 0x00 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_31 0x0004 0x0234 0x0000 0x04 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_GPIO3_IO_29 0x0004 0x0234 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x0004 0x0234 0x0000 0x06 0x00 + +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_TCK 0x0008 0x0238 0x05F8 0x00 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0008 0x0238 0x04B4 0x04 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_GPIO3_IO_30 0x0008 0x0238 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0008 0x0238 0x0598 0x06 0x00 + +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_TDO 0x000C 0x023C 0x0000 0x00 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x023C 0x0000 0x01 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM2 0x000C 0x023C 0x0000 0x02 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_CAN2_RX 0x000C 0x023C 0x04A4 0x03 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x000C 0x023C 0x04B8 0x04 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_GPIO3_IO_31 0x000C 0x023C 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x000C 0x023C 0x05A0 0x06 0x00 + +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPIO2_IO_0 0x0010 0x0240 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x0010 0x0240 0x0530 0x01 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPTMUX_INOUT0 0x0010 0x0240 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPSPI6_PCS0 0x0010 0x0240 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPUART5_TX 0x0010 0x0240 0x05A0 0x05 0x01 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C5_SDA 0x0010 0x0240 0x0540 0x06 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x0010 0x0240 0x04BC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPIO2_IO_1 0x0014 0x0244 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x0014 0x0244 0x052C 0x01 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPTMUX_INOUT1 0x0014 0x0244 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPSPI6_SIN 0x0014 0x0244 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPUART5_RX 0x0014 0x0244 0x059C 0x05 0x01 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C5_SCL 0x0014 0x0244 0x053C 0x06 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x0014 0x0244 0x04C0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPIO2_IO_2 0x0018 0x0248 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C4_SDA 0x0018 0x0248 0x0538 0x01 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPTMUX_INOUT2 0x0018 0x0248 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPSPI6_SOUT 0x0018 0x0248 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0018 0x0248 0x0598 0x05 0x01 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x0018 0x0248 0x0548 0x06 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x0018 0x0248 0x04C4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPIO2_IO_3 0x001C 0x024C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C4_SCL 0x001C 0x024C 0x0534 0x01 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPTMUX_INOUT3 0x001C 0x024C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPSPI6_SCK 0x001C 0x024C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPUART5_RTS_B 0x001C 0x024C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x001C 0x024C 0x0544 0x06 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x001C 0x024C 0x04C8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x0020 0x0250 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_TPM3_CH0 0x0020 0x0250 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0250 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPTMUX_INOUT4 0x0020 0x0250 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPSPI7_PCS0 0x0020 0x0250 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPUART6_TX 0x0020 0x0250 0x05AC 0x05 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPI2C6_SDA 0x0020 0x0250 0x0548 0x06 0x01 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x0020 0x0250 0x04CC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPIO2_IO_5 0x0024 0x0254 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_TPM4_CH0 0x0024 0x0254 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_0 0x0024 0x0254 0x0464 0x02 0x01 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPTMUX_INOUT5 0x0024 0x0254 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x0024 0x0254 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPUART6_RX 0x0024 0x0254 0x05A8 0x05 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPI2C6_SCL 0x0024 0x0254 0x0544 0x06 0x01 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x0024 0x0254 0x04D0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPIO2_IO_6 0x0028 0x0258 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_TPM5_CH0 0x0028 0x0258 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_1 0x0028 0x0258 0x0468 0x02 0x01 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPTMUX_INOUT6 0x0028 0x0258 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x0028 0x0258 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0028 0x0258 0x05A4 0x05 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPI2C7_SDA 0x0028 0x0258 0x0550 0x06 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x0028 0x0258 0x04D4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPIO2_IO_7 0x002C 0x025C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI3_PCS1 0x002C 0x025C 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPTMUX_INOUT7 0x002C 0x025C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x002C 0x025C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPUART6_RTS_B 0x002C 0x025C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPI2C7_SCL 0x002C 0x025C 0x054C 0x06 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x002C 0x025C 0x04D8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPIO2_IO_8 0x0030 0x0260 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPSPI3_PCS0 0x0030 0x0260 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPTMUX_INOUT8 0x0030 0x0260 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_TPM6_CH0 0x0030 0x0260 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPUART7_TX 0x0030 0x0260 0x05B4 0x05 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x0030 0x0260 0x0550 0x06 0x01 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0030 0x0260 0x04DC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPIO2_IO_9 0x0034 0x0264 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPSPI3_SIN 0x0034 0x0264 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPTMUX_INOUT9 0x0034 0x0264 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_TPM3_EXTCLK 0x0034 0x0264 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPUART7_RX 0x0034 0x0264 0x05B0 0x05 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x0034 0x0264 0x054C 0x06 0x01 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0034 0x0264 0x04E0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x0038 0x0268 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPSPI3_SOUT 0x0038 0x0268 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPTMUX_INOUT10 0x0038 0x0268 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_TPM4_EXTCLK 0x0038 0x0268 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPUART7_CTS_B 0x0038 0x0268 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPI2C8_SDA 0x0038 0x0268 0x0558 0x06 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x0038 0x0268 0x04E4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x003C 0x026C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPSPI3_SCK 0x003C 0x026C 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPTMUX_INOUT11 0x003C 0x026C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_TPM5_EXTCLK 0x003C 0x026C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPUART7_RTS_B 0x003C 0x026C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPI2C8_SCL 0x003C 0x026C 0x0554 0x06 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x003C 0x026C 0x04E8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_GPIO2_IO_12 0x0040 0x0270 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x0040 0x0270 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_2 0x0040 0x0270 0x046C 0x02 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0040 0x0270 0x04EC 0x03 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPSPI8_PCS0 0x0040 0x0270 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPUART8_TX 0x0040 0x0270 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPI2C8_SDA 0x0040 0x0270 0x0558 0x06 0x01 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x0040 0x0270 0x05BC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_GPIO2_IO_13 0x0044 0x0274 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_TPM4_CH2 0x0044 0x0274 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_3 0x0044 0x0274 0x0470 0x02 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPSPI8_SIN 0x0044 0x0274 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPUART8_RX 0x0044 0x0274 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPI2C8_SCL 0x0044 0x0274 0x0554 0x06 0x01 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0044 0x0274 0x04F0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_GPIO2_IO_14 0x0048 0x0278 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART3_TX 0x0048 0x0278 0x0588 0x01 0x01 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPSPI8_SOUT 0x0048 0x0278 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART8_CTS_B 0x0048 0x0278 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART4_TX 0x0048 0x0278 0x0594 0x06 0x01 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x0048 0x0278 0x04F4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_GPIO2_IO_15 0x004C 0x027C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART3_RX 0x004C 0x027C 0x0584 0x01 0x01 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x004C 0x027C 0x0624 0x03 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPSPI8_SCK 0x004C 0x027C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART8_RTS_B 0x004C 0x027C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART4_RX 0x004C 0x027C 0x0590 0x06 0x01 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x004C 0x027C 0x04F8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x0050 0x0280 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x0050 0x0280 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_2 0x0050 0x0280 0x046C 0x02 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0050 0x0280 0x0580 0x04 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0050 0x0280 0x0564 0x05 0x00 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART4_CTS_B 0x0050 0x0280 0x058C 0x06 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0050 0x0280 0x04FC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x0054 0x0284 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x0054 0x0284 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART3_RTS_B 0x0054 0x0284 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0054 0x0284 0x0560 0x05 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART4_RTS_B 0x0054 0x0284 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0054 0x0284 0x0500 0x07 0x00 + +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x0058 0x0288 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0058 0x0288 0x05B8 0x01 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI5_PCS0 0x0058 0x0288 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0058 0x0288 0x055C 0x05 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_TPM5_CH2 0x0058 0x0288 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x0058 0x0288 0x0504 0x07 0x00 + +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_GPIO2_IO_19 0x005C 0x028C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x005C 0x028C 0x05BC 0x01 0x01 +#define IMX952_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_3 0x005C 0x028C 0x0470 0x02 0x01 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x005C 0x028C 0x0508 0x03 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI5_SIN 0x005C 0x028C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI4_SIN 0x005C 0x028C 0x056C 0x05 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x005C 0x028C 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x005C 0x028C 0x05F4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x0060 0x0290 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x0060 0x0290 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_0 0x0060 0x0290 0x0464 0x02 0x02 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI5_SOUT 0x0060 0x0290 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI4_SOUT 0x0060 0x0290 0x0570 0x05 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_TPM3_CH1 0x0060 0x0290 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0060 0x0290 0x050C 0x07 0x00 + +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x0064 0x0294 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x0064 0x0294 0x05F4 0x01 0x01 +#define IMX952_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0294 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0064 0x0294 0x0510 0x03 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI5_SCK 0x0064 0x0294 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI4_SCK 0x0064 0x0294 0x0568 0x05 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_TPM4_CH1 0x0064 0x0294 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0064 0x0294 0x05B8 0x07 0x01 + +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_GPIO2_IO_22 0x0068 0x0298 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_USDHC3_CLK 0x0068 0x0298 0x0604 0x01 0x00 +#define IMX952_PAD_GPIO_IO22__HSIOMIX_TOP_USB1_OTG_OC 0x0068 0x0298 0x047C 0x03 0x01 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM5_CH1 0x0068 0x0298 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM6_EXTCLK 0x0068 0x0298 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_LPI2C5_SDA 0x0068 0x0298 0x0540 0x06 0x01 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x0068 0x0298 0x0514 0x07 0x00 + +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_GPIO2_IO_23 0x006C 0x029C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_USDHC3_CMD 0x006C 0x029C 0x0608 0x01 0x00 +#define IMX952_PAD_GPIO_IO23__HSIOMIX_TOP_USB2_OTG_OC 0x006C 0x029C 0x0480 0x03 0x01 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_TPM6_CH1 0x006C 0x029C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_LPI2C5_SCL 0x006C 0x029C 0x053C 0x06 0x01 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x006C 0x029C 0x0518 0x07 0x00 + +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_GPIO2_IO_24 0x0070 0x02A0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_USDHC3_DATA0 0x0070 0x02A0 0x060C 0x01 0x00 +#define IMX952_PAD_GPIO_IO24__HSIOMIX_TOP_USB1_OTG_PWR 0x0070 0x02A0 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TPM3_CH3 0x0070 0x02A0 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TDO 0x0070 0x02A0 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_LPSPI6_PCS1 0x0070 0x02A0 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0070 0x02A0 0x051C 0x07 0x00 + +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_GPIO2_IO_25 0x0074 0x02A4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_USDHC3_DATA1 0x0074 0x02A4 0x0610 0x01 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x0074 0x02A4 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO25__HSIOMIX_TOP_USB2_OTG_PWR 0x0074 0x02A4 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TPM4_CH3 0x0074 0x02A4 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TCK 0x0074 0x02A4 0x05F8 0x05 0x01 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_LPSPI7_PCS1 0x0074 0x02A4 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0074 0x02A4 0x0520 0x07 0x00 + +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x0078 0x02A8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_USDHC3_DATA2 0x0078 0x02A8 0x0614 0x01 0x00 +#define IMX952_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_1 0x0078 0x02A8 0x0468 0x02 0x02 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x0078 0x02A8 0x04AC 0x03 0x01 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TPM5_CH3 0x0078 0x02A8 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TDI 0x0078 0x02A8 0x05FC 0x05 0x01 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_LPSPI8_PCS1 0x0078 0x02A8 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x0078 0x02A8 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_GPIO2_IO_27 0x007C 0x02AC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_USDHC3_DATA3 0x007C 0x02AC 0x0618 0x01 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x007C 0x02AC 0x04A4 0x02 0x02 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TPM6_CH3 0x007C 0x02AC 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TMS 0x007C 0x02AC 0x0600 0x05 0x01 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_LPSPI5_PCS1 0x007C 0x02AC 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x007C 0x02AC 0x04B0 0x07 0x01 + +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_GPIO2_IO_28 0x0080 0x02B0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_LPI2C3_SDA 0x0080 0x02B0 0x0530 0x01 0x01 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_CAN3_TX 0x0080 0x02B0 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_28 0x0080 0x02B0 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_GPIO2_IO_29 0x0084 0x02B4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_LPI2C3_SCL 0x0084 0x02B4 0x052C 0x01 0x01 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_CAN3_RX 0x0084 0x02B4 0x04A8 0x02 0x01 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_29 0x0084 0x02B4 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_GPIO2_IO_30 0x0088 0x02B8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x0088 0x02B8 0x0538 0x01 0x01 +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0088 0x02B8 0x04B4 0x07 0x01 + +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_GPIO2_IO_31 0x008C 0x02BC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x008C 0x02BC 0x0534 0x01 0x01 +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x008C 0x02BC 0x04B8 0x07 0x01 + +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_GPIO5_IO_12 0x0090 0x02C0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x02C0 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPUART6_TX 0x0090 0x02C0 0x05AC 0x02 0x01 +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0090 0x02C0 0x0564 0x04 0x01 + +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_GPIO5_IO_13 0x0094 0x02C4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPUART6_RX 0x0094 0x02C4 0x05A8 0x02 0x01 +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0094 0x02C4 0x0560 0x04 0x01 + +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x0098 0x02C8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0098 0x02C8 0x05A4 0x02 0x01 +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0098 0x02C8 0x055C 0x04 0x01 + +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_GPIO5_IO_15 0x009C 0x02CC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPUART6_RTS_B 0x009C 0x02CC 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPSPI4_SIN 0x009C 0x02CC 0x056C 0x04 0x01 + +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPSPI4_SOUT 0x00A0 0x02D0 0x0570 0x04 0x01 +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x00A0 0x02D0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPUART7_TX 0x00A0 0x02D0 0x05B4 0x02 0x01 + +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_GPIO5_IO_17 0x00A4 0x02D4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPUART7_RX 0x00A4 0x02D4 0x05B0 0x02 0x01 +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPSPI4_SCK 0x00A4 0x02D4 0x0568 0x04 0x01 + +#define IMX952_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00D4 0x0304 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00D4 0x0304 0x0494 0x01 0x00 +#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x00D4 0x0304 0x04AC 0x04 0x00 +#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x00D4 0x0304 0x0000 0x05 0x00 + +#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x00D8 0x0308 0x0000 0x05 0x00 +#define IMX952_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00D8 0x0308 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00D8 0x0308 0x0000 0x01 0x00 +#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x00D8 0x0308 0x04B0 0x04 0x00 + +#define IMX952_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00DC 0x030C 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00DC 0x030C 0x0498 0x01 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_CAN3_TX 0x00DC 0x030C 0x0000 0x02 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_28 0x00DC 0x030C 0x0000 0x04 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_GPIO4_IO_28 0x00DC 0x030C 0x0000 0x05 0x00 + +#define IMX952_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00E0 0x0310 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00E0 0x0310 0x0000 0x01 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_CAN3_RX 0x00E0 0x0310 0x04A8 0x02 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_29 0x00E0 0x0310 0x0000 0x04 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_GPIO4_IO_29 0x00E0 0x0310 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00E4 0x0314 0x0484 0x00 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_LPUART3_DCD_B 0x00E4 0x0314 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_I3C2_SCL 0x00E4 0x0314 0x0524 0x02 0x00 +#define IMX952_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00E4 0x0314 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_0 0x00E4 0x0314 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_GPIO4_IO_0 0x00E4 0x0314 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00E8 0x0318 0x0488 0x00 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_LPUART3_RIN_B 0x00E8 0x0318 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_I3C2_SDA 0x00E8 0x0318 0x0528 0x02 0x00 +#define IMX952_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00E8 0x0318 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_1 0x00E8 0x0318 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_GPIO4_IO_1 0x00E8 0x0318 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00EC 0x031C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_CAN2_TX 0x00EC 0x031C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00EC 0x031C 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_2 0x00EC 0x031C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_GPIO4_IO_2 0x00EC 0x031C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00F0 0x0320 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00F0 0x0320 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_CAN2_RX 0x00F0 0x0320 0x04A4 0x02 0x01 +#define IMX952_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00F0 0x0320 0x0480 0x03 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_3 0x00F0 0x0320 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_GPIO4_IO_3 0x00F0 0x0320 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00F4 0x0324 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_LPUART3_RTS_B 0x00F4 0x0324 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR 0x00F4 0x0324 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00F4 0x0324 0x047C 0x03 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_4 0x00F4 0x0324 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_GPIO4_IO_4 0x00F4 0x0324 0x0000 0x05 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR_B 0x00F4 0x0324 0x0000 0x06 0x00 +#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00F4 0x0324 0x0000 0x07 0x00 + +#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00F8 0x0328 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_LPUART3_TX 0x00F8 0x0328 0x0588 0x01 0x00 +#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00F8 0x0328 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_5 0x00F8 0x0328 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_GPIO4_IO_5 0x00F8 0x0328 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00FC 0x032C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_LPUART3_DTR_B 0x00FC 0x032C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00FC 0x032C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_6 0x00FC 0x032C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_6 0x00FC 0x032C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x0100 0x0330 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RMII_REF50_CLK_OUT 0x0100 0x0330 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_7 0x0100 0x0330 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_GPIO4_IO_7 0x0100 0x0330 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x0104 0x0334 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_LPUART3_DSR_B 0x0104 0x0334 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x0104 0x0334 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x0104 0x0334 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_8 0x0104 0x0334 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_8 0x0104 0x0334 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x0108 0x0338 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0108 0x0338 0x048C 0x01 0x00 +#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_9 0x0108 0x0338 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_GPIO4_IO_9 0x0108 0x0338 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x010C 0x033C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_LPUART3_RX 0x010C 0x033C 0x0584 0x01 0x00 +#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x010C 0x033C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_10 0x010C 0x033C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_GPIO4_IO_10 0x010C 0x033C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x0110 0x0340 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0110 0x0340 0x0580 0x01 0x00 +#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x0110 0x0340 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPTMR2_ALT0 0x0110 0x0340 0x0574 0x03 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_11 0x0110 0x0340 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_GPIO4_IO_11 0x0110 0x0340 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x0114 0x0344 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0114 0x0344 0x048C 0x02 0x01 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_LPTMR2_ALT1 0x0114 0x0344 0x0578 0x03 0x00 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_12 0x0114 0x0344 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_GPIO4_IO_12 0x0114 0x0344 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x0118 0x0348 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0118 0x0348 0x057C 0x03 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_13 0x0118 0x0348 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_GPIO4_IO_13 0x0118 0x0348 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x011C 0x034C 0x0484 0x00 0x01 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_LPUART4_DCD_B 0x011C 0x034C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x011C 0x034C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_14 0x011C 0x034C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_GPIO4_IO_14 0x011C 0x034C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x0120 0x0350 0x0488 0x00 0x01 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_LPUART4_RIN_B 0x0120 0x0350 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x0120 0x0350 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_15 0x0120 0x0350 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_GPIO4_IO_15 0x0120 0x0350 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_0 0x0124 0x0354 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_16 0x0124 0x0354 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_GPIO4_IO_16 0x0124 0x0354 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x0124 0x0354 0x0000 0x00 0x00 + +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x0128 0x0358 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x0128 0x0358 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_1 0x0128 0x0358 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x0128 0x0358 0x05D0 0x03 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_17 0x0128 0x0358 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_GPIO4_IO_17 0x0128 0x0358 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x012C 0x035C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_LPUART4_RTS_B 0x012C 0x035C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_2 0x012C 0x035C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x012C 0x035C 0x05CC 0x03 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_18 0x012C 0x035C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_GPIO4_IO_18 0x012C 0x035C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x012C 0x035C 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0130 0x0360 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_LPUART4_TX 0x0130 0x0360 0x0594 0x01 0x00 +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_3 0x0130 0x0360 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x0130 0x0360 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_19 0x0130 0x0360 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_GPIO4_IO_19 0x0130 0x0360 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0130 0x0360 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0134 0x0364 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_LPUART4_DTR_B 0x0134 0x0364 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0134 0x0364 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0134 0x0364 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_20 0x0134 0x0364 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_20 0x0134 0x0364 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x0138 0x0368 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RMII_REF50_CLK_OUT 0x0138 0x0368 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x0138 0x0368 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_21 0x0138 0x0368 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_GPIO4_IO_21 0x0138 0x0368 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x013C 0x036C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_LPUART4_DSR_B 0x013C 0x036C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_0 0x013C 0x036C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_22 0x013C 0x036C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_22 0x013C 0x036C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x013C 0x036C 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0140 0x0370 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0140 0x0370 0x0490 0x01 0x00 +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_1 0x0140 0x0370 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x0140 0x0370 0x05C8 0x03 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_23 0x0140 0x0370 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_GPIO4_IO_23 0x0140 0x0370 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0144 0x0374 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_LPUART4_RX 0x0144 0x0374 0x0590 0x01 0x00 +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_2 0x0144 0x0374 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x0144 0x0374 0x05C0 0x03 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_24 0x0144 0x0374 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_GPIO4_IO_24 0x0144 0x0374 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0144 0x0374 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x0148 0x0378 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_3 0x0148 0x0378 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x0148 0x0378 0x05C4 0x03 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_25 0x0148 0x0378 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_GPIO4_IO_25 0x0148 0x0378 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x0148 0x0378 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x014C 0x037C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_LPUART4_CTS_B 0x014C 0x037C 0x058C 0x01 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x014C 0x037C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x014C 0x037C 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_26 0x014C 0x037C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_GPIO4_IO_26 0x014C 0x037C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x014C 0x037C 0x0490 0x06 0x01 + +#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0150 0x0380 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0150 0x0380 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_27 0x0150 0x0380 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_GPIO4_IO_27 0x0150 0x0380 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0154 0x0384 0x04DC 0x04 0x01 +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_GPIO3_IO_8 0x0154 0x0384 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x0154 0x0384 0x0000 0x00 0x00 + +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x0158 0x0388 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0158 0x0388 0x04E0 0x04 0x01 +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_GPIO3_IO_9 0x0158 0x0388 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x015C 0x038C 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x015C 0x038C 0x04E4 0x04 0x01 +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_GPIO3_IO_10 0x015C 0x038C 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x0160 0x0390 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x0160 0x0390 0x04E8 0x04 0x01 +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_GPIO3_IO_11 0x0160 0x0390 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x0164 0x0394 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x0164 0x0394 0x0624 0x01 0x01 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0164 0x0394 0x04EC 0x04 0x01 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_GPIO3_IO_12 0x0164 0x0394 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0164 0x0394 0x0000 0x06 0x00 + +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x0168 0x0398 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x0168 0x0398 0x064C 0x01 0x00 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0168 0x0398 0x04F0 0x04 0x01 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_GPIO3_IO_13 0x0168 0x0398 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x016C 0x039C 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x016C 0x039C 0x0638 0x01 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x016C 0x039C 0x04F4 0x04 0x01 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_GPIO3_IO_14 0x016C 0x039C 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x016C 0x039C 0x066C 0x06 0x00 + +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x0170 0x03A0 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x0170 0x03A0 0x063C 0x01 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_RESET_B 0x0170 0x03A0 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x0170 0x03A0 0x04F8 0x04 0x01 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_GPIO3_IO_15 0x0170 0x03A0 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x0170 0x03A0 0x0670 0x06 0x00 + +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x0174 0x03A4 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x0174 0x03A4 0x0640 0x01 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_CD_B 0x0174 0x03A4 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0174 0x03A4 0x04FC 0x04 0x01 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_GPIO3_IO_16 0x0174 0x03A4 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x0174 0x03A4 0x0674 0x06 0x00 + +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x0178 0x03A8 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x0178 0x03A8 0x0644 0x01 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_WP 0x0178 0x03A8 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0178 0x03A8 0x0500 0x04 0x01 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_GPIO3_IO_17 0x0178 0x03A8 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x0178 0x03A8 0x0678 0x06 0x00 + +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x017C 0x03AC 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI1_A_DQS 0x017C 0x03AC 0x0620 0x01 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x017C 0x03AC 0x0504 0x04 0x01 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_GPIO3_IO_18 0x017C 0x03AC 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x017C 0x03AC 0x0654 0x06 0x00 + +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x0180 0x03B0 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_WP 0x0180 0x03B0 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0180 0x03B0 0x057C 0x02 0x01 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x0180 0x03B0 0x0508 0x04 0x01 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_GPIO3_IO_19 0x0180 0x03B0 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0180 0x03B0 0x0478 0x06 0x01 + +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x0184 0x03B4 0x0604 0x00 0x01 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x0184 0x03B4 0x061C 0x01 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x0184 0x03B4 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x0184 0x03B4 0x05D8 0x03 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0184 0x03B4 0x050C 0x04 0x01 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_GPIO3_IO_20 0x0184 0x03B4 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x0184 0x03B4 0x0658 0x06 0x00 + +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x0188 0x03B8 0x0608 0x00 0x01 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x0188 0x03B8 0x0648 0x01 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x0188 0x03B8 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x0188 0x03B8 0x05E8 0x03 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0188 0x03B8 0x0510 0x04 0x01 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_GPIO3_IO_21 0x0188 0x03B8 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI_SLV_CS 0x0188 0x03B8 0x0650 0x06 0x00 + +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x018C 0x03BC 0x060C 0x00 0x01 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x018C 0x03BC 0x0628 0x01 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x018C 0x03BC 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x018C 0x03BC 0x05D4 0x03 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x018C 0x03BC 0x0514 0x04 0x01 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_GPIO3_IO_22 0x018C 0x03BC 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x018C 0x03BC 0x065C 0x06 0x00 + +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x0190 0x03C0 0x0610 0x00 0x01 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x0190 0x03C0 0x062C 0x01 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x0190 0x03C0 0x05DC 0x02 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x0190 0x03C0 0x0000 0x03 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x0190 0x03C0 0x0518 0x04 0x01 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_GPIO3_IO_23 0x0190 0x03C0 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x0190 0x03C0 0x0660 0x06 0x00 + +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x0194 0x03C4 0x0614 0x00 0x01 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x0194 0x03C4 0x0630 0x01 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x0194 0x03C4 0x05E0 0x02 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x0194 0x03C4 0x05F0 0x03 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0194 0x03C4 0x051C 0x04 0x01 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_GPIO3_IO_24 0x0194 0x03C4 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x0194 0x03C4 0x0664 0x06 0x00 + +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x0198 0x03C8 0x0618 0x00 0x01 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x0198 0x03C8 0x0634 0x01 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x0198 0x03C8 0x05E4 0x02 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x0198 0x03C8 0x05EC 0x03 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0198 0x03C8 0x0520 0x04 0x01 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_GPIO3_IO_25 0x0198 0x03C8 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x0198 0x03C8 0x0668 0x06 0x00 + +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x019C 0x03CC 0x0628 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_4 0x019C 0x03CC 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x019C 0x03CC 0x05CC 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_RX_DATA_1 0x019C 0x03CC 0x0000 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x019C 0x03CC 0x065C 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_GPIO5_IO_0 0x019C 0x03CC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x01A0 0x03D0 0x062C 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_5 0x01A0 0x03D0 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x01A0 0x03D0 0x05D0 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_DATA_1 0x01A0 0x03D0 0x0000 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x01A0 0x03D0 0x0660 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_GPIO5_IO_1 0x01A0 0x03D0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x01A4 0x03D4 0x0630 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_6 0x01A4 0x03D4 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x01A4 0x03D4 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x01A4 0x03D4 0x0664 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_GPIO5_IO_2 0x01A4 0x03D4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x01A8 0x03D8 0x0634 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_7 0x01A8 0x03D8 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x01A8 0x03D8 0x05C4 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x01A8 0x03D8 0x0668 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_GPIO5_IO_3 0x01A8 0x03D8 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x01AC 0x03DC 0x0638 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x01AC 0x03DC 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x01AC 0x03DC 0x05DC 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x01AC 0x03DC 0x066C 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_GPIO5_IO_4 0x01AC 0x03DC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x01B0 0x03E0 0x063C 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x01B0 0x03E0 0x05F0 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x01B0 0x03E0 0x05E0 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_6 0x01B0 0x03E0 0x049C 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x01B0 0x03E0 0x0670 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_GPIO5_IO_5 0x01B0 0x03E0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x01B4 0x03E4 0x0640 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x01B4 0x03E4 0x05EC 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x01B4 0x03E4 0x05E4 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_7 0x01B4 0x03E4 0x04A0 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x01B4 0x03E4 0x0674 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_GPIO5_IO_6 0x01B4 0x03E4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x01B8 0x03E8 0x0644 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x01B8 0x03E8 0x05D8 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x01B8 0x03E8 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x01B8 0x03E8 0x0678 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_GPIO5_IO_7 0x01B8 0x03E8 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x01BC 0x03EC 0x0620 0x00 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x01BC 0x03EC 0x05E8 0x01 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x01BC 0x03EC 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_6 0x01BC 0x03EC 0x049C 0x03 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x01BC 0x03EC 0x0654 0x04 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_GPIO5_IO_8 0x01BC 0x03EC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x01C0 0x03F0 0x061C 0x00 0x01 +#define IMX952_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_4 0x01C0 0x03F0 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x01C0 0x03F0 0x05C8 0x02 0x01 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x01C0 0x03F0 0x0658 0x04 0x01 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_GPIO5_IO_9 0x01C0 0x03F0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x01C4 0x03F4 0x0648 0x00 0x01 +#define IMX952_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_5 0x01C4 0x03F4 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x01C4 0x03F4 0x05C0 0x02 0x01 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI_SLV_CS 0x01C4 0x03F4 0x0650 0x04 0x01 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_GPIO5_IO_10 0x01C4 0x03F4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x01C8 0x03F8 0x064C 0x00 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x01C8 0x03F8 0x05D4 0x01 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x01C8 0x03F8 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_7 0x01C8 0x03F8 0x04A0 0x03 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x01C8 0x03F8 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_USDHC2_CD_B 0x01CC 0x03FC 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01CC 0x03FC 0x0494 0x01 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_I3C2_SCL 0x01CC 0x03FC 0x0524 0x02 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x01CC 0x03FC 0x04BC 0x04 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x01CC 0x03FC 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x01D0 0x0400 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01D0 0x0400 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_I3C2_SDA 0x01D0 0x0400 0x0528 0x02 0x01 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x01D0 0x0400 0x04C0 0x04 0x01 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_GPIO3_IO_1 0x01D0 0x0400 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01D0 0x0400 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x01D4 0x0404 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01D4 0x0404 0x0498 0x01 0x01 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR 0x01D4 0x0404 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR_B 0x01D4 0x0404 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x01D4 0x0404 0x04C4 0x04 0x01 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_GPIO3_IO_2 0x01D4 0x0404 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01D4 0x0404 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x01D8 0x0408 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01D8 0x0408 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_CAN2_TX 0x01D8 0x0408 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x01D8 0x0408 0x04C8 0x04 0x01 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_GPIO3_IO_3 0x01D8 0x0408 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01D8 0x0408 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x01DC 0x040C 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01DC 0x040C 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_CAN2_RX 0x01DC 0x040C 0x04A4 0x02 0x03 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x01DC 0x040C 0x04CC 0x04 0x01 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_GPIO3_IO_4 0x01DC 0x040C 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x01E0 0x0410 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01E0 0x0410 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01E0 0x0410 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x01E0 0x0410 0x04D0 0x04 0x01 +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_GPIO3_IO_5 0x01E0 0x0410 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x01E4 0x0414 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_LPTMR2_ALT0 0x01E4 0x0414 0x0574 0x01 0x01 +#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01E4 0x0414 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01E4 0x0414 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x01E4 0x0414 0x04D4 0x04 0x01 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_GPIO3_IO_6 0x01E4 0x0414 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_USDHC2_RESET_B 0x01E8 0x0418 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_LPTMR2_ALT1 0x01E8 0x0418 0x0578 0x01 0x01 +#define IMX952_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01E8 0x0418 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x01E8 0x0418 0x04D8 0x04 0x01 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x01E8 0x0418 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01EC 0x041C 0x0000 0x00 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01EC 0x041C 0x0000 0x01 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01EC 0x041C 0x0000 0x02 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01EC 0x041C 0x0000 0x03 0x00 +#define IMX952_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01EC 0x041C 0x0000 0x04 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_0 0x01EC 0x041C 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01F0 0x0420 0x0000 0x00 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01F0 0x0420 0x0000 0x01 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01F0 0x0420 0x0000 0x02 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01F0 0x0420 0x0000 0x03 0x00 +#define IMX952_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01F0 0x0420 0x0000 0x04 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_1 0x01F0 0x0420 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01F4 0x0424 0x0000 0x00 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01F4 0x0424 0x0000 0x01 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01F4 0x0424 0x0000 0x02 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01F4 0x0424 0x0000 0x03 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01F4 0x0424 0x0000 0x04 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_2 0x01F4 0x0424 0x0000 0x05 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01F4 0x0424 0x0000 0x06 0x00 + +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01F8 0x0428 0x0000 0x00 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01F8 0x0428 0x0000 0x02 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01F8 0x0428 0x0000 0x03 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01F8 0x0428 0x0000 0x04 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_3 0x01F8 0x0428 0x0000 0x05 0x00 + +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01FC 0x042C 0x0000 0x00 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_UART_CSSI_RX 0x01FC 0x042C 0x0000 0x01 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01FC 0x042C 0x0000 0x02 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01FC 0x042C 0x0000 0x03 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_4 0x01FC 0x042C 0x0000 0x05 0x00 + +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x0200 0x0430 0x0000 0x00 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_UART_CSSI_TX 0x0200 0x0430 0x0000 0x01 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x0200 0x0430 0x0000 0x02 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x0200 0x0430 0x0000 0x03 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_5 0x0200 0x0430 0x0000 0x05 0x00 + +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x0204 0x0434 0x0000 0x00 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x0204 0x0434 0x0000 0x01 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x0204 0x0434 0x0000 0x02 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x0204 0x0434 0x0000 0x03 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x0204 0x0434 0x0474 0x04 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_6 0x0204 0x0434 0x0000 0x05 0x00 + +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x0208 0x0438 0x0000 0x00 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x0208 0x0438 0x0000 0x01 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x0208 0x0438 0x0000 0x02 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x0208 0x0438 0x0000 0x03 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_7 0x0208 0x0438 0x0000 0x05 0x00 + +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x020C 0x043C 0x0000 0x00 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x020C 0x043C 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT0 0x020C 0x043C 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x020C 0x043C 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x020C 0x043C 0x0000 0x06 0x00 + +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x0210 0x0440 0x0464 0x00 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x0210 0x0440 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x0210 0x0440 0x0000 0x02 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x0210 0x0440 0x0000 0x03 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT1 0x0210 0x0440 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x0210 0x0440 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x0210 0x0440 0x0460 0x06 0x00 + +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_1 0x0214 0x0444 0x0468 0x00 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_NMI 0x0214 0x0444 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x0214 0x0444 0x0000 0x02 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x0214 0x0444 0x0000 0x03 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT2 0x0214 0x0444 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_10 0x0214 0x0444 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0214 0x0444 0x0478 0x06 0x00 + +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x0218 0x0448 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_1 0x0218 0x0448 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x0218 0x0448 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x0218 0x0448 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x0218 0x0448 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x0218 0x0448 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x021C 0x044C 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x021C 0x044C 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x021C 0x044C 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x021C 0x044C 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x021C 0x044C 0x0460 0x04 0x01 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x021C 0x044C 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x0220 0x0450 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x0220 0x0450 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x0220 0x0450 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x0220 0x0450 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x0220 0x0450 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x0220 0x0450 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x0224 0x0454 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x0224 0x0454 0x0474 0x01 0x01 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x0224 0x0454 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x0224 0x0454 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x0224 0x0454 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x0224 0x0454 0x0000 0x05 0x00 + +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x0228 0x0458 0x0000 0x00 0x00 +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x0228 0x0458 0x0000 0x01 0x00 +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_15 0x0228 0x0458 0x0000 0x05 0x00 +#endif /* __DTS_IMX952_PINFUNC_H__ */ diff --git a/arch/arm64/boot/dts/freescale/imx952-power.h b/arch/arm64/boot/dts/freescale/imx952-power.h new file mode 100644 index 000000000000..1d0fb8c93e24 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-power.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX952_POWER_H__ +#define __IMX952_POWER_H__ + +#define IMX952_PD_ANA 0 +#define IMX952_PD_AON 1 +#define IMX952_PD_BBSM 2 +#define IMX952_PD_CAMERA 3 +#define IMX952_PD_CCMSRCGPC 4 +#define IMX952_PD_A55C0 5 +#define IMX952_PD_A55C1 6 +#define IMX952_PD_A55C2 7 +#define IMX952_PD_A55C3 8 +#define IMX952_PD_A55P 9 +#define IMX952_PD_DDR 10 +#define IMX952_PD_DISPLAY 11 +#define IMX952_PD_GPU 12 +#define IMX952_PD_HSIO_TOP 13 +#define IMX952_PD_HSIO_WAON 14 +#define IMX952_PD_M7 15 +#define IMX952_PD_NETC 16 +#define IMX952_PD_NOC 17 +#define IMX952_PD_NPU 18 +#define IMX952_PD_VPU 19 +#define IMX952_PD_WAKEUP 20 + +#define IMX952_PERF_M33 0 +#define IMX952_PERF_WAKEUP 1 +#define IMX952_PERF_M7 2 +#define IMX952_PERF_DRAM 3 +#define IMX952_PERF_HSIO 4 +#define IMX952_PERF_NPU 5 +#define IMX952_PERF_NOC 6 +#define IMX952_PERF_A55 7 +#define IMX952_PERF_GPU 8 +#define IMX952_PERF_VPU 9 +#define IMX952_PERF_CAM 10 +#define IMX952_PERF_DISP 11 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi new file mode 100644 index 000000000000..33bde271d394 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -0,0 +1,1248 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2025 NXP + */ + +#include +#include +#include + +#include "imx952-clock.h" +#include "imx952-pinfunc.h" +#include "imx952-power.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; + + clk_ldb_pll_pixel: clock-ldb-pll-div7 { + compatible = "fixed-factor-clock"; + clocks = <&scmi_clk IMX952_CLK_LDBPLL>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + clock-output-names = "ldb_pll_div7"; + }; + + clk_osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + A55_2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + A55_3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <3>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&A55_0>; + }; + + core1 { + cpu = <&A55_1>; + }; + + core2 { + cpu = <&A55_2>; + }; + + core3 { + cpu = <&A55_3>; + }; + }; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; + shmem = <&scmi_buf0>, <&scmi_buf1>; + #address-cells = <1>; + #size-cells = <0>; + arm,max-rx-timeout-ms = <5000>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_sys_power: protocol@12 { + reg = <0x12>; + }; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_iomuxc: protocol@19 { + reg = <0x19>; + }; + + scmi_lmm: protocol@80 { + reg = <0x80>; + }; + + scmi_bbm: protocol@81 { + reg = <0x81>; + }; + + scmi_cpu: protocol@82 { + reg = <0x82>; + }; + + scmi_misc: protocol@84 { + reg = <0x84>; + }; + }; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + dma-noncoherent; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: msi-controller@48040000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x48040000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + dma-noncoherent; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk_dummy>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk_dummy>; + clock-names = "main_clk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>, + <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x42000000 0x0 0x800000>; + ranges = <0x42000000 0x0 0x42000000 0x8000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + mu7: mailbox@42050000 { + compatible = "fsl,imx95-mu"; + reg = <0x42050000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: watchdog@420b0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x420b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm3: pwm@42100000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42100000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm4: pwm@42110000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42110000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42120000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42120000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42130000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42130000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c@42140000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42140000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_I3C2SLOW>, + <&clk_dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42150000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42150000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C3>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42160000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42160000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C4>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi3: spi@42170000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42170000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI3>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi4: spi@42180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42180000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI4>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart3: serial@42190000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42190000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART3>; + clock-names = "ipg"; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart4: serial@421a0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART4>; + clock-names = "ipg"; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart5: serial@421b0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421b0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART5>; + clock-names = "ipg"; + dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart6: serial@421c0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421c0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART6>; + clock-names = "ipg"; + dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan2: can@421d0000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x421d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_CAN2>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan3: can@42220000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x42220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_CAN3>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + lpuart7: serial@422b0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x422b0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART7>; + clock-names = "ipg"; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart8: serial@422c0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x422c0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART8>; + clock-names = "ipg"; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpi2c5: i2c@422d0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C5>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c6: i2c@422e0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422e0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C6>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c7: i2c@422f0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C7>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c8: i2c@42300000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42300000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C8>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi5: spi@42310000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42310000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI5>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi6: spi@42320000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42320000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI6>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi7: spi@42330000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42330000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI7>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi8: spi@42340000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42340000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI8>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mu8: mailbox@42350000 { + compatible = "fsl,imx95-mu"; + reg = <0x42350000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x42800000 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x42800000 0x0 0x42800000 0x800000>; + + edma2: dma-controller@42800000 { + compatible = "fsl,imx95-edma5"; + reg = <0x42800000 0x210000>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <64>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; //error irq + }; + + usdhc1: mmc@42c20000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c20000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42c30000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c30000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@42c40000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c40000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43810000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 4 32>; + ngpios = <32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43820000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>, + <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>; + ngpios = <32>; + }; + + gpio4: gpio@43840000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43840000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>; + ngpios = <30>; + }; + + gpio5: gpio@43850000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43850000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>; + ngpios = <18>; + }; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x44000000 0x0 0x800000>; + ranges = <0x44000000 0x0 0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + edma1: dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x210000>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; //error irq + }; + + mu1: mailbox@44220000 { + compatible = "fsl,imx95-mu"; + reg = <0x44220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@44290000 { + compatible = "nxp,imx95-sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = ; + clocks = <&clk_osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_I3C1SLOW>, + <&clk_dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C1>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C2>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI1>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI2>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART1>; + clock-names = "ipg"; + dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART2>; + clock-names = "ipg"; + dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_CAN1>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + ; + clocks = <&scmi_clk IMX952_CLK_ADC>; + clock-names = "ipg"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x1000>; + ranges; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram0: sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + }; + + mu3: mailbox@445d0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu5: mailbox@44610000 { + compatible = "fsl,imx95-mu"; + reg = <0x44610000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu6: mailbox@44630000 { + compatible = "fsl,imx95-mu"; + reg = <0x44630000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + v2x_mu0: mailbox@47300000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47300000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu2: mailbox@47320000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47320000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu3: mailbox@47330000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47330000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu4: mailbox@47340000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47340000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu: mailbox@47350000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47350000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + /* GPIO1 is under exclusive control of System Manager */ + gpio1: gpio@47400000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x47400000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_M33>, + <&scmi_clk IMX952_CLK_M33>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 123 16>; + ngpios = <16>; + status = "disabled"; + }; + + elemu0: mailbox@47520000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47520000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu1: mailbox@47530000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47530000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu2: mailbox@47540000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47540000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu3: mailbox@47550000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47550000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + elemu4: mailbox@47560000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47560000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu5: mailbox@47570000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47570000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + usb1: usb@4c100000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c100000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, + <&scmi_clk IMX952_CLK_OSC32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x0 0x4c100200 0x0 0x200>, + <0x0 0x4c010010 0x0 0x4>; + }; + + usb2: usb@4c200000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c200000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, + <&scmi_clk IMX952_CLK_OSC32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x0 0x4c200200 0x0 0x200>, + <0x0 0x4c010014 0x0 0x4>; + }; + }; +}; From a5aa8551d0046ec701e8962f83361165ccf640a4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Dec 2025 09:42:16 +0800 Subject: [PATCH 066/104] arm64: dts: freescale: Add i.MX952 EVK basic device tree Add i.MX952 EVK basic device tree, with UART1, SDHC[1,2] supported. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + arch/arm64/boot/dts/freescale/imx952-evk.dts | 217 +++++++++++++++++++ 2 files changed, 219 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx952-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index edb8332ed7e0..633f7c0e33af 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -430,6 +430,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-verdin-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx952-evk.dtb + imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo imx8mm-kontron-bl-lte-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts new file mode 100644 index 000000000000..2c753fcbae3c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include "imx952.dtsi" + +/ { + model = "NXP i.MX952 EVK board"; + compatible = "fsl,imx952-evk", "fsl,imx952"; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x15fe + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x13fe + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x13fe + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x13fe + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x13fe + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x13fe + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x13fe + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x13fe + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x13fe + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x13fe + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e + >; + }; +}; From c8614121539494c6dad84df074aa5d89e2d845f7 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 23 Dec 2025 17:05:56 +0800 Subject: [PATCH 067/104] arm64: dts: imx94: add xspi device node imx94 has two xspi, add these device nodes. Signed-off-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx94.dtsi | 34 +++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 4fdec712307f..d2f31c8caf6e 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -629,7 +629,7 @@ aips3: bus@42800000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0 0x42800000 0 0x800000>; ranges = <0x42800000 0x0 0x42800000 0x800000>, - <0x28000000 0x0 0x28000000 0x1000000>; + <0x24000000 0x0 0x24000000 0xc000000>; #address-cells = <1>; #size-cells = <1>; @@ -785,6 +785,38 @@ mu17: mailbox@42b60000 { #mbox-cells = <2>; status = "disabled"; }; + + xspi1: spi@42b90000 { + compatible = "nxp,imx94-xspi"; + reg = <0x42b90000 0x50000>, <0x28000000 0x08000000>; + reg-names = "base", "mmap"; + interrupts = , // EENV0 + , // EENV1 + , // EENV2 + , // EENV3 + ; // EENV4 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_XSPI1>; + clock-names = "per"; + status = "disabled"; + }; + + xspi2: spi@42be0000 { + compatible = "nxp,imx94-xspi"; + reg = <0x42be0000 0x50000>, <0x24000000 0x04000000>; + reg-names = "base", "mmap"; + interrupts = , // EENV0 + , // EENV1 + , // EENV2 + , // EENV3 + ; // EENV4 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_XSPI2>; + clock-names = "per"; + status = "disabled"; + }; }; gpio2: gpio@43810000 { From 5a0ee673a793c977e94c30ff8b5ac81d8e6a3c0f Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 23 Dec 2025 17:05:57 +0800 Subject: [PATCH 068/104] arm64: dts: imx94: add mt35xu512aba spi nor support Add mt35xu512aba spi nor support on imx943-evk board. This nor chip support OCT DTR mode. For the reset pin, since the nor chip side need 1.8v IO voltage for reset pin, but the IO expander side use 3.3v IO voltage, so to make circuit safe, need to config the pad as OPEN DRAIN. Signed-off-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 34 ++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 98938391497e..31fa9675cee1 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -738,6 +738,22 @@ pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp { IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e >; }; + + pinctrl_xspi1: xspi1grp { + fsl,pins = < + IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe + IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B 0x3fe + IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0 0x3fe + IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1 0x3fe + IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2 0x3fe + IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3 0x3fe + IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4 0x3fe + IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5 0x3fe + IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6 0x3fe + IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7 0x3fe + IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe + >; + }; }; &usdhc1 { @@ -769,3 +785,21 @@ &wdog3 { fsl,ext-reset-output; status = "okay"; }; + +&xspi1 { + pinctrl-0 = <&pinctrl_xspi1>; + pinctrl-1 = <&pinctrl_xspi1>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mt35xu512aba: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + reset-gpios = <&pcal6416_i2c6_u50 15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + spi-max-frequency = <200000000>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + }; +}; From 5ceddf531b7f5ec4e505f329a9ccc7ef18f7de4e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:25 +0100 Subject: [PATCH 069/104] arm64: dts: freescale: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso | 2 +- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 2 +- arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ef80bf6a604f..b07022e3b6d5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -278,7 +278,7 @@ sfp: efuse@1e80000 { clock-names = "sfp"; }; - sec_mon: sec_mon@1e90000 { + sec_mon: sec-mon@1e90000 { compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; reg = <0x0 0x1e90000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 22173d69713d..6fefe837f434 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -851,7 +851,7 @@ pcie1: pcie@3400000 { status = "disabled"; }; - pcie_ep1: pcie_ep@3400000 { + pcie_ep1: pcie-ep@3400000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03400000 0x0 0x00100000>, <0x40 0x00000000 0x8 0x00000000>; @@ -890,7 +890,7 @@ pcie2: pcie@3500000 { status = "disabled"; }; - pcie_ep2: pcie_ep@3500000 { + pcie_ep2: pcie-ep@3500000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03500000 0x0 0x00100000>, <0x48 0x00000000 0x8 0x00000000>; @@ -929,7 +929,7 @@ pcie3: pcie@3600000 { status = "disabled"; }; - pcie_ep3: pcie_ep@3600000 { + pcie_ep3: pcie-ep@3600000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03600000 0x0 0x00100000>, <0x50 0x00000000 0x8 0x00000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso index 43d5905f3d72..414f44b85564 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso @@ -33,7 +33,7 @@ vdev0vring1: vdev0vring1@b8008000 { no-map; }; - rsc_table: rsc_table@b80ff000 { + rsc_table: rsc-table@b80ff000 { reg = <0 0xb80ff000 0 0x1000>; no-map; }; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index b934295bac15..3081513cfc04 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -215,7 +215,7 @@ rsc_table: rsc-table@88220000 { no-map; }; - vpu_boot: vpu_boot@a0000000 { + vpu_boot: vpu-boot@a0000000 { reg = <0 0xa0000000 0 0x100000>; no-map; }; diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi index 43418844701b..456129f4a682 100644 --- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi @@ -40,7 +40,7 @@ linux_cma: linux,cma { linux,cma-default; }; - vpu_boot: vpu_boot@a0000000 { + vpu_boot: vpu-boot@a0000000 { reg = <0 0xa0000000 0 0x100000>; no-map; }; From 7dce6d3909cb95108d92fc95dedf18d488e9ccae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:26 +0100 Subject: [PATCH 070/104] arm64: dts: freescale: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' and before '{' characters. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts | 2 +- .../dts/freescale/imx8mp-hummingboard-pulse-common.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx93-var-som.dtsi | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts index 138f21e257aa..242fa930bd2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts @@ -117,7 +117,7 @@ &aud2htx { }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi index 825ad6a2ba14..fa7cb9759d01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi @@ -141,7 +141,7 @@ mpcie-reset-hog { }; &i2c3 { - carrier_eeprom: eeprom@57{ + carrier_eeprom: eeprom@57 { compatible = "st,24c02", "atmel,24c02"; reg = <0x57>; pagesize = <16>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi index 4e6629f940bf..3cdb0bc0ab72 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi @@ -198,7 +198,7 @@ buck2: BUCK2 { nxp,dvs-standby-voltage = <850000>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -206,7 +206,7 @@ buck4: BUCK4{ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -264,7 +264,7 @@ ldo5: LDO5 { }; }; - som_eeprom: eeprom@50{ + som_eeprom: eeprom@50 { compatible = "st,24c01", "atmel,24c01"; reg = <0x50>; pagesize = <16>; diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi index 2dc8b18ae91e..24063bf8183d 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi @@ -131,7 +131,7 @@ buck2: BUCK2 { regulator-ramp-delay = <3125>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -139,7 +139,7 @@ buck4: BUCK4{ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; From 202266aee7d54e90a861fcc364993100414b8148 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:27 +0100 Subject: [PATCH 071/104] arm64: dts: freescale: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1088a-ten64.dts | 4 +-- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 32 +++++++++---------- .../dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts | 16 +++++----- .../dts/freescale/imx8mp-libra-rdk-fpsc.dts | 2 +- .../freescale/imx8mp-phyboard-pollux-rdk.dts | 2 +- .../dts/freescale/imx8mp-toradex-smarc.dtsi | 6 ++-- .../imx8mp-tqma8mpql-mba8mp-ras314.dts | 2 +- .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 2 +- .../dts/freescale/imx8mq-librem5-devkit.dts | 2 +- .../boot/dts/freescale/imx8mq-librem5.dtsi | 6 ++-- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 12 +++---- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 4 +-- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 6 ++-- .../boot/dts/freescale/imx8x-colibri.dtsi | 2 +- .../boot/dts/freescale/imx95-15x15-evk.dts | 2 +- .../dts/freescale/imx95-toradex-smarc.dtsi | 2 +- arch/arm64/boot/dts/freescale/s32g3.dtsi | 4 +-- .../boot/dts/freescale/s32gxxxa-evb.dtsi | 20 ++++++------ .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 20 ++++++------ 21 files changed, 75 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts index 71765ec91745..f51508952d51 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts @@ -392,13 +392,13 @@ partition@800000 { /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */ partition@2800000 { label = "ubia"; - reg = <0x2800000 0x6C00000>; + reg = <0x2800000 0x6c00000>; }; /* ubib (second OpenWrt) */ partition@9400000 { label = "ubib"; - reg = <0x9400000 0x6C00000>; + reg = <0x9400000 0x6c00000>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index b2f6cd237be0..99016768b73f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -684,7 +684,7 @@ smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; #iommu-cells = <1>; - stream-match-mask = <0x7C00>; + stream-match-mask = <0x7c00>; dma-coherent; #global-interrupts = <12>; // global secure fault diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 9421fdd7e30e..6073e426774a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -881,7 +881,7 @@ smmu: iommu@5000000 { reg = <0 0x5000000 0 0x800000>; #global-interrupts = <12>; #iommu-cells = <1>; - stream-match-mask = <0x7C00>; + stream-match-mask = <0x7c00>; dma-coherent; interrupts = , /* global secure fault */ , /* combined secure interrupt */ diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index d899c0355e51..853b01452813 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -35,7 +35,7 @@ cpu0: cpu@0 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; @@ -52,7 +52,7 @@ cpu1: cpu@1 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; @@ -69,7 +69,7 @@ cpu100: cpu@100 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; @@ -86,7 +86,7 @@ cpu101: cpu@101 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; @@ -103,7 +103,7 @@ cpu200: cpu@200 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; @@ -120,7 +120,7 @@ cpu201: cpu@201 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; @@ -137,7 +137,7 @@ cpu300: cpu@300 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; @@ -154,7 +154,7 @@ cpu301: cpu@301 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; @@ -171,7 +171,7 @@ cpu400: cpu@400 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; @@ -188,7 +188,7 @@ cpu401: cpu@401 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; @@ -205,7 +205,7 @@ cpu500: cpu@500 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; @@ -222,7 +222,7 @@ cpu501: cpu@501 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; @@ -239,7 +239,7 @@ cpu600: cpu@600 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; @@ -256,7 +256,7 @@ cpu601: cpu@601 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; @@ -273,7 +273,7 @@ cpu700: cpu@700 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; @@ -290,7 +290,7 @@ cpu701: cpu@701 { d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index 0d009f4be804..664f4a6950a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -147,23 +147,23 @@ pinctrl_gpioled: gpioledgrp { }; pinctrl_i2c2: i2c2grp { - fsl,pins = , - ; + fsl,pins = , + ; }; pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = , - ; + fsl,pins = , + ; }; pinctrl_i2c3: i2c3grp { - fsl,pins = , - ; + fsl,pins = , + ; }; pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = , - ; + fsl,pins = , + ; }; pinctrl_pwm3: pwm3grp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts index ec1f10022248..86b8c5af4153 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts @@ -226,7 +226,7 @@ MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x12 }; pinctrl_rtc: rtcgrp { fsl,pins = < - MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1C0 + MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 90ec73068a6d..0fe52c73fc8f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -501,7 +501,7 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 pinctrl_rtc: rtcgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi index bebe19eb360f..0348da385f23 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi @@ -1044,7 +1044,7 @@ pinctrl_lvds_dsi_sel: lvdsdsiselgrp { }; pinctrl_mcu_int: mcuintgrp { - fsl,pins = ; /* MCU_INT# */ + fsl,pins = ; /* MCU_INT# */ }; /* SMARC LCD1_BKLT_PWM */ @@ -1096,12 +1096,12 @@ pinctrl_sai3: sai3grp { /* SMARC SLEEP# */ pinctrl_sleep: sleepgrp { - fsl,pins = ; /* SMARC S149 - SLEEP# */ + fsl,pins = ; /* SMARC S149 - SLEEP# */ }; /* SMARC SMB_ALERT# */ pinctrl_smb_alert: smbalertgrp { - fsl,pins = ; /* SMARC P1 - SMB_ALERT# */ + fsl,pins = ; /* SMARC P1 - SMB_ALERT# */ }; /* TPM_CS# */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index 6e927ff1e967..b7f69c92b774 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -134,7 +134,7 @@ linux,cma { compatible = "shared-dma-pool"; reusable; size = <0 0x38000000>; - alloc-ranges = <0 0x40000000 0 0xB0000000>; + alloc-ranges = <0 0x40000000 0 0xb0000000>; linux,cma-default; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index fdfe246c5640..ad49bf85a04d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -228,7 +228,7 @@ linux,cma { compatible = "shared-dma-pool"; reusable; size = <0 0x38000000>; - alloc-ranges = <0 0x40000000 0 0xB0000000>; + alloc-ranges = <0 0x40000000 0 0xb0000000>; linux,cma-default; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index d9f203c79519..aadaeef928bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -633,7 +633,7 @@ MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ pinctrl_hpdet: hpdetgrp { fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */ + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xc0 /* HP_DET */ >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 9e0e2d7271ef..2975e9451661 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -536,9 +536,9 @@ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 pinctrl_keys: keysgrp { fsl,pins = < /* VOL- */ - MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 + MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01c0 /* VOL+ */ - MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 + MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01c0 >; }; @@ -620,7 +620,7 @@ MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 pinctrl_tcpc: tcpcgrp { fsl,pins = < /* TCPC_INT */ - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 779d9f78fb81..7d4574c6de1d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -1214,17 +1214,17 @@ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c pinctrl_mipi_csi0: mipi-csi0grp { fsl,pins = < - IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 - IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 - IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xc0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xc0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041 >; }; pinctrl_mipi_csi1: mipi-csi1grp { fsl,pins = < - IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 - IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 - IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xc0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xc0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xc0000041 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 9e7309a0ca51..f7e28f22343a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -137,7 +137,7 @@ A72_0: cpu@100 { reg = <0x0 0x100>; clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; @@ -241,7 +241,7 @@ opp-1596000000 { gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ - <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x51b00000 0 0xc0000>, /* GICR */ <0x0 0x52000000 0 0x2000>, /* GICC */ <0x0 0x52010000 0 0x1000>, /* GICH */ <0x0 0x52020000 0 0x20000>; /* GICV */ diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 50a97c0297c7..40a0bc9f4e84 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -1062,9 +1062,9 @@ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 pinctrl_mipi_csi0: mipi-csi0grp { fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 - IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 - IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xc0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xc0000041 + IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 8e9e841cc828..014808774b0e 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -623,7 +623,7 @@ pinctrl_csi_ctl: csictlgrp { }; pinctrl_csi_mclk: csimclkgrp { - fsl,pins = ; /* SODIMM 75 / X3-12 */ + fsl,pins = ; /* SODIMM 75 / X3-12 */ }; pinctrl_ext_io0: extio0grp { diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 3081513cfc04..d4184fb8b28c 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -178,7 +178,7 @@ reserved-memory { linux_cma: linux,cma { compatible = "shared-dma-pool"; - alloc-ranges = <0 0x80000000 0 0x7F000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; reusable; size = <0 0x3c000000>; linux,cma-default; diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index afbdadcb3686..a0752f21edf9 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -153,7 +153,7 @@ linux_cma: linux,cma { compatible = "shared-dma-pool"; reusable; size = <0 0x3c000000>; - alloc-ranges = <0 0x80000000 0 0x7F000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; linux,cma-default; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index eff7673e7f34..e314f3c7d61d 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -641,9 +641,9 @@ swt6: watchdog@40208000 { status = "disabled"; }; - swt7: watchdog@4020C000 { + swt7: watchdog@4020c000 { compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; - reg = <0x4020C000 0x1000>; + reg = <0x4020c000 0x1000>; clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; clock-names = "counter", "module", "register"; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi index f1969cdcef19..803ff4531077 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -197,16 +197,16 @@ dspi1-grp2 { }; dspi1-grp3 { - pinmux = <0x5F0>; + pinmux = <0x5f0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi1-grp4 { - pinmux = <0x3D92>, - <0x3DA2>, - <0x3DB2>; + pinmux = <0x3d92>, + <0x3da2>, + <0x3db2>; }; }; @@ -219,26 +219,26 @@ dspi5-grp0 { }; dspi5-grp1 { - pinmux = <0xA0>; + pinmux = <0xa0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi5-grp2 { - pinmux = <0x3ED2>, - <0x3EE2>, - <0x3EF2>; + pinmux = <0x3ed2>, + <0x3ee2>, + <0x3ef2>; }; dspi5-grp3 { - pinmux = <0xB3>; + pinmux = <0xb3>; output-enable; slew-rate = <150>; }; dspi5-grp4 { - pinmux = <0xC3>; + pinmux = <0xc3>; output-enable; input-enable; slew-rate = <150>; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi index 3bc3335c9248..979868f6d2c5 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi @@ -151,16 +151,16 @@ dspi1-grp2 { }; dspi1-grp3 { - pinmux = <0x5F0>; + pinmux = <0x5f0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi1-grp4 { - pinmux = <0x3D92>, - <0x3DA2>, - <0x3DB2>; + pinmux = <0x3d92>, + <0x3da2>, + <0x3db2>; }; }; @@ -173,26 +173,26 @@ dspi5-grp0 { }; dspi5-grp1 { - pinmux = <0xA0>; + pinmux = <0xa0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi5-grp2 { - pinmux = <0x3ED2>, - <0x3EE2>, - <0x3EF2>; + pinmux = <0x3ed2>, + <0x3ee2>, + <0x3ef2>; }; dspi5-grp3 { - pinmux = <0xB3>; + pinmux = <0xb3>; output-enable; slew-rate = <150>; }; dspi5-grp4 { - pinmux = <0xC3>; + pinmux = <0xc3>; output-enable; input-enable; slew-rate = <150>; From eb2615ad4643c9e3fc6a3c9082084cec744402b9 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 23 Dec 2025 17:28:28 +0100 Subject: [PATCH 072/104] arm64: dts: imx8qm: Add CPU cluster labels Add labels to the cpu cluster nodes to prepare for the addition of the i.MX8QP SoC in which these nodes would need to be adjusted from another DT file. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index f7e28f22343a..ae7de9f99055 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -38,7 +38,7 @@ cpus { #size-cells = <0>; cpu-map { - cluster0 { + cluster0: cluster0 { core0 { cpu = <&A53_0>; }; @@ -53,7 +53,7 @@ core3 { }; }; - cluster1 { + cluster1: cluster1 { core0 { cpu = <&A72_0>; }; From 3669332babd0038b714abd3e360be130fd401022 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 23 Dec 2025 17:28:29 +0100 Subject: [PATCH 073/104] arm64: dts: freescale: Add NXP i.MX8QP SoC dtsi Add support for NXP i.MX8QP SoC, this is pin to pin compatible variant of the i.MX8QM, with a slower GPU and one Cortex A72 core instead of two. Link: https://www.nxp.com/products/i.MX8 Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qp.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qp.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qp.dtsi b/arch/arm64/boot/dts/freescale/imx8qp.dtsi new file mode 100644 index 000000000000..26af9c5a51c5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) + +#include "imx8qm.dtsi" + +/delete-node/ &A72_1; + +&cluster1 { + /delete-node/ core1; +}; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&thermal_zones { + cpu1-thermal { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; From db97615aea6602ce0f81f320eced9574f808b091 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 23 Dec 2025 17:28:30 +0100 Subject: [PATCH 074/104] arm64: dts: freescale: Add Apalis iMX8QP Add support for the Apalis iMX8QP SoM mated with Apalis Ixora and Apalis Evaluation board. Apalis iMX8QP is a variant of the Apalis iMX8QM, using an NXP i.MX8QP SoC instead of the i.MX8QM. The two SoCs are pin to pin compatible, with the i.MX8QP being a lower end variant, with a slower GPU and one Cortex A72 core instead of two. The two Apalis SoMs variants share the same schematics and PCB, and the iMX8QP variant exists only on revision V1.1 of board. Link: https://www.nxp.com/products/i.MX8 Link: https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 5 ++++ .../imx8qp-apalis-v1.1-eval-v1.2.dts | 26 +++++++++++++++++++ .../dts/freescale/imx8qp-apalis-v1.1-eval.dts | 16 ++++++++++++ .../imx8qp-apalis-v1.1-ixora-v1.1.dts | 16 ++++++++++++ .../imx8qp-apalis-v1.1-ixora-v1.2.dts | 16 ++++++++++++ .../dts/freescale/imx8qp-apalis-v1.1.dtsi | 16 ++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 633f7c0e33af..c770b1212a34 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -363,6 +363,11 @@ dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi1.dtb imx8qm-mek-ov5640-dual-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo imx8qm-mek-ov5640-csi1.dtbo dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-dual.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-eval.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-eval-v1.2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-ixora-v1.1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-ixora-v1.2.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts new file mode 100644 index 000000000000..b5318de67cb0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-v1.1-eval-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /delete-property/ no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /delete-property/ no-1-8-v; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..d558cff2582f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8-v1.1-eval", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts new file mode 100644 index 000000000000..a73a6324f552 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.1 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts new file mode 100644 index 000000000000..71568d7ec8e5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.2 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi new file mode 100644 index 000000000000..1e5311512344 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx8qp.dtsi" +#include "imx8-apalis-v1.1.dtsi" + +&cooling_maps_map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; From d703856872d5b875f46d1a781af1df6795780c20 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 31 Oct 2025 13:49:41 +0100 Subject: [PATCH 075/104] arm64: dts: colibri-imx8x: Add backlight Add a backlight node to colibri-imx8x. The node can be enabled from an overlay once display output is implemented. Signed-off-by: Philippe Schenker Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 014808774b0e..b19900b2272a 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -3,7 +3,21 @@ * Copyright 2019 Toradex */ +#include "dt-bindings/pwm/pwm.h" + / { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + power-supply = <®_module_3v3>; + pwms = <&adma_pwm 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + chosen { stdout-path = &lpuart3; }; From d4dc56d8224d1c5a20e06939c817b28a60fbc35e Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Fri, 31 Oct 2025 13:49:42 +0100 Subject: [PATCH 076/104] arm64: dts: colibri-imx8x: Add wi-fi 32kHz clock The Wi-Fi module requires a 32kHz clock to support Wi-Fi/BT low power operation. Setting the pinmuxing option on the connected pin to 32kHz is all needed to generated the signal. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index b19900b2272a..7c258e8b5aa2 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -490,7 +490,7 @@ &mu1_m0 { /* On-module PCIe for Wi-Fi */ &pcieb { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>; phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; From abc8424e7f967c8dcbafdd99ff688e7a35441128 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 31 Oct 2025 13:49:43 +0100 Subject: [PATCH 077/104] arm64: dts: colibri-imx8x: Add cma memory Add CMA in device tree and set its size to 416MiB for all Colibri iMX8X. The size is tuned to be enough to play full HD video using gst-play and to fit in the SKU with the lowest amount of RAM (1GB). Signed-off-by: Philippe Schenker Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 7c258e8b5aa2..47895ff8cb24 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -86,6 +86,19 @@ reg_usbh_vbus: regulator-usbh-vbus { regulator-name = "usbh_vbus"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + linux,cma-default; + reusable; + size = <0 0x1a000000>; + }; + }; + sound-card { compatible = "simple-audio-card"; simple-audio-card,bitclock-master = <&dailink_master>; From 6f6c18cba16fe5a8e6d60e5fd277059c2d18dbcc Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 29 Dec 2025 11:31:01 -0500 Subject: [PATCH 078/104] arm64: dts: imx8mp-evk: add camera ov5640 and related nodes Add camera ov5640 and related nodes. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 80 ++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 7ededc1a0617..b256be710ea1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -84,6 +84,27 @@ pcie0_refclk: pcie0-refclk { clock-frequency = <100000000>; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_2v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + reg_audio_3v3: regulator-audio-3v3 { compatible = "regulator-fixed"; regulator-name = "audio-3v3"; @@ -548,6 +569,30 @@ &i2c2 { pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_2v8>; + DVDD-supply = <®_1v5>; + DOVDD-supply = <®_1v8>; + status = "okay"; + + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + }; + }; + }; + hdmi@3d { compatible = "adi,adv7535"; reg = <0x3d>; @@ -652,6 +697,10 @@ &i2c5 { */ }; +&isi_0 { + status = "okay"; +}; + &lcdif1 { status = "okay"; }; @@ -670,6 +719,19 @@ &micfil { status = "okay"; }; +&mipi_csi_0 { + status = "okay"; + + ports { + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { samsung,esc-clock-frequency = <10000000>; status = "okay"; @@ -843,6 +905,24 @@ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 >; }; + pinctrl_csi_mclk: csi_mclk_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x50 + >; + }; + + pinctrl_csi0_pwn: csi0_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10 + >; + }; + + pinctrl_csi0_rst: csi0_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 From 00398481e06b53fa120b408a0020d3281cfc8121 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 30 Dec 2025 02:40:35 +0100 Subject: [PATCH 079/104] arm64: dts: imx8mp: Update Data Modul i.MX8M Plus eDM SBC DT to rev.903 Update the DT to match newest Data Modul i.MX8M Plus eDM SBC rev.903 board which implements significant changes. Keep some of the rev.900 and rev.902 nodes in the DT so that a DTO can be used to support old rev.900 and rev.902 boards easily. The changes from rev.900 to rev.902 are: - Both ethernet PHYs replaced from AR8031 to BCM54213PE - Both ethernet PHYs MDIO address changed - PCIe WiFi now comes with dedicated regulator - I2C TPM chip address - Additional GPIO expander for LVDS panel control added - Current EEPROM I2C address changed - Another optional EEPROM added onto another I2C bus The changes from rev.902 to rev.903 are: - Additional GPIO expander for WiFi and LVDS panel control added - Multiple GPIOs are reassigned Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../freescale/imx8mp-data-modul-edm-sbc.dts | 148 +++++++++++++++--- 1 file changed, 129 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts index 16078ff60ef0..7e46537a22a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts @@ -93,6 +93,17 @@ reg_panel_vcc: regulator-panel-vcc { status = "disabled"; }; + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + regulator-name = "WIFI_BT_RST#"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -190,7 +201,7 @@ &ecspi3 { /* Display connector SPI */ &eqos { /* First ethernet */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; - phy-handle = <&phy_eqos>; + phy-handle = <&phy_eqos_bcm>; phy-mode = "rgmii-id"; status = "okay"; @@ -200,7 +211,7 @@ mdio { #size-cells = <0>; /* Atheros AR8031 PHY */ - phy_eqos: ethernet-phy@0 { + phy_eqos_ath: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; /* @@ -213,6 +224,7 @@ phy_eqos: ethernet-phy@0 { reset-deassert-us = <10000>; qca,keep-pll-enabled; vddio-supply = <&vddio_eqos>; + status = "disabled"; vddio_eqos: vddio-regulator { regulator-name = "VDDIO_EQOS"; @@ -224,13 +236,27 @@ vddh_eqos: vddh-regulator { regulator-name = "VDDH_EQOS"; }; }; + + /* Broadcom BCM54213PE PHY */ + phy_eqos_bcm: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * Dedicated ENET_INT# and ENET_WOL# signals are + * unused, the PHY does not provide cable detect + * interrupt. + */ + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; }; }; &fec { /* Second ethernet */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; - phy-handle = <&phy_fec>; + phy-handle = <&phy_fec_bcm>; phy-mode = "rgmii-id"; fsl,magic-packet; status = "okay"; @@ -240,7 +266,7 @@ mdio { #size-cells = <0>; /* Atheros AR8031 PHY */ - phy_fec: ethernet-phy@0 { + phy_fec_ath: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; /* @@ -253,6 +279,7 @@ phy_fec: ethernet-phy@0 { reset-deassert-us = <10000>; qca,keep-pll-enabled; vddio-supply = <&vddio_fec>; + status = "disabled"; vddio_fec: vddio-regulator { regulator-name = "VDDIO_FEC"; @@ -264,6 +291,20 @@ vddh_fec: vddh-regulator { regulator-name = "VDDH_FEC"; }; }; + + /* Broadcom BCM54213PE PHY */ + phy_fec_bcm: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * Dedicated ENET_INT# and ENET_WOL# signals are + * unused, the PHY does not provide cable detect + * interrupt. + */ + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; }; }; @@ -378,13 +419,26 @@ usb-hub@2c { self-powered; }; - eeprom: eeprom@50 { + tpm: tpm@2e { + compatible = "st,st33tphf2ei2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; + + eeprom900: eeprom@50 { /* board rev.900 */ compatible = "atmel,24c32"; reg = <0x50>; pagesize = <32>; + status = "disabled"; + }; + + eeprom902: eeprom@51 { /* board rev.902 */ + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; }; rtc: rtc@68 { + #clock-cells = <1>; compatible = "st,m41t62"; reg = <0x68>; pinctrl-names = "default"; @@ -408,6 +462,46 @@ &i2c2 { scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + + gpiolvds: io-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "BL_ENABLE_V", "SEL_BL_12V", + "SEL_PANEL_5V", "SEL_PANEL_12V", + "SEL_BL_PWM", "SEL_BL_EN", + "REVERSE_SCAN_PANEL", "GND_REV903"; + }; + + gpiowifi: io-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "BL_LVDS_ENABLE_3V3", "BL_LVDS_PWM_3V3", + "M2_BT_WAKE_3V3#", "M2_W_DISABLE2_3V3#", + "TFT_PANEL_ENABLE_3V3", "TPM_RESET_3V3#", + "CSI2_PD_3V3", "CSI2_RESET_3V3#"; + + /* BL_LVDS_PWM_3V3 is patch-wired to BL_PWM_3V3 on rev.903 */ + pwm-input-hog { + gpio-hog; + gpios = <1 0>; + input; + line-name = "BL_LVDS_PWM_3V3_HOG"; + }; + }; + + eepromlvds: eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + /* Optional EEPROM, disabled by default. */ + status = "disabled"; + }; }; &i2c3 { @@ -521,6 +615,7 @@ &pcie { pinctrl-0 = <&pinctrl_pcie0>; fsl,max-link-speed = <3>; reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie0>; status = "okay"; }; @@ -598,7 +693,17 @@ &uart3 { /* A53 Debug */ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw55572-bt"; + brcm,requires-autobaud-mode; + clocks = <&rtc 0>; + clock-names = "txco"; + max-speed = <921600>; + shutdown-gpios = <&gpiowifi 3 GPIO_ACTIVE_HIGH>; + }; }; &usb3_phy0 { @@ -686,8 +791,6 @@ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 /* ENET_RST# */ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6 - /* ENET_INT# */ - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090 >; }; @@ -709,8 +812,6 @@ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f /* ENET2_RST# */ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6 - /* ENET2_INT# */ - MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 >; }; @@ -754,10 +855,6 @@ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090 /* PG_V_IN_VAR# */ MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000 - /* CSI2_PD_1V8 */ - MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0 - /* CSI2_RESET_1V8# */ - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0 /* DIS_USB_DN1 */ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 @@ -771,8 +868,14 @@ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0 /* GRAPHICS_PRSNT_1V8# */ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000 + /* TOUCH_RESET_3V3# */ + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 + /* TOUCH_INT# */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000140 /* CLK_CCM_CLKO1_3V3 */ MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10 + /* ENET_INT# (rev.900,901) or M2_WDIS_BTIRQ_3V3# (rev.903) */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000092 >; }; @@ -875,12 +978,10 @@ pinctrl_pcie0: pcie-grp { fsl,pins = < /* M2_PCIE_RST# */ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 - /* M2_W_DISABLE1_1V8# */ + /* M2_PCIE_WAKE_1V8# */ MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2 - /* M2_W_DISABLE2_1V8# */ - MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2 - /* CLK_M2_32K768 */ - MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14 + /* M2_UART_WAKE_1V8# */ + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000002 /* M2_PCIE_WAKE# */ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140 /* M2_PCIE_CLKREQ# */ @@ -974,6 +1075,8 @@ pinctrl_uart4: uart4-grp { fsl,pins = < MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x149 + MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x149 >; }; @@ -1100,4 +1203,11 @@ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26 >; }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + /* WIFI_BT_RST_3V3# */ + MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 + >; + }; }; From b4bf5e55899e8c2662a6f0e221128f590ac5f331 Mon Sep 17 00:00:00 2001 From: Joseph Guo Date: Tue, 30 Dec 2025 16:58:54 +0900 Subject: [PATCH 080/104] arm64: dts: freescale: Add FRDM-IMX91 basic support The FRDM i.MX 91 development board is a low-cost and compact developmentboard featuring the i.MX 91 applications processor: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91 Add FRDM-IMX91 board dts support. - Enable ADC1. - Enable lpuart1 and lpuart5. - Enable network eqos and fec. - Enable I2C bus and children nodes under I2C bus. - Enable USB and related nodes. - Enable uSDHC1, uSDHC2 and uSDHC3. - Enable MU1 and MU2. - Enable Watchdog3. - Enable MQS Co-developed-by: Tom Zheng Signed-off-by: Tom Zheng Co-developed-by: Steven Yang Signed-off-by: Steven Yang Reviewed-by: Andrew Lunn Reviewed-by: Francesco Valla Tested-by: Francesco Valla Signed-off-by: Joseph Guo Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx91-11x11-frdm.dts | 906 ++++++++++++++++++ 2 files changed, 907 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c770b1212a34..ce8f937c2315 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -386,6 +386,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts new file mode 100644 index 000000000000..0d1acf8a55a5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-11x11-frdm", "fsl,imx91"; + model = "NXP i.MX91 11x11 FRDM Board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &bbnsm_rtc; + rtc1 = &pcf2131; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + enable-gpios = <&pcal6524 23 GPIO_ACTIVE_LOW>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-k2 { + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + label = "Button K2"; + gpios = <&pcal6524 5 GPIO_PULL_UP>; + linux,code = ; + }; + + button-k3 { + interrupt-parent = <&pcal6524>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + label = "Button K3"; + gpios = <&pcal6524 6 GPIO_PULL_UP>; + linux,code = ; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power"; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + bootph-pre-ram; + bootph-some-ram; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * This regulator defined as PDn pin of the IW610 wifi module. + * IW610 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW610 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "reg_vdd_12v"; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vexp_3v3: regulator-vexp-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VEXP_3V3"; + vin-supply = <&buck4>; + gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vexp_5v: regulator-vexp-5v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VEXP_5V"; + gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + soc@0 { + bootph-all; + bootph-pre-ram; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + audio-codec = <&mqs1>; + audio-cpu = <&sai1>; + model = "mqs-audio"; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&clk { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + pinctrl-names = "default", "sleep"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; + pinctrl-names = "default", "sleep"; + phys = <&flexcan_phy>; + status = "okay"; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcal6408: gpio@20 { + compatible = "nxp,pcal9554b"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_usdhc3_vmmc>; + status = "okay"; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio3>; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2237500>; + regulator-min-microvolt = <650000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK4"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK5"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK6"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-name = "LDO1"; + }; + + ldo4: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO4"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + status = "okay"; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&mqs1 { + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + pinctrl-0 = <&pinctrl_mqs1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&sai1 { + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX91_PAD_GPIO_IO25__CAN2_TX 0x139e + MX91_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_flexcan2_sleep: flexcan2sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e + MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX91_PAD_GPIO_IO08__GPIO2_IO8 0x3fe + MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; + + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + bootph-pre-ram; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; From f0ed0e84445245e56aa73c4df8d99936a2ce8549 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 20 Oct 2025 15:00:42 -0400 Subject: [PATCH 081/104] arm64: dts: imx91: Add thermal-sensor and thermal-zone support Add thermal-sensor and thermal-zone support. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx91.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi index 4d8300b2a7bc..f075592bfc01 100644 --- a/arch/arm64/boot/dts/freescale/imx91.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -6,6 +6,54 @@ #include "imx91-pinfunc.h" #include "imx91_93_common.dtsi" +/{ + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&aips1 { + tmu: thermal-sensor@44482000 { + compatible = "fsl,imx91-tmu"; + reg = <0x44482000 0x1000>; + #thermal-sensor-cells = <0>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + interrupt-parent = <&gic>; + interrupts = , + , + ; + interrupt-names = "thr1", "thr2", "ready"; + nvmem-cells = <&tmu_trim1>, <&tmu_trim2>; + nvmem-cell-names = "trim1", "trim2"; + }; +}; + &clk { compatible = "fsl,imx91-ccm"; }; @@ -69,3 +117,13 @@ &media_blk_ctrl { clock-names = "apb", "axi", "nic", "disp", "cam", "lcdif", "isi", "csi"; }; + +&ocotp { + tmu_trim1: tmu-trim@a0 { + reg = <0xa0 0x4>; + }; + + tmu_trim2: tmu-trim@a4 { + reg = <0xa4 0x4>; + }; +}; From fc61fdfdc4dd03fa5cea784e1969ed3df049c6c8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 Nov 2025 15:31:30 +0100 Subject: [PATCH 082/104] arm64: dts: imx95: Use GPU_CGC as core clock for GPU The i.MX95 imx-sm introduced new GPU_CGC clock since imx-sm commit ca5e078833fa ("SM-128: Add clock management via CCM LPCG direct control") which are downstream clock of GPU clock. These new GPU_CGC clock gate the existing GPU clock. Currently, without clk_ignore_unused on kernel command line, those new GPU_CGC clock are unused and the kernel will disable them. This has no impact on i.MX95 A0/A1, but does prevent GPU register access from working at all on i.MX95 B0. The GPU_CGC clock are present on both i.MX95 A0/A1/B0, therefore update the DT such, that the GPU core clock are the GPU_CGC clock. When the panthor driver enables the GPU core clock, it enables both the GPU_CGC as well as its parent GPU clock. Fixes: 67934f248e64 ("arm64: dts: imx95: Describe Mali G310 GPU") Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-clock.h | 1 + arch/arm64/boot/dts/freescale/imx95.dtsi | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/dts/freescale/imx95-clock.h index e1f91203e794..22311612e440 100644 --- a/arch/arm64/boot/dts/freescale/imx95-clock.h +++ b/arch/arm64/boot/dts/freescale/imx95-clock.h @@ -183,5 +183,6 @@ #define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + 7) #define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8) #define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9) +#define IMX95_CLK_GPU_CGC (IMX95_CCM_NUM_CLK_SRC + 123 + 10) #endif /* __CLOCK_IMX95_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index e45014d50abe..93d53c3f9eab 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -2164,7 +2164,7 @@ netc_emdio: mdio@0,0 { gpu: gpu@4d900000 { compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; reg = <0 0x4d900000 0 0x480000>; - clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; + clocks = <&scmi_clk IMX95_CLK_GPU_CGC>, <&scmi_clk IMX95_CLK_GPUAPB>; clock-names = "core", "coregroup"; interrupts = , , From 6429d40e519fed71e2bd2afd59f9a379f9740a9b Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:38 +0100 Subject: [PATCH 083/104] arm64: dts: imx8mq-librem5: Enable I2C recovery i2c-imx can perform bus recovery by temporarily switching I2C pins into GPIO mode. To do so, it needs GPIO and pinctrl handles to be provided in the device tree. Suggested-by: Denis Sergeevich Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5.dtsi | 48 +++++++++++++++++-- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 2975e9451661..2bd25ef7f304 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -512,6 +512,13 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 >; }; + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x26 + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x26 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 @@ -519,6 +526,13 @@ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 >; }; + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x26 + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x26 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 @@ -526,6 +540,13 @@ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 >; }; + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x26 + MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x26 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 @@ -533,6 +554,13 @@ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 >; }; + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x26 + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x26 + >; + }; + pinctrl_keys: keysgrp { fsl,pins = < /* VOL- */ @@ -782,8 +810,11 @@ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f &i2c1 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; typec_pd: usb-pd@3f { @@ -982,8 +1013,11 @@ rtc@68 { &i2c2 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; magnetometer: magnetometer@1e { @@ -1031,8 +1065,11 @@ accel_gyro: accel-gyro@6a { &i2c3 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; codec: audio-codec@1a { @@ -1121,8 +1158,11 @@ touchscreen@38 { &i2c4 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; vcm@c { From bb01a42b1bc2ee4483a784ac6e8597d16227a04f Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:39 +0100 Subject: [PATCH 084/104] arm64: dts: imx8mq-librem5: Set vibrator's PWM frequency to 20kHz 1Hz as used previously was way too long. Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 2bd25ef7f304..bc3e103b2d6a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -287,7 +287,7 @@ bm818_codec: sound-wwan-codec { vibrator { compatible = "pwm-vibrator"; - pwms = <&pwm1 0 1000000000 0>; + pwms = <&pwm1 0 50000 0>; pwm-names = "enable"; vcc-supply = <®_vdd_3v3>; }; From 1361bfee8d7b791288e585a3467330a5f5b699ed Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:40 +0100 Subject: [PATCH 085/104] arm64: dts: imx8mq-librem5: Enable SNVS RTC It has been disabled because it was being used for system clock instead of the discrete RTC. However, SNVS has some features that the discrete RTC does not, such as being able to turn the device on. Solve that issue with aliases instead and reenable SNVS RTC. Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index bc3e103b2d6a..5e0bf127e7e5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -17,6 +17,11 @@ / { compatible = "purism,librem5", "fsl,imx8mq"; chassis-type = "handset"; + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + backlight_dsi: backlight-dsi { compatible = "led-backlight"; leds = <&led_backlight>; @@ -1001,7 +1006,7 @@ ldo7_reg: LDO7 { }; }; - rtc@68 { + rtc: rtc@68 { compatible = "microcrystal,rv4162"; reg = <0x68>; pinctrl-names = "default"; @@ -1316,10 +1321,6 @@ &snvs_pwrkey { status = "okay"; }; -&snvs_rtc { - status = "disabled"; -}; - &uart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; From f9774d6d4ba45cb345b17001861e5ecdf0b4c659 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:41 +0100 Subject: [PATCH 086/104] arm64: dts: imx8mq-librem5: Limit uSDHC2 frequency to 50MHz SparkLAN card has stability issues at 100MHz. It still appears to be able to max out its throughput this way, so limit the frequency to ensure stable operation. Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 5e0bf127e7e5..5bc9654cd436 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1424,7 +1424,7 @@ &usdhc1 { &usdhc2 { assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; + assigned-clock-rates = <50000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>; @@ -1434,7 +1434,7 @@ &usdhc2 { mmc-pwrseq = <&usdhc2_pwrseq>; post-power-on-delay-ms = <20>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cap-sdio-irq; keep-power-in-suspend; From f8d3da15a96975646eb17b270753fdf639c37a65 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:42 +0100 Subject: [PATCH 087/104] arm64: dts: imx8mq-librem5: Set cap-power-off-card for usdhc2 This is needed for brcmfmac to turn the card off in suspend since 8c3170628a9ce24a59647bd24f897e666af919b8. Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 5bc9654cd436..068799cbedb2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1437,6 +1437,7 @@ &usdhc2 { max-frequency = <50000000>; disable-wp; cap-sdio-irq; + cap-power-off-card; keep-power-in-suspend; wakeup-source; status = "okay"; From 507d920800ea52388d89756eb168482e18bf0681 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:43 +0100 Subject: [PATCH 088/104] arm64: dts: imx8mq-librem5: Don't set mic-cfg for wm8962 The default values are fine, and MICDET_ENA is handled by the driver on its own anyway. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 068799cbedb2..eee390c27210 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1085,7 +1085,6 @@ codec: audio-codec@1a { assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; #sound-dai-cells = <0>; - mic-cfg = <0x200>; DCVDD-supply = <®_aud_1v8>; DBVDD-supply = <®_aud_1v8>; AVDD-supply = <®_aud_1v8>; From 347e8b20acfeb2861e28892062b6dc3d9f579981 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Jan 2026 20:00:39 +0100 Subject: [PATCH 089/104] arm64: dts: imx8mn: Add SNVS LPGPR Add SNVS LPGPR bindings to MX8M Nano, the LPGPR is used to store boot counter. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b98b3d0ddf25..3199bc0966b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -628,6 +628,11 @@ snvs_pwrkey: snvs-powerkey { wakeup-source; status = "disabled"; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx8mn-snvs-lpgpr", + "fsl,imx7d-snvs-lpgpr"; + }; }; clk: clock-controller@30380000 { From 5eb7405db99b171494f9aa3d37e2985ae74ee37f Mon Sep 17 00:00:00 2001 From: Fedor Ross Date: Tue, 6 Jan 2026 20:00:40 +0100 Subject: [PATCH 090/104] arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2 Add support for ifm i.MX8MN VHIP4 EvalBoard v1 and v2 reference design. This system exists in two generations, v1 and v2, which share a lot of commonality. The boards come with either single gigabit ethernet or an KSZ8794 fast-ethernet switch, boot from eMMC, and offer CAN interfaces via Microchip MCP25xx SPI CAN controllers, UART, and USB host. The GPU is not available in the SoC populated on these devices. Signed-off-by: Fedor Ross Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 19 + .../imx8mn-vhip4-evalboard-common.dtsi | 396 ++++++++++++++++++ ...imx8mn-vhip4-evalboard-ksz8794-common.dtsi | 98 +++++ ...mn-vhip4-evalboard-v1-overlay-ksz8794.dtso | 24 ++ ...mn-vhip4-evalboard-v1-overlay-ksz9031.dtso | 48 +++ .../freescale/imx8mn-vhip4-evalboard-v1.dts | 258 ++++++++++++ ...n-vhip4-evalboard-v2-overlay-adin1300.dtso | 60 +++ ...mn-vhip4-evalboard-v2-overlay-ksz8794.dtso | 24 ++ .../freescale/imx8mn-vhip4-evalboard-v2.dts | 221 ++++++++++ 9 files changed, 1148 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ce8f937c2315..83df038701de 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -193,6 +193,25 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb +imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo +imx8mn-vhip4-evalboard-v1-overlay-ksz9031-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtbo +imx8mn-vhip4-evalboard-v2-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo +imx8mn-vhip4-evalboard-v2-overlay-adin1300-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtbo \ + imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtbo \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo + imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-usbotg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi new file mode 100644 index 000000000000..aaf9761703aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2024 Fedor Ross + */ + +#include "imx8mn.dtsi" +#include + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board"; + compatible = "ifm,imx8mn-vhip4-evalboard", "ifm,imx8mn-vhip4", "fsl,imx8mn"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + mmc2 = &usdhc2; + rtc0 = &hw_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200 rootwait"; + stdout-path = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x40000000>; + }; + + can_clk20m: can-clk20m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + can_clk40m: can-clk40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio_button>; + pinctrl-names = "default"; + + button-2 { + label = "Button2"; + gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-3 { + label = "Button3"; + gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + ifm_led: led { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_gpio_led>; + pinctrl-names = "default", "extended"; + + led-0 { + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + color = ; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + color = ; + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_cs>; + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_ecspi3_cs>; + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&gpu { + /* SoC has GPU fused off. */ + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + hw_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + + ifm_pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <790000>; + regulator-max-microvolt = <860000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <840000>; + regulator-max-microvolt = <960000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x110 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x110 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x190 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + /* SPI3_CAN_CLK */ + MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x110 + /* SPI3_CAN_MOSI */ + MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x110 + /* SPI3_CAN_MISO */ + MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x190 + >; + }; + + pinctrl_gpio_button: gpiobutton-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x96 + MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x96 + >; + }; + + pinctrl_gpio_led: gpioled-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x116 + MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x116 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000110 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000114 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000116 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&pgc_gpumix { + /* SoC has GPU fused off. */ + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi new file mode 100644 index 000000000000..c1a98ec2f438 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Fedor Ross + */ + +#include + +#include "imx8mn-pinfunc.h" + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ksz8794: ethernet-switch@1 { + compatible = "microchip,ksz8794"; + pinctrl-names = "default", "reset"; + pinctrl-0 = <&pinctrl_ks8794>; + pinctrl-1 = <&pinctrl_ks8794>; + reg = <1>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + spi-max-frequency = <5000000>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + fixed-link { + full-duplex; + speed = <1000>; + }; + }; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + full-duplex; + speed = <1000>; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; + + pinctrl_ks8794: ks8794-grp { + fsl,pins = < + /* KSZ8794 reset line */ + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso new file mode 100644 index 000000000000..20eb427f3dd6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include + +#include "imx8mn-pinfunc.h" + +&pinctrl_ecspi1 { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x10 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x10 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x90 + /* KS8794 nCS */ + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; +}; + +#include "imx8mn-vhip4-evalboard-ksz8794-common.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso new file mode 100644 index 000000000000..de24206106b3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mn-pinfunc.h" + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts new file mode 100644 index 000000000000..5f37065bf43f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2024 Fedor Ross + */ + +/dts-v1/; + +#include "imx8mn-vhip4-evalboard-common.dtsi" + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board v1"; + compatible = "ifm,imx8mn-vhip4-evalboard-v1", "ifm,imx8mn-vhip4-evalboard", + "ifm,imx8mn-vhip4", "fsl,imx8mn"; +}; + +&ifm_led { + pinctrl-1 = <&pinctrl_gpio_led_v1>; + + led-2 { + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + color = ; + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + color = ; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 21 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32c81w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <32768>; + address-width = <16>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp25625"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp25625>; + reg = <0>; + clocks = <&can_clk20m>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + }; + + can1: can@1 { + compatible = "microchip,mcp2518fd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp2518>; + reg = <1>; + clocks = <&can_clk40m>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + spi-max-frequency = <20000000>; + }; +}; + +&i2c1 { + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ifm_pmic { + interrupt-parent = <&gpio2>; + interrupts = <0 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + /* KS8794 nCS */ + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; + }; + + pinctrl_ecspi3_cs: ecspi3-cs-grp { + fsl,pins = < + /* MCP25625 nCS */ + MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x150 + /* MCP2518FD nCS */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x150 + >; + }; + + pinctrl_gpio_5: gpio5-grp { + fsl,pins = < + /* CFG_EEPROM_WP */ + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x140 + >; + }; + + pinctrl_gpio_led_v1: gpioled-v1-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x116 + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x116 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000056 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000d6 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x56 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0xd6 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000056 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000d6 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x56 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0xd6 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x40000056 + MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x400000d6 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x56 + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0xd6 + >; + }; + + pinctrl_mcp2518: mcp2518-grp { + fsl,pins = < + /* MCP2518 nINT line */ + MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x116 + /* MCP2518 nINT1/GPIO1 line */ + MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x116 + >; + }; + + pinctrl_mcp25625: mcp25625-grp { + fsl,pins = < + /* MCP25625 nINT line */ + MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x156 + >; + }; + + pinctrl_pmic: pmic-irq-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x16 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x142 + MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x142 + >; + }; + + pinctrl_usb_nreset: usbnreset-grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x14a + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_5>; + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", + "ifm_device_info_eeprom_wp", + "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_nreset>; + #address-cells = <1>; + #size-cells = <0>; + + usb-hub@1 { + compatible = "usb424,2512", "usb424,2514"; + reg = <1>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso new file mode 100644 index 000000000000..6ad7434a1787 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Fedor Ross + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mn-pinfunc.h" + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + + adi,rx-internal-delay-ps = <1800>; + adi,tx-internal-delay-ps = <2200>; + interrupts-extended = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + /* nRST */ + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x156 + /* nIRQ */ + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso new file mode 100644 index 000000000000..ab1304ebd965 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include + +#include "imx8mn-pinfunc.h" + +&pinctrl_ecspi1 { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x10 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x10 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x90 + /* KS8794 nCS */ + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; +}; + +#include "imx8mn-vhip4-evalboard-ksz8794-common.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts new file mode 100644 index 000000000000..4dadfb7f78de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Fedor Ross + */ + +/dts-v1/; + +#include "imx8mn-vhip4-evalboard-common.dtsi" + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board v2"; + compatible = "ifm,imx8mn-vhip4-evalboard-v2", "ifm,imx8mn-vhip4-evalboard", + "ifm,imx8mn-vhip4", "fsl,imx8mn"; + + multi-led { + compatible = "leds-group-multicolor"; + color = ; + function = LED_FUNCTION_INDICATOR; + leds = <&rgb_0>, <&rgb_1>, <&rgb_2>; + }; +}; + +&ifm_led { + pinctrl-1 = <&pinctrl_gpio_led_v2>; + + rgb_0: rgb-led-red { + color = ; + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rgb_1: rgb-led-green { + color = ; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rgb_2: rgb-led-blue { + color = ; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio1 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeprom@0 { + compatible = "fujitsu,mb85rs64", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <32768>; + address-width = <16>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2518fd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp2518>; + reg = <0>; + clocks = <&can_clk40m>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + spi-max-frequency = <20000000>; + }; +}; + +&i2c1 { + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c3 { + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ifm_pmic { + interrupt-parent = <&gpio5>; + interrupts = <17 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + /* KS8794 nCS */ + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x150 + /* Retain memory nCS (FRAM or MRAM) */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + /* RETAIN_nHOLD */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x140 + >; + }; + + pinctrl_ecspi3_cs: ecspi3-cs-grp { + fsl,pins = < + /* MCP2518FD nCS */ + MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x150 + >; + }; + + pinctrl_gpio_led_v2: gpioled-v2-grp { + fsl,pins = < + /* LED_RGB_RED */ + MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x116 + /* LED_RGB_GREEN */ + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x116 + /* LED_RGB_BLUE */ + MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x116 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x40000056 + MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x400000d6 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x56 + MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0xd6 + /* CFG_EEPROM_WP */ + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 + /* RTC_nIRQ */ + MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x116 + /* LOG_EE_WP */ + MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x140 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000056 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000d6 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x56 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0xd6 + >; + }; + + pinctrl_mcp2518: mcp2518-grp { + fsl,pins = < + /* CAN0_CLKO */ + MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x116 + /* CAN0_nINT0 */ + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x116 + /* CAN0_nINT1 */ + MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x116 + /* CAN0_nINT */ + MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x116 + >; + }; + + pinctrl_pmic: pmic-irq-grp { + fsl,pins = < + /* PMIC_nIRQ */ + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1d6 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x142 + MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x142 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", + "ifm_device_info_eeprom_wp", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", + "ifm_logging_eeprom_wp", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; From 730f6b28cb877fdc75bb13bd4d82c270e3bcd3cd Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:07 +0800 Subject: [PATCH 091/104] arm64: dts: imx952: Add idle-states node Add idle-states node and refer it in A55 nodes to enable cpuidle. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi index 33bde271d394..91fe4916ac04 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR MIT) /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ #include @@ -50,12 +50,27 @@ cpus { #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + A55_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX952_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -73,6 +88,7 @@ A55_1: cpu@100 { reg = <0x100>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX952_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -90,6 +106,7 @@ A55_2: cpu@200 { reg = <0x200>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX952_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -107,6 +124,7 @@ A55_3: cpu@300 { reg = <0x300>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX952_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; From 570a0eb963274c6f5457e4ee24a18c0baa47058a Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Sun, 11 Jan 2026 20:40:08 +0800 Subject: [PATCH 092/104] arm64: dts: imx952-evk: Change the usdhc1_200mhz drive strength to DSE4 Set usdhc1_200mhz drive strength need to use DSE4, according to validation team's suggestion, Signed-off-by: Haibo Chen Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 2c753fcbae3c..e5d989bd7c7b 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -159,17 +159,17 @@ IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x15fe - IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x13fe - IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x13fe - IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x13fe - IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x13fe - IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x13fe - IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x13fe - IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x13fe - IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x13fe - IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x13fe - IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x15fe + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e >; }; From b7f274333167c9ba3343780d2621f7fa90904657 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:09 +0800 Subject: [PATCH 093/104] arm64: dts: imx952-evk: Enable I2C[2,3,4,6,7] bus Enable I2C bus[2,3,4,6,7] and the io-expanders connected to each I2C bus. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 166 +++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index e5d989bd7c7b..98f2f96a91cc 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -17,6 +17,14 @@ aliases { gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; @@ -79,6 +87,111 @@ reg_usdhc2_vmmc: regulator-usdhc2 { }; }; +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + adp5585: io-expander@34 { + compatible = "adi,adp5585-00", "adi,adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + gpio-reserved-ranges = <5 1>; + #pwm-cells = <3>; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + i2c3_pcal6408: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_3p3v>; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c4>; + status = "okay"; + + i2c4_pcal6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_pcal6408>; + vcc-supply = <®_3p3v>; + }; +}; + +&lpi2c6 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c6>; + status = "okay"; + + pcal6416: gpio@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416>; + vcc-supply = <®_3p3v>; + + pdm-can-sel-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-low; + }; + + mqs-en-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + +&lpi2c7 { + clock-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &lpuart1 { /* console */ pinctrl-names = "default"; @@ -112,6 +225,59 @@ &usdhc2 { }; &scmi_iomuxc { + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x40000b9e + IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e + IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_i2c4_pcal6408: i2c4pcal6408grp { + fsl,pins = < + IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x31e + >; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = < + IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e + IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x40000b9e + IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6416: pcal6416grp { + fsl,pins = < + IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e From fc910b85b27147accce831da2e52a56f17987c3c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:10 +0800 Subject: [PATCH 094/104] arm64: dts: imx952-evk: Enable UART5 Enable UART5 for using Bluetooth. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 98f2f96a91cc..dcc339b766a2 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -28,6 +28,7 @@ aliases { mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; + serial4 = &lpuart5; }; chosen { @@ -199,6 +200,17 @@ &lpuart1 { status = "okay"; }; +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -291,6 +303,15 @@ IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e + IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e + IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e + IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e From ba1d167451875caddb11502fcc26015bbb31d728 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:11 +0800 Subject: [PATCH 095/104] arm64: dts: imx952-evk: Enable SPI7 Enable SPI7 for i.MX952-EVK. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index dcc339b766a2..447aea3cfd07 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -29,6 +29,7 @@ aliases { mmc1 = &usdhc2; serial0 = &lpuart1; serial4 = &lpuart5; + spi6 = &lpspi7; }; chosen { @@ -211,6 +212,13 @@ bluetooth { }; }; +&lpspi7 { + cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi7>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -278,6 +286,15 @@ IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e >; }; + pinctrl_lpspi7: lpspi7grp { + fsl,pins = < + IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x39e + IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x39e + IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x39e + IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x39e + >; + }; + pinctrl_pcal6416: pcal6416grp { fsl,pins = < IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e From 8e135b9d57f844da78db760bf22b68a151a0e710 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:12 +0800 Subject: [PATCH 096/104] arm64: dts: imx952-evk: Enable USB[1,2] Enable USB[1,2] and add ptn5110 connected to USB1. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 76 ++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 447aea3cfd07..0b6b28c24e46 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx952.dtsi" / { @@ -87,6 +88,16 @@ reg_usdhc2_vmmc: regulator-usdhc2 { enable-active-high; off-on-delay-us = <12000>; }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; &lpi2c2 { @@ -192,6 +203,40 @@ pcal6524: gpio@22 { interrupt-parent = <&gpio5>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5110>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; }; &lpuart1 { @@ -219,6 +264,31 @@ &lpspi7 { status = "okay"; }; +&usb1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usb2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -307,6 +377,12 @@ IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e >; }; + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e From 1f563af57f255b26d4b788f9219ba17a748ccbe3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:13 +0800 Subject: [PATCH 097/104] arm64: dts: imx952-evk: Enable wdog3 Enable wdog3 to allow System manager reset Linux. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 0b6b28c24e46..24a3468b1817 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -314,6 +314,11 @@ &usdhc2 { status = "okay"; }; +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + &scmi_iomuxc { pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < From 13b56cf38fcaf6320d84392c6b6ec783d6def5a1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:14 +0800 Subject: [PATCH 098/104] arm64: dts: imx952-evk: Enable TPM[3,6] Enable TPM[3,6] for PWM. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 34 +++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 24a3468b1817..21b951a21564 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -1,10 +1,11 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ /dts-v1/; +#include #include #include "imx952.dtsi" @@ -42,6 +43,13 @@ memory@80000000 { reg = <0x0 0x80000000 0 0x80000000>; }; + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; + cooling-levels = <64 128 192 255>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -264,6 +272,18 @@ &lpspi7 { status = "okay"; }; +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm3>; + status = "okay"; +}; + +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; + status = "okay"; +}; + &usb1 { dr_mode = "otg"; hnp-disable; @@ -394,6 +414,18 @@ IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e >; }; + pinctrl_tpm3: tpm3grp { + fsl,pins = < + IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x51e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e From aef607803edda92d2fc853a2e5f3dba6d147d598 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Sun, 11 Jan 2026 20:40:15 +0800 Subject: [PATCH 099/104] arm64: dts: imx952-evk: Add flexcan support Add flexcan support, since flexcan1 share pins with PDM, default disable flexcan1. Signed-off-by: Haibo Chen Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 45 ++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 21b951a21564..bae7b88f8229 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -64,6 +64,22 @@ linux_cma: linux,cma { }; }; + flexcan1_phy: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + max-bitrate = <8000000>; + enable-gpios = <&pcal6416 6 GPIO_ACTIVE_HIGH>; + standby-gpios = <&pcal6416 5 GPIO_ACTIVE_LOW>; + }; + + flexcan2_phy: can-phy1 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + max-bitrate = <8000000>; + enable-gpios = <&i2c4_pcal6408 4 GPIO_ACTIVE_HIGH>; + standby-gpios = <&i2c4_pcal6408 3 GPIO_ACTIVE_LOW>; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; @@ -108,6 +124,21 @@ reg_usb_vbus: regulator-vbus { }; +/* pin conflict with PDM */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + phys = <&flexcan1_phy>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + phys = <&flexcan2_phy>; + status = "okay"; +}; + &lpi2c2 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -340,6 +371,20 @@ &wdog3 { }; &scmi_iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e + IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e + >; + }; + pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e From 2da6336e94c223ee5b8535faf8138f0c8b8f1275 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:16 +0800 Subject: [PATCH 100/104] arm64: dts: imx952-evk: Add nxp,ctrl-ids for scmi misc Add nxp,ctrl-ids in scmi_misc node for wakeup notification. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index bae7b88f8229..b838323468d4 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -9,6 +9,15 @@ #include #include "imx952.dtsi" +#define FALLING_EDGE BIT(0) +#define RISING_EDGE BIT(1) + +#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_M2E_WAKE 0x8001U /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002U /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */ + / { model = "NXP i.MX952 EVK board"; compatible = "fsl,imx952-evk", "fsl,imx952"; @@ -303,6 +312,14 @@ &lpspi7 { status = "okay"; }; +&scmi_misc { + nxp,ctrl-ids = ; +}; + &tpm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm3>; From 8c898869809ddb3347a7cddcb3a8ceee42b38488 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Tue, 13 Jan 2026 09:50:02 +0200 Subject: [PATCH 101/104] arm64: dts: imx93-11x11-frdm: Add MQS audio support Enable Medium Quality Sound (MQS) output on the i.MX93 FRDM 11x11 board by adding sound card description and enabling sai1 and mqs1 dts nodes, together with necessary clocks and pinmux. This supports audio playback via SAI1 DAI which is connected to the MQS1 block. Co-developed-by: Tom Zheng Signed-off-by: Tom Zheng Signed-off-by: Daniel Baluta Tested-by: Francesco Valla Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-frdm.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts index 066c5139842b..5bb6ae0d154a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts @@ -81,6 +81,13 @@ vdevbuffer: vdevbuffer@a4020000 { no-map; }; }; + + sound-mqs { + compatible = "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs1>; + }; }; &adc1 { @@ -315,6 +322,27 @@ &lpuart1 { /* console */ status = "okay"; }; +&mqs1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs1>; + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { adp-disable; disable-over-current; @@ -479,6 +507,13 @@ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e >; }; + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; + pinctrl_pcal6524: pcal6524grp { fsl,pins = < MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e From 1a7d97c2d3868c7c7b74b26d4af210e22666171b Mon Sep 17 00:00:00 2001 From: Francesco Valla Date: Thu, 15 Jan 2026 18:11:34 +0100 Subject: [PATCH 102/104] arm64: dts: imx93-11x11-frdm: enable additional devices Enable additional devices on the i.MX93 FRDM board: - CAN port and associated transceiver - Bluetooth portion of the IW612 chipset - WiFi SDIO port - user buttons The WiFi portion of the on-board IW612 chipset is still not supported upstream, but since SDIO is a discoverable bus it will be probed once it is. Signed-off-by: Francesco Valla Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-frdm.dts | 152 ++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts index 5bb6ae0d154a..bd14ba28690c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts @@ -9,6 +9,7 @@ / { model = "NXP i.MX93 11X11 FRDM board"; aliases { + can0 = &flexcan2; ethernet0 = &fec; ethernet1 = &eqos; i2c0 = &lpi2c1; @@ -18,12 +19,40 @@ aliases { mmc1 = &usdhc2; /* uSD */ rtc0 = &pcf2131; serial0 = &lpuart1; + serial4 = &lpuart5; }; chosen { stdout-path = &lpuart1; }; + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-k2 { + label = "Button K2"; + linux,code = ; + gpios = <&pcal6524 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + }; + + button-k3 { + label = "Button K3"; + linux,code = ; + gpios = <&pcal6524 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + interrupt-parent = <&pcal6524>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + }; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; off-on-delay-us = <12000>; @@ -37,6 +66,16 @@ reg_usdhc2_vmmc: regulator-usdhc2 { enable-active-high; }; + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "VPCIe_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reserved-memory { ranges; #address-cells = <2>; @@ -88,6 +127,11 @@ sound-mqs { audio-cpu = <&sai1>; audio-codec = <&mqs1>; }; + + usdhc3_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; }; &adc1 { @@ -157,11 +201,27 @@ ethphy2: ethernet-phy@2 { }; }; +&flexcan2 { + phys = <&flexcan2_phy>; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + &lpi2c1 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c1>; pinctrl-names = "default"; status = "okay"; + + pcal6408: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; }; &lpi2c2 { @@ -322,6 +382,21 @@ &lpuart1 { /* console */ status = "okay"; }; +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + uart-has-rtscts; + + bluetooth { + compatible = "nxp,88w8987-bt"; + device-wakeup-gpios = <&pcal6408 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pcal6524 19 GPIO_ACTIVE_LOW>; + vcc-supply = <®_usdhc3_vmmc>; + }; +}; + &mqs1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mqs1>; @@ -394,6 +469,20 @@ &usdhc2 { status = "okay"; }; +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + status = "okay"; +}; + &wdog3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -486,6 +575,13 @@ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e >; }; + pinctrl_flexcan2_sleep: flexcan2sleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e + MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + pinctrl_lpi2c1: lpi2c1grp { fsl,pins = < MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e @@ -533,6 +629,15 @@ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < @@ -647,6 +752,53 @@ MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e From 868f5c154c25b7b2fba29c5c07f3b22a7ec8d49e Mon Sep 17 00:00:00 2001 From: Francesco Valla Date: Thu, 15 Jan 2026 18:41:10 +0100 Subject: [PATCH 103/104] arm64: dts: imx91-11x11-frdm: fix CAN transceiver gpio According to the HW schematic, the CAN transceiver does not have an enable pin but a silent one. Fix the GPIO property name and polarity. Fixes: b4bf5e55899e ("arm64: dts: freescale: Add FRDM-IMX91 basic support") Signed-off-by: Francesco Valla Acked-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts index 0d1acf8a55a5..c25561574d3f 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts @@ -39,7 +39,7 @@ flexcan_phy: can-phy { compatible = "nxp,tja1051"; #phy-cells = <0>; max-bitrate = <5000000>; - enable-gpios = <&pcal6524 23 GPIO_ACTIVE_LOW>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; }; gpio-keys { From 9bdfeed989b126a3c9c5a6f74ad2d96784b69d27 Mon Sep 17 00:00:00 2001 From: Lei Xu Date: Fri, 16 Jan 2026 00:56:14 -0800 Subject: [PATCH 104/104] arm64: dts: freescale: imx95: Add support for i.MX95 15x15 FRDM board The i.MX95 15x15 FRDM board is a compact and cost-effective development platform based on the i.MX95 applications processor. Add device tree support for this board, including: - LPUART1 and LPUART5 - NETC - USB - PCIe - uSDHC1, uSDHC2 and uSDHC3 - FlexCAN2 and FlexCAN5 - LPI2C2, LPI2C3, LPI2C4 and their child nodes - Watchdog3 Reviewed-by: Laurentiu Mihalcea Signed-off-by: Lei Xu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx95-15x15-frdm.dts | 964 ++++++++++++++++++ 2 files changed, 965 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 83df038701de..700bab4d3e60 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -441,6 +441,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts new file mode 100644 index 000000000000..ca1c4966c867 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "imx95.dtsi" + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */ + +/ { + compatible = "fsl,imx95-15x15-frdm", "fsl,imx95"; + model = "NXP i.MX95 15X15 FRDM board"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + stdout-path = &lpuart1; + }; + + dmic: dmic { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <2>; + }; + + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + /* + * Shared SILENT GPIO: CAN PHYs enter silent mode + * together (hardware design). + */ + silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; + }; + + flexcan5_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "+V5.0_SW"; + }; + + reg_ext_3v3: regulator-ext-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCCEXT_3V3"; + }; + + reg_ext_5v: regulator-ext-5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VCCEXT_5V"; + gpio = <&pcal6524 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_ekey_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power-ekey"; + gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_mkey_pwr: regulator-m2-mkey-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-mkey-power"; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_SD2_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_ekey_pwr>; + gpio = <&pcal6524 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_VBUS"; + gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: memory@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: memory@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: memory@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vpu_boot: memory@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + + codec { + sound-dai = <&dmic>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + phys = <&flexcan2_phy>; + status = "okay"; +}; + +&flexcan5 { + pinctrl-0 = <&pinctrl_flexcan5>; + pinctrl-names = "default"; + phys = <&flexcan5_phy>; + status = "okay"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + gpio-line-names = "ENET1 PHY reset", + "ENET2 PHY reset", + "SPI3/GPIO select", + "UART3/GPIO select", + "CAN2&5/GPIO select", + "PWM/GPIO select", + "Watch dog enable", + "CAN1&2&5 silent", + "SDIO_nRST", + "WL_nDISABLE1", + "WL_nDISABLE2", + "M.2 Mkey NC06", + "EXT_5V0_PWR_EN", + "EXT_3V3_PWR_EN", + "Mkey power control", + "USB2 power control", + "Ekey power control", + "MIPI-DSICSI reset", + "MIPI-DSI IO2", + "MIPI-CSI reset", + "LVDS TP reset", + "LVDS BL enable", + "LVDS BL power enable", + "IT6263 reset"; + + lpspi-gpio-sel-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + }; + + lpuart-gpio-sel-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-low; + }; + + can-gpio-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + }; + + pwm-gpio-sel-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ptn5110>; + pinctrl-names = "default"; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-names = "default"; + status = "okay"; + + pca9632: led-controller@62 { + compatible = "nxp,pca9632"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + nxp,inverted-out; + + led_backlight0: led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <0>; + }; + + led_backlight1: led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <1>; + }; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +/* Configure MSI and IOMMU mappings specific to the i.MX95 15x15 FRDM board. */ +&netc_bus0 { + msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map = <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x50 &smmu 0x25 0x1>, + <0x60 &smmu 0x26 0x1>, + <0x80 &smmu 0x24 0x1>, + <0xc0 &smmu 0x27 0x1>; +}; + +&netc_emdio { + pinctrl-0 = <&pinctrl_emdio>; + pinctrl-names = "default"; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 0 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 1 GPIO_ACTIVE_LOW>; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; + supports-clkreq; + vpcie-supply = <®_m2_mkey_pwr>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e + IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e + >; + }; + + pinctrl_flexcan5: flexcan5grp { + fsl,pins = < + IMX95_PAD_GPIO_IO22__CAN5_TX 0x39e + IMX95_PAD_GPIO_IO23__CAN5_RX 0x39e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids = ; +}; + +&thermal_zones { + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&usb2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +};