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dt-bindings: display: mediatek: Add OF graph support for board path

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The display IPs in MediaTek SoCs support being interconnected with
different instances of DDP IPs (for example, merge0 or merge1) and/or
with different DDP IPs (for example, rdma can be connected with either
color, dpi, dsi, merge, etc), forming a full Display Data Path that
ends with an actual display.

The final display pipeline is effectively board specific, as it does
depend on the display that is attached to it, and eventually on the
sensors supported by the board (for example, Adaptive Ambient Light
would need an Ambient Light Sensor, otherwise it's pointless!), other
than the output type.

Add support for OF graphs to most of the MediaTek DDP (display) bindings
to add flexibility to build custom hardware paths, hence enabling board
specific configuration of the display pipeline and allowing to finally
migrate away from using hardcoded paths.

Please note that - while this commit retains retro-compatibility with
old device trees - it will break the ABI for mediatek,dsi and for
mediatek,dpi for the sake of consistency between the `ports` in all
MediaTek DRM drivers versus DRM bridge drivers as in the previous
binding, MediaTek was using `port` (implicitly, port@0) as an OUTPUT,
while now the first port is an INPUT, and the second one is an OUTPUT,
which is consistent with other DRM drivers which can be chained to
drm/mediatek.

As for maintainability concerns, I am aware that the old device tree
will not be actively tested anymore, but retrocompatibility breakages
will *not* be more likely to happen in the future because any addition
to the graph (new drivers) will be done only for features present on
newer SoCs, keeping the old ones (and their default pipeline) untouched.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: Michael Walle <mwalle@kernel.org> # on kontron-sbc-i1200
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20241017103809.156056-2-angelogioacchino.delregno@collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno 2024-10-17 12:38:07 +02:00 committed by Chun-Kuang Hu
parent 9852d85ec9
commit 2b6433f30b
16 changed files with 372 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
View File

@ -62,6 +62,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: AAL input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
AAL output to the next component's input, for example could be one
of many gamma, overdrive or other blocks.
required:
- port@0
- port@1
required:
- compatible
- reg
@ -89,5 +110,24 @@ examples:
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_AAL>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
aal0_in: endpoint {
remote-endpoint = <&ccorr0_out>;
};
};
port@1 {
reg = <1>;
aal0_out: endpoint {
remote-endpoint = <&gamma0_in>;
};
};
};
};
};

21
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
View File

@ -57,6 +57,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: CCORR input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
CCORR output to the input of the next desired component in the
display pipeline, usually only one of the available AAL blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
View File

@ -65,6 +65,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: COLOR input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
COLOR output to the input of the next desired component in the
display pipeline, for example one of the available CCORR or AAL
blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
View File

@ -56,6 +56,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DITHER input, usually from a POSTMASK or GAMMA block.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
DITHER output to the input of the next desired component in the
display pipeline, for example one of the available DSC compressors,
DP_INTF, DSI, LVDS or others.
required:
- port@0
- port@1
required:
- compatible
- reg

25
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
View File

@ -71,13 +71,34 @@ properties:
Output port node. This port should be connected to the input port of an
attached HDMI, LVDS or DisplayPort encoder chip.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPI input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DPI output to an HDMI, LVDS or DisplayPort encoder input
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- port
oneOf:
- required:
- port
- required:
- ports
allOf:
- if:
@ -100,7 +121,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
dpi0: dpi@1401d000 {
dpi: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

24
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
View File

@ -49,6 +49,30 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Display Stream Compression input, usually from one of the DITHER
or MERGE blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Display Stream Compression output to the input of the next desired
component in the display pipeline, for example to MERGE, DP_INTF,
DPI or DSI.
required:
- port@0
- port@1
required:
- compatible
- reg

27
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
View File

@ -77,6 +77,26 @@ properties:
Output port node. This port should be connected to the input
port of an attached DSI panel or DSI-to-eDP encoder chip.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input ports can have multiple endpoints, each of those connects
to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DSI input port, usually from DITHER, DSC or MERGE
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
DSI output to an attached DSI panel, or a DSI-to-X encoder chip
required:
- port@0
- port@1
required:
- compatible
- reg
@ -86,7 +106,12 @@ required:
- clock-names
- phys
- phy-names
- port
oneOf:
- required:
- port
- required:
- ports
unevaluatedProperties: false

22
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
View File

@ -110,6 +110,28 @@ properties:
include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
function block.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: ETHDR input, usually from one of the MERGE blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
ETHDR output to the input of the next desired component in the
display pipeline, for example one of the available MERGE blocks,
or others.
required:
- port@0
- port@1
required:
- compatible
- reg

19
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
View File

@ -65,6 +65,25 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: GAMMA input, usually from one of the AAL blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
GAMMA output to the input of the next desired component in the
display pipeline, for example one of the available DITHER or
POSTMASK blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

23
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
View File

@ -77,6 +77,29 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
MERGE input port, usually from DITHER, DPI, DSC, DSI, MDP_RDMA,
ETHDR or even from a different MERGE block
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
MERGE output to a DSC, DPI, DP_INTF, DSI, ETHDR, Write DMA, or
a different MERGE block, or others.
required:
- port@0
- port@1
resets:
description: reset controller
See Documentation/devicetree/bindings/reset/reset.txt for details.

22
Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
View File

@ -38,6 +38,28 @@ properties:
items:
- description: OD Clock
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: OD input port, usually from an AAL block
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
OD output to the input of the next desired component in the
display pipeline, for example one of the available RDMA or
other blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
View File

@ -57,6 +57,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: OVL input port from MMSYS, VDOSYS or other OVLs
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
OVL output to the input of the next desired component in the
display pipeline, for example one of the available COLOR, RDMA
or WDMA blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
View File

@ -75,6 +75,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: OVL input port from MMSYS or one of multiple VDOSYS
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
OVL output to the input of the next desired component in the
display pipeline, for example one of the available COLOR, RDMA
or WDMA blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

21
Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
View File

@ -52,6 +52,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: POSTMASK input port, usually from GAMMA
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
POSTMASK output to the input of the next desired component in the
display pipeline, for example one of the available DITHER blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

22
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
View File

@ -87,6 +87,28 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: RDMA input port, usually from MMSYS, OD or OVL
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
RDMA output to the input of the next desired component in the
display pipeline, for example one of the available COLOR, DPI,
DSI, MERGE or UFOE blocks.
required:
- port@0
- port@1
required:
- compatible
- reg

21
Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
View File

@ -43,6 +43,27 @@ properties:
items:
- description: UFOe Clock
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Input and output ports can have multiple endpoints, each of those
connects to either the primary, secondary, etc, display pipeline.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: UFOE input, usually from one of the RDMA blocks.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
UFOE output to the input of the next desired component in the
display pipeline, usually one of the available DSI blocks.
required:
- port@0
- port@1
required:
- compatible
- reg