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arm64: dts: imx8mp-frdm: Use symbolic macros for IOMUXC_SW_PAD_CTL_PAD

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Currently, in order to configure IOMUXC_SW_PAD_CTL_PAD a magic raw value
is written in this register. This makes code not obvious to read and
modify.

Use symbolic macros instead of the magic values to improve code
readability.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Daniel Baluta 2026-03-02 15:38:05 +02:00 committed by Frank Li
parent 95f56afadb
commit 2b5b97cd39
1 changed files with 84 additions and 48 deletions
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132
arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
View File

@ -252,104 +252,140 @@ &usdhc3 {
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>;
};
pinctrl_pcal6416_0_int: pcal6416-0-int-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16
(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_pcal6416_1_int: pcal6416-1-int-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11
(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
(MX8MP_FSEL_FAST | MX8MP_PULL_UP |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>;
};
};