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drm/i915/dpll: Move away from using shared dpll
Rename functions to move away from using shared dpll in the dpll framework as much as possible since dpll may not always be shared. --v2 -Use intel_dpll_global instead of global_dpll [Jani] --v3 -Just use intel_dpll [Jani] --v4 -Drop the global from comments [Jani] Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250515071801.2221120-8-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal
parent
386a183259
commit
2b3b9a8faf
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@ -1569,7 +1569,7 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
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id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
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return intel_get_shared_dpll_by_id(display, id);
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return intel_get_dpll_by_id(display, id);
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}
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static void adls_ddi_enable_clock(struct intel_encoder *encoder,
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@ -1723,7 +1723,7 @@ static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
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if (phy >= PHY_C)
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id += DPLL_ID_DG1_DPLL2;
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return intel_get_shared_dpll_by_id(display, id);
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return intel_get_dpll_by_id(display, id);
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}
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static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
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@ -1895,7 +1895,7 @@ static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
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return NULL;
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}
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return intel_get_shared_dpll_by_id(display, id);
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return intel_get_dpll_by_id(display, id);
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}
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static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
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@ -1918,7 +1918,7 @@ static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
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return NULL;
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}
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return intel_get_shared_dpll_by_id(display, id);
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return intel_get_dpll_by_id(display, id);
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}
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static void skl_ddi_enable_clock(struct intel_encoder *encoder,
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@ -1986,7 +1986,7 @@ static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
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id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
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DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
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return intel_get_shared_dpll_by_id(display, id);
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return intel_get_dpll_by_id(display, id);
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}
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void hsw_ddi_enable_clock(struct intel_encoder *encoder,
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@ -2053,7 +2053,7 @@ static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
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return NULL;
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}
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return intel_get_shared_dpll_by_id(display, id);
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return intel_get_dpll_by_id(display, id);
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}
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void intel_ddi_enable_clock(struct intel_encoder *encoder,
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@ -2760,7 +2760,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
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* 4. Enable the port PLL.
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*
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* The PLL enabling itself was already done before this function by
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* hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
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* hsw_crtc_enable()->intel_enable_dpll(). We need only
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* configure the PLL to port mapping here.
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*/
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intel_ddi_enable_clock(encoder, crtc_state);
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@ -1664,7 +1664,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
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intel_encoders_pre_pll_enable(state, crtc);
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if (new_crtc_state->intel_dpll)
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intel_enable_shared_dpll(new_crtc_state);
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intel_enable_dpll(new_crtc_state);
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intel_encoders_pre_enable(state, crtc);
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@ -1793,7 +1793,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
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intel_encoders_disable(state, crtc);
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intel_encoders_post_disable(state, crtc);
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intel_disable_shared_dpll(old_crtc_state);
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intel_disable_dpll(old_crtc_state);
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intel_encoders_post_pll_disable(state, crtc);
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@ -6436,7 +6436,7 @@ int intel_atomic_check(struct drm_device *dev,
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any_ms = true;
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intel_release_shared_dplls(state, crtc);
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intel_release_dplls(state, crtc);
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}
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if (any_ms && !check_digital_port_conflicts(state)) {
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@ -7533,7 +7533,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state)
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intel_atomic_swap_global_state(state);
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intel_shared_dpll_swap_state(state);
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intel_dpll_swap_state(state);
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intel_atomic_track_fbs(state);
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@ -446,7 +446,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
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}
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intel_plane_possible_crtcs_init(display);
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intel_shared_dpll_init(display);
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intel_dpll_init(display);
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intel_fdi_pll_freq_update(display);
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intel_update_czclk(display);
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@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
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intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
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return 0;
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ret = intel_compute_shared_dplls(state, crtc, encoder);
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ret = intel_compute_dplls(state, crtc, encoder);
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if (ret)
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return ret;
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@ -1190,7 +1190,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
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intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
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return 0;
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return intel_reserve_shared_dplls(state, crtc, encoder);
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return intel_reserve_dplls(state, crtc, encoder);
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}
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static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
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@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
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if (ret)
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return ret;
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/* TODO: Do the readback via intel_compute_shared_dplls() */
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/* TODO: Do the readback via intel_compute_dplls() */
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crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
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crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
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@ -1395,7 +1395,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
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ilk_compute_dpll(crtc_state, &crtc_state->dpll,
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&crtc_state->dpll);
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ret = intel_compute_shared_dplls(state, crtc, NULL);
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ret = intel_compute_dplls(state, crtc, NULL);
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if (ret)
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return ret;
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@ -1415,7 +1415,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
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if (!crtc_state->has_pch_encoder)
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return 0;
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return intel_reserve_shared_dplls(state, crtc, NULL);
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return intel_reserve_dplls(state, crtc, NULL);
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}
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static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
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@ -52,21 +52,21 @@
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* share a PLL if their configurations match.
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*
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* This file provides an abstraction over display PLLs. The function
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* intel_shared_dpll_init() initializes the PLLs for the given platform. The
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* intel_dpll_init() initializes the PLLs for the given platform. The
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* users of a PLL are tracked and that tracking is integrated with the atomic
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* modset interface. During an atomic operation, required PLLs can be reserved
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* for a given CRTC and encoder configuration by calling
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* intel_reserve_shared_dplls() and previously reserved PLLs can be released
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* with intel_release_shared_dplls().
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* intel_reserve_dplls() and previously reserved PLLs can be released
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* with intel_release_dplls().
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* Changes to the users are first staged in the atomic state, and then made
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* effective by calling intel_shared_dpll_swap_state() during the atomic
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* effective by calling intel_dpll_swap_state() during the atomic
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* commit phase.
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*/
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/* platform specific hooks for managing DPLLs */
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struct intel_dpll_funcs {
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/*
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* Hook for enabling the pll, called from intel_enable_shared_dpll() if
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* Hook for enabling the pll, called from intel_enable_dpll() if
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* the pll is not already enabled.
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*/
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void (*enable)(struct intel_display *display,
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@ -74,7 +74,7 @@ struct intel_dpll_funcs {
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const struct intel_dpll_hw_state *dpll_hw_state);
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/*
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* Hook for disabling the pll, called from intel_disable_shared_dpll()
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* Hook for disabling the pll, called from intel_disable_dpll()
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* only when it is safe to disable the pll, i.e., there are no more
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* tracked users for it.
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*/
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@ -133,7 +133,7 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
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}
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static struct intel_dpll_state *
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intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
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intel_atomic_get_dpll_state(struct drm_atomic_state *s)
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{
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struct intel_atomic_state *state = to_intel_atomic_state(s);
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struct intel_display *display = to_intel_display(state);
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@ -151,7 +151,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
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}
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/**
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* intel_get_shared_dpll_by_id - get a DPLL given its id
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* intel_get_dpll_by_id - get a DPLL given its id
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* @display: intel_display device instance
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* @id: pll id
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*
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@ -159,8 +159,8 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
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* A pointer to the DPLL with @id
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*/
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struct intel_dpll *
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intel_get_shared_dpll_by_id(struct intel_display *display,
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enum intel_dpll_id id)
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intel_get_dpll_by_id(struct intel_display *display,
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enum intel_dpll_id id)
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{
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struct intel_dpll *pll;
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int i;
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@ -175,9 +175,9 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
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}
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/* For ILK+ */
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void assert_shared_dpll(struct intel_display *display,
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struct intel_dpll *pll,
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bool state)
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void assert_dpll(struct intel_display *display,
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struct intel_dpll *pll,
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bool state)
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{
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bool cur_state;
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struct intel_dpll_hw_state hw_state;
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@ -250,12 +250,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
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}
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/**
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* intel_enable_shared_dpll - enable a CRTC's shared DPLL
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* @crtc_state: CRTC, and its state, which has a shared DPLL
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* intel_enable_dpll - enable a CRTC's DPLL
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* @crtc_state: CRTC, and its state, which has a DPLL
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*
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* Enable the shared DPLL used by @crtc.
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* Enable DPLL used by @crtc.
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*/
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void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
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void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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@ -282,7 +282,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
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if (old_mask) {
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drm_WARN_ON(display->drm, !pll->on);
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assert_shared_dpll_enabled(display, pll);
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assert_dpll_enabled(display, pll);
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goto out;
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}
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drm_WARN_ON(display->drm, pll->on);
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@ -296,12 +296,12 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
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}
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/**
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* intel_disable_shared_dpll - disable a CRTC's shared DPLL
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* intel_disable_dpll - disable a CRTC's shared DPLL
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* @crtc_state: CRTC, and its state, which has a shared DPLL
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*
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* Disable the shared DPLL used by @crtc.
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* Disable DPLL used by @crtc.
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*/
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void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
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void intel_disable_dpll(const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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@ -326,7 +326,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
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pll->info->name, pll->active_mask, pll->on,
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crtc->base.base.id, crtc->base.name);
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assert_shared_dpll_enabled(display, pll);
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assert_dpll_enabled(display, pll);
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drm_WARN_ON(display->drm, !pll->on);
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pll->active_mask &= ~pipe_mask;
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@ -358,10 +358,10 @@ intel_dpll_mask_all(struct intel_display *display)
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}
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static struct intel_dpll *
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intel_find_shared_dpll(struct intel_atomic_state *state,
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const struct intel_crtc *crtc,
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const struct intel_dpll_hw_state *dpll_hw_state,
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unsigned long dpll_mask)
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intel_find_dpll(struct intel_atomic_state *state,
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const struct intel_crtc *crtc,
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const struct intel_dpll_hw_state *dpll_hw_state,
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unsigned long dpll_mask)
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{
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struct intel_display *display = to_intel_display(crtc);
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unsigned long dpll_mask_all = intel_dpll_mask_all(display);
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@ -369,14 +369,14 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
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struct intel_dpll *unused_pll = NULL;
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enum intel_dpll_id id;
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dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
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dpll_state = intel_atomic_get_dpll_state(&state->base);
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drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
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for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
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struct intel_dpll *pll;
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pll = intel_get_shared_dpll_by_id(display, id);
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pll = intel_get_dpll_by_id(display, id);
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if (!pll)
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continue;
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@ -412,7 +412,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
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}
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/**
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* intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
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* intel_reference_dpll_crtc - Get a DPLL reference for a CRTC
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* @crtc: CRTC on which behalf the reference is taken
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* @pll: DPLL for which the reference is taken
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* @dpll_state: the DPLL atomic state in which the reference is tracked
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@ -420,9 +420,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
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* Take a reference for @pll tracking the use of it by @crtc.
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*/
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static void
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intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
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const struct intel_dpll *pll,
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struct intel_dpll_state *dpll_state)
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intel_reference_dpll_crtc(const struct intel_crtc *crtc,
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const struct intel_dpll *pll,
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struct intel_dpll_state *dpll_state)
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{
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struct intel_display *display = to_intel_display(crtc);
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@ -435,23 +435,23 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
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}
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static void
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intel_reference_shared_dpll(struct intel_atomic_state *state,
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const struct intel_crtc *crtc,
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const struct intel_dpll *pll,
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const struct intel_dpll_hw_state *dpll_hw_state)
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intel_reference_dpll(struct intel_atomic_state *state,
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const struct intel_crtc *crtc,
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const struct intel_dpll *pll,
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const struct intel_dpll_hw_state *dpll_hw_state)
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{
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struct intel_dpll_state *dpll_state;
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dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
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dpll_state = intel_atomic_get_dpll_state(&state->base);
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if (dpll_state[pll->index].pipe_mask == 0)
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dpll_state[pll->index].hw_state = *dpll_hw_state;
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intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
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intel_reference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
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}
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/**
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* intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
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* intel_unreference_dpll_crtc - Drop a DPLL reference for a CRTC
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* @crtc: CRTC on which behalf the reference is dropped
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* @pll: DPLL for which the reference is dropped
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* @dpll_state: the DPLL atomic state in which the reference is tracked
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@ -459,9 +459,9 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
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* Drop a reference for @pll tracking the end of use of it by @crtc.
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*/
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void
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intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
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const struct intel_dpll *pll,
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struct intel_dpll_state *dpll_state)
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intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
|
||||
const struct intel_dpll *pll,
|
||||
struct intel_dpll_state *dpll_state)
|
||||
{
|
||||
struct intel_display *display = to_intel_display(crtc);
|
||||
|
||||
|
|
@ -473,15 +473,15 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
|
|||
crtc->base.base.id, crtc->base.name, pll->info->name);
|
||||
}
|
||||
|
||||
static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
|
||||
const struct intel_crtc *crtc,
|
||||
const struct intel_dpll *pll)
|
||||
static void intel_unreference_dpll(struct intel_atomic_state *state,
|
||||
const struct intel_crtc *crtc,
|
||||
const struct intel_dpll *pll)
|
||||
{
|
||||
struct intel_dpll_state *dpll_state;
|
||||
|
||||
dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
|
||||
dpll_state = intel_atomic_get_dpll_state(&state->base);
|
||||
|
||||
intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
|
||||
intel_unreference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
|
||||
}
|
||||
|
||||
static void intel_put_dpll(struct intel_atomic_state *state,
|
||||
|
|
@ -497,11 +497,11 @@ static void intel_put_dpll(struct intel_atomic_state *state,
|
|||
if (!old_crtc_state->intel_dpll)
|
||||
return;
|
||||
|
||||
intel_unreference_shared_dpll(state, crtc, old_crtc_state->intel_dpll);
|
||||
intel_unreference_dpll(state, crtc, old_crtc_state->intel_dpll);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_shared_dpll_swap_state - make atomic DPLL configuration effective
|
||||
* intel_dpll_swap_state - make atomic DPLL configuration effective
|
||||
* @state: atomic state
|
||||
*
|
||||
* This is the dpll version of drm_atomic_helper_swap_state() since the
|
||||
|
|
@ -511,7 +511,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
|
|||
* i.e. it also puts the current state into @state, even though there is no
|
||||
* need for that at this moment.
|
||||
*/
|
||||
void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
|
||||
void intel_dpll_swap_state(struct intel_atomic_state *state)
|
||||
{
|
||||
struct intel_display *display = to_intel_display(state);
|
||||
struct intel_dpll_state *dpll_state = state->dpll_state;
|
||||
|
|
@ -620,25 +620,25 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
|
|||
if (HAS_PCH_IBX(display)) {
|
||||
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
|
||||
id = (enum intel_dpll_id) crtc->pipe;
|
||||
pll = intel_get_shared_dpll_by_id(display, id);
|
||||
pll = intel_get_dpll_by_id(display, id);
|
||||
|
||||
drm_dbg_kms(display->drm,
|
||||
"[CRTC:%d:%s] using pre-allocated %s\n",
|
||||
crtc->base.base.id, crtc->base.name,
|
||||
pll->info->name);
|
||||
} else {
|
||||
pll = intel_find_shared_dpll(state, crtc,
|
||||
&crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_PCH_PLL_B) |
|
||||
BIT(DPLL_ID_PCH_PLL_A));
|
||||
pll = intel_find_dpll(state, crtc,
|
||||
&crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_PCH_PLL_B) |
|
||||
BIT(DPLL_ID_PCH_PLL_A));
|
||||
}
|
||||
|
||||
if (!pll)
|
||||
return -EINVAL;
|
||||
|
||||
/* reference the pll */
|
||||
intel_reference_shared_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
intel_reference_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
|
||||
crtc_state->intel_dpll = pll;
|
||||
|
||||
|
|
@ -1066,7 +1066,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
|
|||
struct intel_crtc_state *crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
|
||||
return intel_find_shared_dpll(state, crtc,
|
||||
return intel_find_dpll(state, crtc,
|
||||
&crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_WRPLL2) |
|
||||
BIT(DPLL_ID_WRPLL1));
|
||||
|
|
@ -1113,7 +1113,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
pll = intel_get_shared_dpll_by_id(display, pll_id);
|
||||
pll = intel_get_dpll_by_id(display, pll_id);
|
||||
|
||||
if (!pll)
|
||||
return NULL;
|
||||
|
|
@ -1169,7 +1169,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
|
|||
struct intel_crtc_state *crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
|
||||
return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
|
||||
return intel_find_dpll(state, crtc, &crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_SPLL));
|
||||
}
|
||||
|
||||
|
|
@ -1233,8 +1233,8 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
|
|||
if (!pll)
|
||||
return -EINVAL;
|
||||
|
||||
intel_reference_shared_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
intel_reference_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
|
||||
crtc_state->intel_dpll = pll;
|
||||
|
||||
|
|
@ -1942,20 +1942,20 @@ static int skl_get_dpll(struct intel_atomic_state *state,
|
|||
struct intel_dpll *pll;
|
||||
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
|
||||
pll = intel_find_shared_dpll(state, crtc,
|
||||
&crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_SKL_DPLL0));
|
||||
pll = intel_find_dpll(state, crtc,
|
||||
&crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_SKL_DPLL0));
|
||||
else
|
||||
pll = intel_find_shared_dpll(state, crtc,
|
||||
&crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_SKL_DPLL3) |
|
||||
BIT(DPLL_ID_SKL_DPLL2) |
|
||||
BIT(DPLL_ID_SKL_DPLL1));
|
||||
pll = intel_find_dpll(state, crtc,
|
||||
&crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_SKL_DPLL3) |
|
||||
BIT(DPLL_ID_SKL_DPLL2) |
|
||||
BIT(DPLL_ID_SKL_DPLL1));
|
||||
if (!pll)
|
||||
return -EINVAL;
|
||||
|
||||
intel_reference_shared_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
intel_reference_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
|
||||
crtc_state->intel_dpll = pll;
|
||||
|
||||
|
|
@ -2434,13 +2434,13 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
|
|||
|
||||
/* 1:1 mapping between ports and PLLs */
|
||||
id = (enum intel_dpll_id) encoder->port;
|
||||
pll = intel_get_shared_dpll_by_id(display, id);
|
||||
pll = intel_get_dpll_by_id(display, id);
|
||||
|
||||
drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
|
||||
crtc->base.base.id, crtc->base.name, pll->info->name);
|
||||
|
||||
intel_reference_shared_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
intel_reference_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
|
||||
crtc_state->intel_dpll = pll;
|
||||
|
||||
|
|
@ -3388,14 +3388,14 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
|
|||
/* Eliminate DPLLs from consideration if reserved by HTI */
|
||||
dpll_mask &= ~intel_hti_dpll_mask(display);
|
||||
|
||||
port_dpll->pll = intel_find_shared_dpll(state, crtc,
|
||||
&port_dpll->hw_state,
|
||||
dpll_mask);
|
||||
port_dpll->pll = intel_find_dpll(state, crtc,
|
||||
&port_dpll->hw_state,
|
||||
dpll_mask);
|
||||
if (!port_dpll->pll)
|
||||
return -EINVAL;
|
||||
|
||||
intel_reference_shared_dpll(state, crtc,
|
||||
port_dpll->pll, &port_dpll->hw_state);
|
||||
intel_reference_dpll(state, crtc,
|
||||
port_dpll->pll, &port_dpll->hw_state);
|
||||
|
||||
icl_update_active_dpll(state, crtc, encoder);
|
||||
|
||||
|
|
@ -3452,26 +3452,25 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
|
|||
int ret;
|
||||
|
||||
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
|
||||
port_dpll->pll = intel_find_shared_dpll(state, crtc,
|
||||
&port_dpll->hw_state,
|
||||
BIT(DPLL_ID_ICL_TBTPLL));
|
||||
port_dpll->pll = intel_find_dpll(state, crtc,
|
||||
&port_dpll->hw_state,
|
||||
BIT(DPLL_ID_ICL_TBTPLL));
|
||||
if (!port_dpll->pll)
|
||||
return -EINVAL;
|
||||
intel_reference_shared_dpll(state, crtc,
|
||||
port_dpll->pll, &port_dpll->hw_state);
|
||||
|
||||
intel_reference_dpll(state, crtc,
|
||||
port_dpll->pll, &port_dpll->hw_state);
|
||||
|
||||
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
|
||||
dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
|
||||
port_dpll->pll = intel_find_shared_dpll(state, crtc,
|
||||
&port_dpll->hw_state,
|
||||
BIT(dpll_id));
|
||||
port_dpll->pll = intel_find_dpll(state, crtc,
|
||||
&port_dpll->hw_state,
|
||||
BIT(dpll_id));
|
||||
if (!port_dpll->pll) {
|
||||
ret = -EINVAL;
|
||||
goto err_unreference_tbt_pll;
|
||||
}
|
||||
intel_reference_shared_dpll(state, crtc,
|
||||
port_dpll->pll, &port_dpll->hw_state);
|
||||
intel_reference_dpll(state, crtc,
|
||||
port_dpll->pll, &port_dpll->hw_state);
|
||||
|
||||
icl_update_active_dpll(state, crtc, encoder);
|
||||
|
||||
|
|
@ -3479,7 +3478,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
|
|||
|
||||
err_unreference_tbt_pll:
|
||||
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
|
||||
intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
|
||||
intel_unreference_dpll(state, crtc, port_dpll->pll);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -3534,7 +3533,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
|
|||
if (!old_port_dpll->pll)
|
||||
continue;
|
||||
|
||||
intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
|
||||
intel_unreference_dpll(state, crtc, old_port_dpll->pll);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4300,12 +4299,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
|
|||
};
|
||||
|
||||
/**
|
||||
* intel_shared_dpll_init - Initialize shared DPLLs
|
||||
* intel_dpll_init - Initialize DPLLs
|
||||
* @display: intel_display device
|
||||
*
|
||||
* Initialize shared DPLLs for @display.
|
||||
* Initialize DPLLs for @display.
|
||||
*/
|
||||
void intel_shared_dpll_init(struct intel_display *display)
|
||||
void intel_dpll_init(struct intel_display *display)
|
||||
{
|
||||
const struct intel_dpll_mgr *dpll_mgr = NULL;
|
||||
const struct dpll_info *dpll_info;
|
||||
|
|
@ -4362,7 +4361,7 @@ void intel_shared_dpll_init(struct intel_display *display)
|
|||
}
|
||||
|
||||
/**
|
||||
* intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
|
||||
* intel_compute_dplls - compute DPLL state CRTC and encoder combination
|
||||
* @state: atomic state
|
||||
* @crtc: CRTC to compute DPLLs for
|
||||
* @encoder: encoder
|
||||
|
|
@ -4370,14 +4369,14 @@ void intel_shared_dpll_init(struct intel_display *display)
|
|||
* This function computes the DPLL state for the given CRTC and encoder.
|
||||
*
|
||||
* The new configuration in the atomic commit @state is made effective by
|
||||
* calling intel_shared_dpll_swap_state().
|
||||
* calling intel_dpll_swap_state().
|
||||
*
|
||||
* Returns:
|
||||
* 0 on success, negative error code on failure.
|
||||
*/
|
||||
int intel_compute_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder)
|
||||
int intel_compute_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct intel_display *display = to_intel_display(state);
|
||||
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
|
||||
|
|
@ -4389,7 +4388,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
|
|||
}
|
||||
|
||||
/**
|
||||
* intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
|
||||
* intel_reserve_dplls - reserve DPLLs for CRTC and encoder combination
|
||||
* @state: atomic state
|
||||
* @crtc: CRTC to reserve DPLLs for
|
||||
* @encoder: encoder
|
||||
|
|
@ -4399,18 +4398,18 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
|
|||
* state.
|
||||
*
|
||||
* The new configuration in the atomic commit @state is made effective by
|
||||
* calling intel_shared_dpll_swap_state().
|
||||
* calling intel_dpll_swap_state().
|
||||
*
|
||||
* The reserved DPLLs should be released by calling
|
||||
* intel_release_shared_dplls().
|
||||
* intel_release_dplls().
|
||||
*
|
||||
* Returns:
|
||||
* 0 if all required DPLLs were successfully reserved,
|
||||
* negative error code otherwise.
|
||||
*/
|
||||
int intel_reserve_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder)
|
||||
int intel_reserve_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct intel_display *display = to_intel_display(state);
|
||||
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
|
||||
|
|
@ -4422,18 +4421,18 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
|
|||
}
|
||||
|
||||
/**
|
||||
* intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
|
||||
* intel_release_dplls - end use of DPLLs by CRTC in atomic state
|
||||
* @state: atomic state
|
||||
* @crtc: crtc from which the DPLLs are to be released
|
||||
*
|
||||
* This function releases all DPLLs reserved by intel_reserve_shared_dplls()
|
||||
* This function releases all DPLLs reserved by intel_reserve_dplls()
|
||||
* from the current atomic commit @state and the old @crtc atomic state.
|
||||
*
|
||||
* The new configuration in the atomic commit @state is made effective by
|
||||
* calling intel_shared_dpll_swap_state().
|
||||
* calling intel_dpll_swap_state().
|
||||
*/
|
||||
void intel_release_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
void intel_release_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct intel_display *display = to_intel_display(state);
|
||||
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
|
||||
|
|
@ -4441,7 +4440,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
|
|||
/*
|
||||
* FIXME: this function is called for every platform having a
|
||||
* compute_clock hook, even though the platform doesn't yet support
|
||||
* the shared DPLL framework and intel_reserve_shared_dplls() is not
|
||||
* the DPLL framework and intel_reserve_dplls() is not
|
||||
* called on those.
|
||||
*/
|
||||
if (!dpll_mgr)
|
||||
|
|
@ -4457,7 +4456,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
|
|||
* @encoder: encoder determining the type of port DPLL
|
||||
*
|
||||
* Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
|
||||
* from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
|
||||
* from the port DPLLs reserved previously by intel_reserve_dplls(). The
|
||||
* DPLL selected will be based on the current mode of the encoder's port.
|
||||
*/
|
||||
void intel_update_active_dpll(struct intel_atomic_state *state,
|
||||
|
|
@ -4522,7 +4521,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
|
|||
to_intel_crtc_state(crtc->base.state);
|
||||
|
||||
if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
|
||||
intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
|
||||
intel_reference_dpll_crtc(crtc, pll, &pll->state);
|
||||
}
|
||||
pll->active_mask = pll->state.pipe_mask;
|
||||
|
||||
|
|
@ -4683,8 +4682,8 @@ static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
|
|||
(old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
|
||||
}
|
||||
|
||||
void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
void intel_dpll_state_verify(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct intel_display *display = to_intel_display(state);
|
||||
const struct intel_crtc_state *old_crtc_state =
|
||||
|
|
@ -4714,7 +4713,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
|
|||
}
|
||||
}
|
||||
|
||||
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
|
||||
void intel_dpll_verify_disabled(struct intel_atomic_state *state)
|
||||
{
|
||||
struct intel_display *display = to_intel_display(state);
|
||||
struct intel_dpll *pll;
|
||||
|
|
|
|||
|
|
@ -387,26 +387,26 @@ struct intel_dpll {
|
|||
#define SKL_DPLL2 2
|
||||
#define SKL_DPLL3 3
|
||||
|
||||
/* shared dpll functions */
|
||||
/* dpll functions */
|
||||
struct intel_dpll *
|
||||
intel_get_shared_dpll_by_id(struct intel_display *display,
|
||||
enum intel_dpll_id id);
|
||||
void assert_shared_dpll(struct intel_display *display,
|
||||
struct intel_dpll *pll,
|
||||
bool state);
|
||||
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
|
||||
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
|
||||
int intel_compute_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder);
|
||||
int intel_reserve_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder);
|
||||
void intel_release_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
|
||||
const struct intel_dpll *pll,
|
||||
struct intel_dpll_state *shared_dpll_state);
|
||||
intel_get_dpll_by_id(struct intel_display *display,
|
||||
enum intel_dpll_id id);
|
||||
void assert_dpll(struct intel_display *display,
|
||||
struct intel_dpll *pll,
|
||||
bool state);
|
||||
#define assert_dpll_enabled(d, p) assert_dpll(d, p, true)
|
||||
#define assert_dpll_disabled(d, p) assert_dpll(d, p, false)
|
||||
int intel_compute_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder);
|
||||
int intel_reserve_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder);
|
||||
void intel_release_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
|
||||
const struct intel_dpll *pll,
|
||||
struct intel_dpll_state *shared_dpll_state);
|
||||
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
|
||||
enum icl_port_dpll_id port_dpll_id);
|
||||
void intel_update_active_dpll(struct intel_atomic_state *state,
|
||||
|
|
@ -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display *display,
|
|||
bool intel_dpll_get_hw_state(struct intel_display *display,
|
||||
struct intel_dpll *pll,
|
||||
struct intel_dpll_hw_state *dpll_hw_state);
|
||||
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
|
||||
void intel_shared_dpll_init(struct intel_display *display);
|
||||
void intel_enable_dpll(const struct intel_crtc_state *crtc_state);
|
||||
void intel_disable_dpll(const struct intel_crtc_state *crtc_state);
|
||||
void intel_dpll_swap_state(struct intel_atomic_state *state);
|
||||
void intel_dpll_init(struct intel_display *display);
|
||||
void intel_dpll_update_ref_clks(struct intel_display *display);
|
||||
void intel_dpll_readout_hw_state(struct intel_display *display);
|
||||
void intel_dpll_sanitize_state(struct intel_display *display);
|
||||
|
|
@ -435,8 +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
|
|||
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
|
||||
bool intel_dpll_is_combophy(enum intel_dpll_id id);
|
||||
|
||||
void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
|
||||
void intel_dpll_state_verify(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void intel_dpll_verify_disabled(struct intel_atomic_state *state);
|
||||
|
||||
#endif /* _INTEL_DPLL_MGR_H_ */
|
||||
|
|
|
|||
|
|
@ -249,7 +249,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
|
|||
|
||||
if (HAS_PCH_SPLIT(display)) {
|
||||
assert_fdi_rx_pll_disabled(display, pipe);
|
||||
assert_shared_dpll_disabled(display, crtc_state->intel_dpll);
|
||||
assert_dpll_disabled(display, crtc_state->intel_dpll);
|
||||
} else {
|
||||
assert_pll_disabled(display, pipe);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -93,9 +93,9 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
|
|||
crtc->base.enabled = false;
|
||||
|
||||
if (crtc_state->intel_dpll)
|
||||
intel_unreference_shared_dpll_crtc(crtc,
|
||||
crtc_state->intel_dpll,
|
||||
&crtc_state->intel_dpll->state);
|
||||
intel_unreference_dpll_crtc(crtc,
|
||||
crtc_state->intel_dpll,
|
||||
&crtc_state->intel_dpll->state);
|
||||
}
|
||||
|
||||
static void set_encoder_for_connector(struct intel_connector *connector,
|
||||
|
|
|
|||
|
|
@ -243,7 +243,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
|
|||
intel_wm_state_verify(state, crtc);
|
||||
verify_connector_state(state, crtc);
|
||||
verify_crtc_state(state, crtc);
|
||||
intel_shared_dpll_state_verify(state, crtc);
|
||||
intel_dpll_state_verify(state, crtc);
|
||||
intel_mpllb_state_verify(state, crtc);
|
||||
intel_cx0pll_state_verify(state, crtc);
|
||||
}
|
||||
|
|
@ -252,5 +252,5 @@ void intel_modeset_verify_disabled(struct intel_atomic_state *state)
|
|||
{
|
||||
verify_encoder_state(state);
|
||||
verify_connector_state(state, NULL);
|
||||
intel_shared_dpll_verify_disabled(state);
|
||||
intel_dpll_verify_disabled(state);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -251,7 +251,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
|
|||
u32 val, pipeconf_val;
|
||||
|
||||
/* Make sure PCH DPLL is enabled */
|
||||
assert_shared_dpll_enabled(display, crtc_state->intel_dpll);
|
||||
assert_dpll_enabled(display, crtc_state->intel_dpll);
|
||||
|
||||
/* FDI must be feeding us bits for PCH ports */
|
||||
assert_fdi_tx_enabled(display, pipe);
|
||||
|
|
@ -382,7 +382,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
|
|||
temp |= TRANS_DPLL_ENABLE(pipe);
|
||||
sel = TRANS_DPLLB_SEL(pipe);
|
||||
if (crtc_state->intel_dpll ==
|
||||
intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
|
||||
intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
|
||||
temp |= sel;
|
||||
else
|
||||
temp &= ~sel;
|
||||
|
|
@ -394,11 +394,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
|
|||
* transcoder, and we actually should do this to not upset any PCH
|
||||
* transcoder that already use the clock when we share it.
|
||||
*
|
||||
* Note that enable_shared_dpll tries to do the right thing, but
|
||||
* get_shared_dpll unconditionally resets the pll - we need that
|
||||
* Note that enable_dpll tries to do the right thing, but
|
||||
* get_dpll unconditionally resets the pll - we need that
|
||||
* to have the right LVDS enable sequence.
|
||||
*/
|
||||
intel_enable_shared_dpll(crtc_state);
|
||||
intel_enable_dpll(crtc_state);
|
||||
|
||||
/* set transcoder timing, panel must allow it */
|
||||
assert_pps_unlocked(display, pipe);
|
||||
|
|
@ -472,7 +472,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
|
|||
|
||||
ilk_fdi_pll_disable(crtc);
|
||||
|
||||
intel_disable_shared_dpll(old_crtc_state);
|
||||
intel_disable_dpll(old_crtc_state);
|
||||
}
|
||||
|
||||
static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
|
||||
|
|
@ -528,7 +528,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
|
|||
pll_id = DPLL_ID_PCH_PLL_A;
|
||||
}
|
||||
|
||||
crtc_state->intel_dpll = intel_get_shared_dpll_by_id(display, pll_id);
|
||||
crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);
|
||||
pll = crtc_state->intel_dpll;
|
||||
|
||||
pll_active = intel_dpll_get_hw_state(display, pll,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user