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drm/amdgpu: remove operations related to legacy address
Remove operations related to legacy address conversion Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Ce Sun <cesun102@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ce Sun
Alex Deucher
parent
3b1f4d5e47
commit
2b3877b00a
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@ -2882,77 +2882,6 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
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return 0;
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}
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static int amdgpu_ras_mca2pa_by_idx(struct amdgpu_device *adev,
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struct eeprom_table_record *bps,
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struct ras_err_data *err_data)
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{
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struct ta_ras_query_address_input addr_in;
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uint32_t socket = 0;
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int ret = 0;
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if (adev->smuio.funcs && adev->smuio.funcs->get_socket_id)
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socket = adev->smuio.funcs->get_socket_id(adev);
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/* reinit err_data */
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err_data->err_addr_cnt = 0;
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err_data->err_addr_len = adev->umc.retire_unit;
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memset(&addr_in, 0, sizeof(addr_in));
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addr_in.ma.err_addr = bps->address;
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addr_in.ma.socket_id = socket;
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addr_in.ma.ch_inst = bps->mem_channel;
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if (!amdgpu_ras_smu_eeprom_supported(adev)) {
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/* tell RAS TA the node instance is not used */
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addr_in.ma.node_inst = TA_RAS_INV_NODE;
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} else {
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addr_in.ma.umc_inst = bps->mcumc_id;
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addr_in.ma.node_inst = bps->cu;
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}
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if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr)
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ret = adev->umc.ras->convert_ras_err_addr(adev, err_data,
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&addr_in, NULL, false);
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return ret;
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}
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static int amdgpu_ras_mca2pa(struct amdgpu_device *adev,
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struct eeprom_table_record *bps,
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struct ras_err_data *err_data)
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{
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struct ta_ras_query_address_input addr_in;
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uint32_t die_id, socket = 0;
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if (adev->smuio.funcs && adev->smuio.funcs->get_socket_id)
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socket = adev->smuio.funcs->get_socket_id(adev);
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/* although die id is gotten from PA in nps1 mode, the id is
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* fitable for any nps mode
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*/
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if (adev->umc.ras && adev->umc.ras->get_die_id_from_pa)
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die_id = adev->umc.ras->get_die_id_from_pa(adev, bps->address,
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bps->retired_page << AMDGPU_GPU_PAGE_SHIFT);
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else
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return -EINVAL;
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/* reinit err_data */
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err_data->err_addr_cnt = 0;
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err_data->err_addr_len = adev->umc.retire_unit;
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memset(&addr_in, 0, sizeof(addr_in));
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addr_in.ma.err_addr = bps->address;
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addr_in.ma.ch_inst = bps->mem_channel;
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addr_in.ma.umc_inst = bps->mcumc_id;
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addr_in.ma.node_inst = die_id;
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addr_in.ma.socket_id = socket;
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if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr)
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return adev->umc.ras->convert_ras_err_addr(adev, err_data,
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&addr_in, NULL, false);
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else
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return -EINVAL;
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}
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static bool __check_record_in_range(struct amdgpu_device *adev,
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struct eeprom_table_record *bps, int count)
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{
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@ -3013,117 +2942,13 @@ static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev,
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struct eeprom_table_record *bps, struct ras_err_data *err_data,
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enum amdgpu_memory_partition nps)
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{
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int i = 0;
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uint64_t chan_idx_v2;
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enum amdgpu_memory_partition save_nps;
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save_nps = (bps[0].retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK;
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chan_idx_v2 = bps[0].retired_page & UMC_CHANNEL_IDX_V2;
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/*old asics just have pa in eeprom*/
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if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) {
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memcpy(err_data->err_addr, bps,
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sizeof(struct eeprom_table_record) * adev->umc.retire_unit);
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goto out;
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}
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memcpy(err_data->err_addr, bps,
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sizeof(struct eeprom_table_record) * adev->umc.retire_unit);
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for (i = 0; i < adev->umc.retire_unit; i++)
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bps[i].retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT);
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if (save_nps || chan_idx_v2) {
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if (save_nps == nps) {
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if (amdgpu_umc_pages_in_a_row(adev, err_data,
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bps[0].retired_page << AMDGPU_GPU_PAGE_SHIFT))
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return -EINVAL;
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for (i = 0; i < adev->umc.retire_unit; i++) {
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err_data->err_addr[i].address = bps[0].address;
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err_data->err_addr[i].mem_channel = bps[0].mem_channel;
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err_data->err_addr[i].bank = bps[0].bank;
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err_data->err_addr[i].err_type = bps[0].err_type;
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err_data->err_addr[i].mcumc_id = bps[0].mcumc_id;
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}
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} else {
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if (amdgpu_ras_mca2pa_by_idx(adev, &bps[0], err_data))
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return -EINVAL;
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}
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} else {
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if (bps[0].address == 0) {
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/* for specific old eeprom data, mca address is not stored,
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* calc it from pa
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*/
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if (amdgpu_umc_pa2mca(adev, bps[0].retired_page << AMDGPU_GPU_PAGE_SHIFT,
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&(bps[0].address), AMDGPU_NPS1_PARTITION_MODE))
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return -EINVAL;
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}
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if (amdgpu_ras_mca2pa(adev, &bps[0], err_data)) {
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if (nps == AMDGPU_NPS1_PARTITION_MODE)
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memcpy(err_data->err_addr, bps,
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sizeof(struct eeprom_table_record) * adev->umc.retire_unit);
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else
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return -EOPNOTSUPP;
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}
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}
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out:
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return __amdgpu_ras_restore_bad_pages(adev, err_data->err_addr, adev->umc.retire_unit);
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}
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static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev,
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struct eeprom_table_record *bps, struct ras_err_data *err_data,
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enum amdgpu_memory_partition nps)
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{
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int i = 0;
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uint64_t chan_idx_v2;
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enum amdgpu_memory_partition save_nps;
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if (!amdgpu_ras_smu_eeprom_supported(adev)) {
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save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK;
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chan_idx_v2 = bps->retired_page & UMC_CHANNEL_IDX_V2;
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bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT);
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} else {
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/* if pmfw manages eeprom, save_nps is not stored on eeprom,
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* we should always convert mca address into physical address,
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* make save_nps different from nps
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*/
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save_nps = nps + 1;
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}
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if (save_nps == nps) {
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if (amdgpu_umc_pages_in_a_row(adev, err_data,
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bps->retired_page << AMDGPU_GPU_PAGE_SHIFT))
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return -EINVAL;
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for (i = 0; i < adev->umc.retire_unit; i++) {
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err_data->err_addr[i].address = bps->address;
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err_data->err_addr[i].mem_channel = bps->mem_channel;
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err_data->err_addr[i].bank = bps->bank;
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err_data->err_addr[i].err_type = bps->err_type;
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err_data->err_addr[i].mcumc_id = bps->mcumc_id;
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}
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} else {
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if (save_nps || chan_idx_v2) {
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if (amdgpu_ras_mca2pa_by_idx(adev, bps, err_data))
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return -EINVAL;
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} else {
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/* for specific old eeprom data, mca address is not stored,
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* calc it from pa
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*/
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if (bps->address == 0)
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if (amdgpu_umc_pa2mca(adev,
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bps->retired_page << AMDGPU_GPU_PAGE_SHIFT,
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&(bps->address),
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AMDGPU_NPS1_PARTITION_MODE))
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return -EINVAL;
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if (amdgpu_ras_mca2pa(adev, bps, err_data))
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return -EOPNOTSUPP;
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}
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}
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return __amdgpu_ras_restore_bad_pages(adev, err_data->err_addr,
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adev->umc.retire_unit);
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}
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/* it deal with vram only. */
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int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
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struct eeprom_table_record *bps, int pages, bool from_rom)
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@ -3156,8 +2981,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
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if (from_rom) {
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/* there is no pa recs in V3, so skip pa recs processing */
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if ((control->tbl_hdr.version < RAS_TABLE_VER_V3) &&
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!amdgpu_ras_smu_eeprom_supported(adev)) {
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if (control->tbl_hdr.version < RAS_TABLE_VER_V3) {
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for (i = 0; i < pages; i++) {
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if (control->ras_num_recs - i >= adev->umc.retire_unit) {
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if ((bps[i].address == bps[i + 1].address) &&
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@ -3174,10 +2998,8 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
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}
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}
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}
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for (; i < pages; i++) {
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ret = __amdgpu_ras_convert_rec_from_rom(adev,
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&bps[i], &err_data, nps);
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}
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for (; i < pages; i++)
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bps[i].retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT);
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con->eh_data->count_saved = con->eh_data->count;
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} else {
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@ -3202,7 +3024,7 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_err_handler_data *data;
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struct amdgpu_ras_eeprom_control *control;
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int save_count, unit_num, i;
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int save_count, unit_num;
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if (!con || !con->eh_data) {
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if (new_cnt)
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@ -3239,21 +3061,10 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
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/* only new entries are saved */
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if (unit_num && save_count) {
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/*old asics only save pa to eeprom like before*/
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if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) {
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if (amdgpu_ras_eeprom_append(control,
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&data->bps[data->count_saved], unit_num)) {
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dev_err(adev->dev, "Failed to save EEPROM table data!");
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return -EIO;
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}
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} else {
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for (i = 0; i < unit_num; i++) {
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if (amdgpu_ras_eeprom_append(control,
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&data->bps[data->count_saved +
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i * adev->umc.retire_unit], 1)) {
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dev_err(adev->dev, "Failed to save EEPROM table data!");
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return -EIO;
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}
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}
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if (amdgpu_ras_eeprom_append(control,
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&data->bps[data->count_saved], unit_num)) {
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dev_err(adev->dev, "Failed to save EEPROM table data!");
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return -EIO;
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}
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dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
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@ -3272,7 +3083,7 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
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struct amdgpu_ras_eeprom_control *control =
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&adev->psp.ras_context.ras->eeprom_control;
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struct eeprom_table_record *bps;
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int ret, i = 0;
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int ret;
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/* no bad page record, skip eeprom access */
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if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
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@ -3286,33 +3097,6 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
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if (ret) {
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dev_err(adev->dev, "Failed to load EEPROM table records!");
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} else {
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if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) {
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/*In V3, there is no pa recs, and some cases(when address==0) may be parsed
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as pa recs, so add verion check to avoid it.
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*/
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if ((control->tbl_hdr.version < RAS_TABLE_VER_V3) &&
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!amdgpu_ras_smu_eeprom_supported(adev)) {
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for (i = 0; i < control->ras_num_recs; i++) {
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if ((control->ras_num_recs - i) >= adev->umc.retire_unit) {
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if ((bps[i].address == bps[i + 1].address) &&
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(bps[i].mem_channel == bps[i + 1].mem_channel)) {
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control->ras_num_pa_recs += adev->umc.retire_unit;
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i += (adev->umc.retire_unit - 1);
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} else {
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control->ras_num_mca_recs +=
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(control->ras_num_recs - i);
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break;
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}
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} else {
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control->ras_num_mca_recs += (control->ras_num_recs - i);
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break;
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}
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}
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} else {
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control->ras_num_mca_recs = control->ras_num_recs;
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}
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}
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ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs, true);
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if (ret)
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goto out;
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@ -3431,9 +3215,6 @@ int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev)
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ret = amdgpu_ras_eeprom_init(control);
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control->is_eeprom_valid = !ret;
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if (!adev->umc.ras || !adev->umc.ras->convert_ras_err_addr)
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control->ras_num_pa_recs = control->ras_num_recs;
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if (adev->umc.ras &&
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adev->umc.ras->get_retire_flip_bits)
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adev->umc.ras->get_retire_flip_bits(adev);
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@ -3453,13 +3234,6 @@ int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev)
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adev, control->bad_channel_bitmap);
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con->update_channel_flag = false;
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}
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/* The format action is only applied to new ASICs */
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if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) >= 12 &&
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control->tbl_hdr.version < RAS_TABLE_VER_V3)
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if (!amdgpu_ras_eeprom_reset_table(control))
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if (amdgpu_ras_save_bad_pages(adev, NULL))
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dev_warn(adev->dev, "Failed to format RAS EEPROM data in V3 version!\n");
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}
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return 0;
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@ -665,7 +665,6 @@ amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
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const u32 num)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));
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struct amdgpu_device *adev = to_amdgpu_device(control);
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u32 a, b, i;
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u8 *buf, *pp;
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int res;
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@ -770,10 +769,7 @@ amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
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% control->ras_max_record_count;
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/*old asics only save pa to eeprom like before*/
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if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12)
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control->ras_num_pa_recs += num;
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else
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control->ras_num_mca_recs += num;
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control->ras_num_pa_recs += num;
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control->ras_num_bad_pages = con->bad_page_num;
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Out:
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@ -501,43 +501,3 @@ int amdgpu_umc_loop_channels(struct amdgpu_device *adev,
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return 0;
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}
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int amdgpu_umc_pages_in_a_row(struct amdgpu_device *adev,
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struct ras_err_data *err_data, uint64_t pa_addr)
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{
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struct ta_ras_query_address_output addr_out;
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/* reinit err_data */
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err_data->err_addr_cnt = 0;
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err_data->err_addr_len = adev->umc.retire_unit;
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addr_out.pa.pa = pa_addr;
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if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr)
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return adev->umc.ras->convert_ras_err_addr(adev, err_data, NULL,
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&addr_out, false);
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else
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return -EINVAL;
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}
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int amdgpu_umc_pa2mca(struct amdgpu_device *adev,
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uint64_t pa, uint64_t *mca, enum amdgpu_memory_partition nps)
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{
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struct ta_ras_query_address_input addr_in;
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struct ta_ras_query_address_output addr_out;
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int ret;
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/* nps: the pa belongs to */
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addr_in.pa.pa = pa | ((uint64_t)nps << 58);
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addr_in.addr_type = TA_RAS_PA_TO_MCA;
|
||||
ret = psp_ras_query_address(&adev->psp, &addr_in, &addr_out);
|
||||
if (ret) {
|
||||
dev_warn(adev->dev, "Failed to query RAS MCA address for 0x%llx",
|
||||
pa);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
*mca = addr_out.ma.err_addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -103,13 +103,6 @@ struct amdgpu_umc_ras {
|
|||
void *ras_error_status);
|
||||
bool (*check_ecc_err_status)(struct amdgpu_device *adev,
|
||||
enum amdgpu_mca_error_type type, void *ras_error_status);
|
||||
int (*convert_ras_err_addr)(struct amdgpu_device *adev,
|
||||
struct ras_err_data *err_data,
|
||||
struct ta_ras_query_address_input *addr_in,
|
||||
struct ta_ras_query_address_output *addr_out,
|
||||
bool dump_addr);
|
||||
uint32_t (*get_die_id_from_pa)(struct amdgpu_device *adev,
|
||||
uint64_t mca_addr, uint64_t retired_page);
|
||||
void (*get_retire_flip_bits)(struct amdgpu_device *adev);
|
||||
void (*mca_ipid_parse)(struct amdgpu_device *adev, uint64_t ipid,
|
||||
uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid);
|
||||
|
|
@ -179,10 +172,4 @@ int amdgpu_umc_loop_channels(struct amdgpu_device *adev,
|
|||
|
||||
void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,
|
||||
void *ras_error_status);
|
||||
int amdgpu_umc_pages_in_a_row(struct amdgpu_device *adev,
|
||||
struct ras_err_data *err_data, uint64_t pa_addr);
|
||||
int amdgpu_umc_lookup_bad_pages_in_a_row(struct amdgpu_device *adev,
|
||||
uint64_t pa_addr, uint64_t *pfns, int len);
|
||||
int amdgpu_umc_pa2mca(struct amdgpu_device *adev,
|
||||
uint64_t pa, uint64_t *mca, enum amdgpu_memory_partition nps);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -197,31 +197,6 @@ static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev,
|
|||
return false;
|
||||
}
|
||||
|
||||
static uint32_t umc_v12_0_get_die_id(struct amdgpu_device *adev,
|
||||
uint64_t mca_addr, uint64_t retired_page)
|
||||
{
|
||||
uint32_t die = 0;
|
||||
|
||||
/* we only calculate die id for nps1 mode right now */
|
||||
die += ((((retired_page >> 12) & 0x1ULL)^
|
||||
((retired_page >> 20) & 0x1ULL) ^
|
||||
((retired_page >> 27) & 0x1ULL) ^
|
||||
((retired_page >> 34) & 0x1ULL) ^
|
||||
((retired_page >> 41) & 0x1ULL)) << 0);
|
||||
|
||||
/* the original PA_C4 and PA_R13 may be cleared in retired_page, so
|
||||
* get them from mca_addr.
|
||||
*/
|
||||
die += ((((retired_page >> 13) & 0x1ULL) ^
|
||||
((mca_addr >> 5) & 0x1ULL) ^
|
||||
((retired_page >> 28) & 0x1ULL) ^
|
||||
((mca_addr >> 23) & 0x1ULL) ^
|
||||
((retired_page >> 42) & 0x1ULL)) << 1);
|
||||
die &= 3;
|
||||
|
||||
return die;
|
||||
}
|
||||
|
||||
static void umc_v12_0_mca_ipid_parse(struct amdgpu_device *adev, uint64_t ipid,
|
||||
uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid)
|
||||
{
|
||||
|
|
@ -240,7 +215,6 @@ struct amdgpu_umc_ras umc_v12_0_ras = {
|
|||
.hw_ops = NULL,
|
||||
},
|
||||
.check_ecc_err_status = umc_v12_0_check_ecc_err_status,
|
||||
.get_die_id_from_pa = umc_v12_0_get_die_id,
|
||||
.get_retire_flip_bits = umc_v12_0_get_retire_flip_bits,
|
||||
.mca_ipid_parse = umc_v12_0_mca_ipid_parse,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user