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pwm: qti-lpg: Add support for FM MODE
PWM channels that are configured to support Variable Frequency Mode generate a signal of fixed duty cycle (50%) and variable frequency. In such cases, the desired frequency setting is calculated differently internally, according to a new formula. Change-Id: I5cbbab9fa75fdd22c75811e5f61e69b8f4abe020 Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
This commit is contained in:
Guru Das Srinagesh
David Collins
parent
4b49bbb8e9
commit
2ab20677d4
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@ -44,6 +44,13 @@
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#define REG_LPG_HI_INDEX 0x56
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#define REG_LPG_LO_INDEX 0x57
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/* PWM module registers */
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#define REG_PWM_STATUS1 0x08
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#define FM_MODE_PRESENT BIT(0)
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#define REG_PWM_FM_MODE 0x50
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#define FM_MODE_ENABLE BIT(7)
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/* REG_LPG_PATTERN_CONFIG */
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#define LPG_PATTERN_EN_PAUSE_LO BIT(0)
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#define LPG_PATTERN_EN_PAUSE_HI BIT(1)
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@ -142,6 +149,8 @@ enum ppg_num_nvmems {
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static const int pwm_size[NUM_PWM_SIZE] = {6, 9};
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static const int clk_freq_hz[NUM_PWM_CLK] = {1024, 32768, 19200000};
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/* clk_period_ns = NSEC_PER_SEC / clk_freq_hz */
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static const int clk_period_ns[NUM_PWM_CLK] = {976562, 30517, 52};
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static const int clk_prediv[NUM_CLK_PREDIV] = {1, 3, 5, 6};
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static const int pwm_exponent[NUM_PWM_EXP] = {0, 1, 2, 3, 4, 5, 6, 7};
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@ -187,6 +196,7 @@ struct qpnp_lpg_channel {
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u8 src_sel;
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u8 subtype;
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bool lut_written;
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bool enable_pfm;
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u64 current_period_ns;
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u64 current_duty_ns;
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};
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@ -490,6 +500,61 @@ static int qpnp_lpg_set_pwm_config(struct qpnp_lpg_channel *lpg)
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return rc;
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}
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static int qpnp_lpg_set_pfm_config(struct qpnp_lpg_channel *lpg)
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{
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int rc;
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u8 val, mask;
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int pwm_clk_idx, clk_exp_idx;
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pwm_clk_idx = __find_index_in_array(lpg->pwm_config.pwm_clk,
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clk_freq_hz, ARRAY_SIZE(clk_freq_hz));
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clk_exp_idx = __find_index_in_array(lpg->pwm_config.clk_exp,
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pwm_exponent, ARRAY_SIZE(pwm_exponent));
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if (pwm_clk_idx < 0 || clk_exp_idx < 0)
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return -EINVAL;
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/* pwm_clk_idx is 1 bit lower than the register value */
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pwm_clk_idx += 1;
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val = pwm_clk_idx;
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mask = LPG_PWM_CLK_FREQ_SEL_MASK;
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rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_SIZE_CLK, mask, val);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "Write LPG_PWM_SIZE_CLK failed, rc=%d\n",
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rc);
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return rc;
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}
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val = clk_exp_idx;
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mask = LPG_PWM_FREQ_EXPONENT_MASK;
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rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_FREQ_PREDIV_CLK, mask, val);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "Write LPG_PWM_FREQ_PREDIV_CLK failed, rc=%d\n",
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rc);
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return rc;
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}
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val = lpg->pwm_config.pwm_value;
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rc = qpnp_lpg_masked_write(lpg, REG_LPG_PWM_VALUE_LSB,
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LPG_PWM_VALUE_LSB_MASK, val);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "Write LPG_PWM_VALUE_LSB failed, rc=%d\n",
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rc);
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return rc;
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}
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val = LPG_PWM_VALUE_SYNC;
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rc = qpnp_lpg_write(lpg, REG_LPG_PWM_SYNC, val);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "Write LPG_PWM_SYNC failed, rc=%d\n",
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rc);
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return rc;
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}
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return rc;
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}
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static int qpnp_lpg_set_sdam_lut_pattern(struct qpnp_lpg_channel *lpg,
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unsigned int *pattern, unsigned int length)
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{
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@ -742,7 +807,7 @@ static int qpnp_lpg_set_ramp_config(struct qpnp_lpg_channel *lpg)
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return rc;
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}
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static void __qpnp_lpg_calc_pwm_period(u64 period_ns,
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static int __qpnp_lpg_calc_pwm_period(u64 period_ns,
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struct lpg_pwm_config *pwm_config)
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{
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struct qpnp_lpg_channel *lpg = container_of(pwm_config,
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@ -827,6 +892,8 @@ static void __qpnp_lpg_calc_pwm_period(u64 period_ns,
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period_ns, pwm_config->pwm_clk, pwm_config->prediv,
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pwm_config->clk_exp, pwm_config->pwm_size);
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pr_debug("Actual period: %lluns\n", pwm_config->best_period_ns);
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return 0;
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}
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static void __qpnp_lpg_calc_pwm_duty(u64 period_ns, u64 duty_ns,
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@ -844,6 +911,76 @@ static void __qpnp_lpg_calc_pwm_duty(u64 period_ns, u64 duty_ns,
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pwm_config->pwm_value = pwm_value;
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}
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static int __qpnp_lpg_calc_pfm_period(u64 period_ns,
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struct lpg_pwm_config *pwm_config)
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{
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int clk, exp, lsb;
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int best_clk = 0, best_exp = 0, best_lsb = -EINVAL;
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u64 lsb_tmp, period_tmp, curr_p_err, last_p_err = 0;
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u64 min_p_err = U64_MAX;
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/*
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* 2 * (pwm_value_lsb + 1) * (2^pwm_exp) * NSEC_PER_SEC
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* pwm_period = ---------------------------------------------------
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* clk_freq_hz
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*
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* For each (clk, exp) solve above equation for pwm_value_lsb, and then
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* use this pwm_lsb to calculate pwm_period and compare with desired
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* period. Store the triplet values that yield the closest value to
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* desired period.
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*/
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for (clk = 0; clk < NUM_PWM_CLK; clk++) {
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last_p_err = U64_MAX;
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for (exp = 0; exp < NUM_PWM_EXP; exp++) {
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lsb_tmp = div_u64(period_ns, clk_period_ns[clk]);
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lsb_tmp >>= (exp + 1);
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lsb = lsb_tmp - 1;
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if (lsb >= 0 && lsb <= U8_MAX) {
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period_tmp = (lsb + 1);
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period_tmp <<= (exp + 1);
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period_tmp *= clk_period_ns[clk];
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curr_p_err = abs(period_ns - period_tmp);
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if (curr_p_err < min_p_err) {
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min_p_err = curr_p_err;
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/* Closest settings found! Save them. */
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best_clk = clk;
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best_exp = exp;
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best_lsb = lsb;
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/*
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* No need to set pwm_size or prediv in
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* `struct pwm_config` as they are
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* no-ops in PFM mode.
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*/
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pwm_config->best_period_ns = period_tmp;
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}
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if (curr_p_err > last_p_err)
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/* No need to iterate further */
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break;
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last_p_err = curr_p_err;
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}
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}
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}
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if (best_lsb < 0) {
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pr_err("Cannot generate %llu ns\n", period_ns);
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return -EINVAL;
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}
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pwm_config->pwm_clk = clk_freq_hz[best_clk];
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pwm_config->clk_exp = pwm_exponent[best_exp];
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pwm_config->pwm_value = best_lsb;
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pr_debug("PFM setting for period_ns %llu: pwm_clk = %d Hz, exponent = %d, pwm_val_lsb = %d\n",
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period_ns, pwm_config->pwm_clk,
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pwm_config->clk_exp, pwm_config->pwm_value);
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pr_debug("Actual PFM period: %llu ns\n", pwm_config->best_period_ns);
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return 0;
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}
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static int qpnp_lpg_config(struct qpnp_lpg_channel *lpg,
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u64 duty_ns, u64 period_ns)
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{
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@ -856,30 +993,45 @@ static int qpnp_lpg_config(struct qpnp_lpg_channel *lpg,
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}
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if (period_ns != lpg->current_period_ns) {
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__qpnp_lpg_calc_pwm_period(period_ns, &lpg->pwm_config);
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if (lpg->enable_pfm) {
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rc = __qpnp_lpg_calc_pfm_period(period_ns,
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&lpg->pwm_config);
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if (rc)
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return rc;
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} else {
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rc = __qpnp_lpg_calc_pwm_period(period_ns,
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&lpg->pwm_config);
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if (rc)
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return rc;
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/* program LUT if PWM period is changed */
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if (lpg->src_sel == LUT_PATTERN) {
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rc = qpnp_lpg_set_lut_pattern(lpg,
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/* program LUT if PWM period is changed */
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if (lpg->src_sel == LUT_PATTERN) {
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rc = qpnp_lpg_set_lut_pattern(lpg,
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lpg->ramp_config.pattern,
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lpg->ramp_config.pattern_length);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "set LUT pattern failed for LPG%d, rc=%d\n",
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lpg->lpg_idx, rc);
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return rc;
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if (rc < 0) {
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dev_err(lpg->chip->dev, "set LUT pattern failed for LPG%d, rc=%d\n",
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lpg->lpg_idx, rc);
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return rc;
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}
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lpg->lut_written = true;
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}
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lpg->lut_written = true;
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}
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}
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if (period_ns != lpg->current_period_ns ||
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duty_ns != lpg->current_duty_ns)
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/* Don't calculate duty cycle for PFM as it is fixed at 50% */
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if ((period_ns != lpg->current_period_ns ||
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duty_ns != lpg->current_duty_ns) && !lpg->enable_pfm)
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__qpnp_lpg_calc_pwm_duty(period_ns, duty_ns, &lpg->pwm_config);
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rc = qpnp_lpg_set_pwm_config(lpg);
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if (lpg->enable_pfm)
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rc = qpnp_lpg_set_pfm_config(lpg);
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else
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rc = qpnp_lpg_set_pwm_config(lpg);
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if (rc < 0) {
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dev_err(lpg->chip->dev, "Config PWM failed for channel %d, rc=%d\n",
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lpg->lpg_idx, rc);
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dev_err(lpg->chip->dev, "Config %s failed for channel %d, rc=%d\n",
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lpg->enable_pfm ? "PFM" : "PWM", lpg->lpg_idx, rc);
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return rc;
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}
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@ -1367,6 +1519,11 @@ static int qpnp_lpg_parse_pattern_dt(struct qpnp_lpg_chip *chip,
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return -EINVAL;
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}
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if (chip->lpgs[lpg_chan_id - 1].enable_pfm) {
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dev_err(chip->dev, "Cannot configure ramp for PFM-enabled channel %d\n");
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return -EINVAL;
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}
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if (chip->use_sdam) {
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rc = of_property_read_u32(child,
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"qcom,lpg-sdam-base",
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@ -1550,6 +1707,60 @@ static int qpnp_lpg_get_nvmem_dt(struct qpnp_lpg_chip *chip)
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return rc;
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}
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static int qpnp_lpg_parse_pfm_support(struct qpnp_lpg_chip *chip)
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{
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u32 chan_idx;
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u32 num_pfm_channels;
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u8 val;
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int i, rc;
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rc = of_property_count_elems_of_size(chip->dev->of_node,
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"qcom,pfm-chan-ids",
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sizeof(u32));
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if (rc < 0)
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return rc;
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if (rc == 0 || rc > chip->num_lpgs)
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return -EINVAL;
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num_pfm_channels = rc;
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for (i = 0; i < num_pfm_channels; i++) {
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rc = of_property_read_u32_index(chip->dev->of_node,
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"qcom,pfm-chan-ids", i, &chan_idx);
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if (rc) {
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dev_err(chip->dev, "Read pfm channel %d failed, rc=%d\n",
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i, rc);
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return -EINVAL;
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}
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if (chan_idx < 1 || chan_idx > chip->num_lpgs) {
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dev_err(chip->dev, "pfm chan id %u is out of range 1~%d\n",
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chan_idx, chip->num_lpgs);
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return -EINVAL;
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}
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chan_idx--; /* zero-based indexing */
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if (chip->lpgs[chan_idx].subtype == SUBTYPE_PWM) {
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rc = qpnp_lpg_read(&chip->lpgs[chan_idx],
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REG_PWM_STATUS1, &val);
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if (rc < 0) {
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dev_err(chip->dev, "Read status1 failed, rc=%d\n",
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rc);
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return rc;
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}
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if (val & FM_MODE_PRESENT)
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chip->lpgs[chan_idx].enable_pfm = true;
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else
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return -EOPNOTSUPP;
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}
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}
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return rc;
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}
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#define DEFAULT_TICK_DURATION_US 7800
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static int qpnp_lpg_parse_dt(struct qpnp_lpg_chip *chip)
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{
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@ -1579,6 +1790,15 @@ static int qpnp_lpg_parse_dt(struct qpnp_lpg_chip *chip)
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}
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}
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if (of_find_property(chip->dev->of_node,
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"qcom,pfm-chan-ids", NULL)) {
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rc = qpnp_lpg_parse_pfm_support(chip);
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if (rc < 0) {
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dev_err(chip->dev, "PFM channels specified incorrectly\n");
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return rc;
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}
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}
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if (of_find_property(chip->dev->of_node, "nvmem", NULL)) {
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chip->lut = devm_kmalloc(chip->dev, sizeof(*chip->lut),
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GFP_KERNEL);
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@ -1669,8 +1889,9 @@ static int qpnp_lpg_sdam_hw_init(struct qpnp_lpg_chip *chip)
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static int qpnp_lpg_probe(struct platform_device *pdev)
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{
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int rc;
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int rc, i;
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struct qpnp_lpg_chip *chip;
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struct qpnp_lpg_channel *lpg;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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@ -1699,6 +1920,19 @@ static int qpnp_lpg_probe(struct platform_device *pdev)
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goto err_out;
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}
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for (i = 0; i < chip->num_lpgs; i++) {
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lpg = &chip->lpgs[i];
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if (lpg->enable_pfm) {
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rc = qpnp_lpg_write(lpg, REG_PWM_FM_MODE,
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FM_MODE_ENABLE);
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if (rc < 0) {
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dev_err(chip->dev, "Write fm_mode_enable failed, rc=%d\n",
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rc);
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return rc;
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}
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}
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}
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dev_set_drvdata(chip->dev, chip);
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chip->pwm_chip.dev = chip->dev;
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chip->pwm_chip.base = -1;
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