soundwire: amd: add clock init control function

Add generic SoundWire clock initialization sequence to support
different SoundWire bus clock frequencies for ACP6.3/7.0/7.1/7.2
platforms and remove hard coding initializations for 12Mhz bus
clock frequency.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.dev>
Link: https://patch.msgid.link/20260226065638.1251771-2-Vijendar.Mukunda@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Vijendar Mukunda 2026-02-26 12:25:53 +05:30 committed by Vinod Koul
parent 4b8fc2b172
commit 2a267a8410
2 changed files with 36 additions and 11 deletions

View File

@ -27,6 +27,36 @@
#define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus)
static int amd_sdw_clk_init_ctrl(struct amd_sdw_manager *amd_manager)
{
struct sdw_bus *bus = &amd_manager->bus;
struct sdw_master_prop *prop = &bus->prop;
u32 divider;
dev_dbg(amd_manager->dev, "mclk %d max %d row %d col %d frame_rate:%d\n",
prop->mclk_freq, prop->max_clk_freq, prop->default_row,
prop->default_col, prop->default_frame_rate);
if (!prop->default_frame_rate || !prop->default_row) {
dev_err(amd_manager->dev, "Default frame_rate %d or row %d is invalid\n",
prop->default_frame_rate, prop->default_row);
return -EINVAL;
}
/* Set clock divider */
divider = (prop->mclk_freq / bus->params.curr_dr_freq);
writel(divider, amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL);
/* Set frame shape base on the actual bus frequency. */
prop->default_col = bus->params.curr_dr_freq /
prop->default_frame_rate / prop->default_row;
amd_manager->cols_index = sdw_find_col_index(prop->default_col);
amd_manager->rows_index = sdw_find_row_index(prop->default_row);
bus->params.col = prop->default_col;
bus->params.row = prop->default_row;
return 0;
}
static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager)
{
u32 val;
@ -960,6 +990,9 @@ int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager)
prop = &amd_manager->bus.prop;
if (!prop->hw_disabled) {
ret = amd_sdw_clk_init_ctrl(amd_manager);
if (ret)
return ret;
ret = amd_init_sdw_manager(amd_manager);
if (ret)
return ret;
@ -984,7 +1017,6 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
struct resource *res;
struct device *dev = &pdev->dev;
struct sdw_master_prop *prop;
struct sdw_bus_params *params;
struct amd_sdw_manager *amd_manager;
int ret;
@ -1048,14 +1080,8 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
return -EINVAL;
}
params = &amd_manager->bus.params;
params->col = AMD_SDW_DEFAULT_COLUMNS;
params->row = AMD_SDW_DEFAULT_ROWS;
prop = &amd_manager->bus.prop;
prop->clk_freq = &amd_sdw_freq_tbl[0];
prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;
prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ;
ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode);
if (ret) {
@ -1347,6 +1373,9 @@ static int __maybe_unused amd_resume_runtime(struct device *dev)
}
}
sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
ret = amd_sdw_clk_init_ctrl(amd_manager);
if (ret)
return ret;
amd_init_sdw_manager(amd_manager);
amd_enable_sdw_interrupts(amd_manager);
ret = amd_enable_sdw_manager(amd_manager);

View File

@ -203,10 +203,6 @@
#define AMD_SDW_DEVICE_STATE_D3 3
#define ACP_PME_EN 0x0001400
static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {
AMD_SDW_DEFAULT_CLK_FREQ,
};
struct sdw_manager_dp_reg {
u32 frame_fmt_reg;
u32 sample_int_reg;