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dt-bindings: PCI: Correct indentation and style in DTS example
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250324125202.81986-1-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski
Manivannan Sadhasivam
parent
c928080166
commit
2a24e06885
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@ -186,49 +186,48 @@ examples:
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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scb {
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#address-cells = <2>;
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#size-cells = <1>;
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pcie0: pcie@7d500000 {
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compatible = "brcm,bcm2711-pcie";
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reg = <0x0 0x7d500000 0x9310>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <2>;
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#size-cells = <1>;
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pcie0: pcie@7d500000 {
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compatible = "brcm,bcm2711-pcie";
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reg = <0x0 0x7d500000 0x9310>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0>;
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msi-controller;
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ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
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dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
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<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
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brcm,enable-ssc;
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brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
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msi-parent = <&pcie0>;
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msi-controller;
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ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
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dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
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<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
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brcm,enable-ssc;
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brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
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/* PCIe bridge, Root Port */
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pci@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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vpcie3v3-supply = <&vreg7>;
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ranges;
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/* PCIe bridge, Root Port */
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pci@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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vpcie3v3-supply = <&vreg7>;
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ranges;
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/* PCIe endpoint */
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pci-ep@0,0 {
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assigned-addresses =
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<0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "pci14e4,1688";
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};
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};
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/* PCIe endpoint */
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pci-ep@0,0 {
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assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "pci14e4,1688";
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};
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};
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};
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};
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@ -37,14 +37,14 @@ examples:
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#size-cells = <2>;
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pcie-ep@fc000000 {
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compatible = "cdns,cdns-pcie-ep";
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reg = <0x0 0xfc000000 0x0 0x01000000>,
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<0x0 0x80000000 0x0 0x40000000>;
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reg-names = "reg", "mem";
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cdns,max-outbound-regions = <16>;
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max-functions = /bits/ 8 <8>;
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy";
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compatible = "cdns,cdns-pcie-ep";
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reg = <0x0 0xfc000000 0x0 0x01000000>,
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<0x0 0x80000000 0x0 0x40000000>;
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reg-names = "reg", "mem";
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cdns,max-outbound-regions = <16>;
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max-functions = /bits/ 8 <8>;
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy";
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};
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};
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...
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@ -53,17 +53,17 @@ examples:
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pcie-ep@37000000 {
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compatible = "intel,keembay-pcie-ep";
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reg = <0x37000000 0x00001000>,
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<0x37100000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36000000 0x01000000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
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num-lanes = <2>;
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compatible = "intel,keembay-pcie-ep";
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reg = <0x37000000 0x00001000>,
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<0x37100000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36000000 0x01000000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
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num-lanes = <2>;
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};
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@ -75,23 +75,23 @@ examples:
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#define KEEM_BAY_A53_PCIE
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#define KEEM_BAY_A53_AUX_PCIE
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pcie@37000000 {
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compatible = "intel,keembay-pcie";
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reg = <0x37000000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36e00000 0x00200000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "atu", "config", "apb";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err";
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clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
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<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
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clock-names = "master", "aux";
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reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
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num-lanes = <2>;
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compatible = "intel,keembay-pcie";
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reg = <0x37000000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36e00000 0x00200000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "atu", "config", "apb";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err";
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clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
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<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
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clock-names = "master", "aux";
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reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
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num-lanes = <2>;
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};
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@ -65,33 +65,33 @@ unevaluatedProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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pcie0: pcie@2030000000 {
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compatible = "microchip,pcie-host-1.0";
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reg = <0x0 0x70000000 0x0 0x08000000>,
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<0x0 0x43008000 0x0 0x00002000>,
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<0x0 0x4300a000 0x0 0x00002000>;
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reg-names = "cfg", "bridge", "ctrl";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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pcie0: pcie@2030000000 {
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compatible = "microchip,pcie-host-1.0";
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reg = <0x0 0x70000000 0x0 0x08000000>,
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<0x0 0x43008000 0x0 0x00002000>,
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<0x0 0x4300a000 0x0 0x00002000>;
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reg-names = "cfg", "bridge", "ctrl";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <119>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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interrupt-parent = <&plic0>;
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msi-parent = <&pcie0>;
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msi-controller;
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bus-range = <0x00 0x7f>;
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ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
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pcie_intc0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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#interrupt-cells = <1>;
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interrupts = <119>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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interrupt-parent = <&plic0>;
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msi-parent = <&pcie0>;
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msi-controller;
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bus-range = <0x00 0x7f>;
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ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
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pcie_intc0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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@ -73,21 +73,21 @@ examples:
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a774c0-sysc.h>
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pcie0_ep: pcie-ep@fe000000 {
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compatible = "renesas,r8a774c0-pcie-ep",
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"renesas,rcar-gen3-pcie-ep";
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reg = <0xfe000000 0x80000>,
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<0xfe100000 0x100000>,
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<0xfe200000 0x200000>,
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<0x30000000 0x8000000>,
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<0x38000000 0x8000000>;
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reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cpg 319>;
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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clocks = <&cpg CPG_MOD 319>;
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clock-names = "pcie";
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max-functions = /bits/ 8 <1>;
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pcie0_ep: pcie-ep@fe000000 {
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compatible = "renesas,r8a774c0-pcie-ep",
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"renesas,rcar-gen3-pcie-ep";
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reg = <0xfe000000 0x80000>,
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<0xfe100000 0x100000>,
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<0xfe200000 0x200000>,
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<0x30000000 0x8000000>,
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<0x38000000 0x8000000>;
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reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cpg 319>;
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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clocks = <&cpg CPG_MOD 319>;
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clock-names = "pcie";
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max-functions = /bits/ 8 <1>;
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};
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@ -113,27 +113,27 @@ examples:
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pcie: pcie@fe000000 {
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compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
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reg = <0 0xfe000000 0 0x80000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
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<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
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<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
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<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
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<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
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clock-names = "pcie", "pcie_bus";
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
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resets = <&cpg 319>;
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vpcie3v3-supply = <&pcie_3v3>;
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vpcie12v-supply = <&pcie_12v>;
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};
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
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<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
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<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
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<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
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<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
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clock-names = "pcie", "pcie_bus";
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
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resets = <&cpg 319>;
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vpcie3v3-supply = <&pcie_3v3>;
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vpcie12v-supply = <&pcie_12v>;
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};
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};
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@ -76,64 +76,62 @@ unevaluatedProperties: false
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examples:
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- |
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versal {
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#address-cells = <2>;
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#size-cells = <2>;
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cpm_pcie: pcie@fca10000 {
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compatible = "xlnx,versal-cpm-host-1.00";
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device_type = "pci";
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
|
||||
interrupts = <0 72 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
|
||||
<0 0 0 2 &pcie_intc_0 1>,
|
||||
<0 0 0 3 &pcie_intc_0 2>,
|
||||
<0 0 0 4 &pcie_intc_0 3>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
|
||||
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
|
||||
msi-map = <0x0 &its_gic 0x0 0x10000>;
|
||||
reg = <0x0 0xfca10000 0x0 0x1000>,
|
||||
<0x6 0x00000000 0x0 0x10000000>;
|
||||
reg-names = "cpm_slcr", "cfg";
|
||||
pcie_intc_0: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
pcie@fca10000 {
|
||||
compatible = "xlnx,versal-cpm-host-1.00";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <0 72 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
|
||||
<0 0 0 2 &pcie_intc_0 1>,
|
||||
<0 0 0 3 &pcie_intc_0 2>,
|
||||
<0 0 0 4 &pcie_intc_0 3>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
|
||||
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
|
||||
msi-map = <0x0 &its_gic 0x0 0x10000>;
|
||||
reg = <0x0 0xfca10000 0x0 0x1000>,
|
||||
<0x6 0x00000000 0x0 0x10000000>;
|
||||
reg-names = "cpm_slcr", "cfg";
|
||||
pcie_intc_0: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpm5_pcie: pcie@fcdd0000 {
|
||||
compatible = "xlnx,versal-cpm5-host";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <0 72 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
|
||||
<0 0 0 2 &pcie_intc_1 1>,
|
||||
<0 0 0 3 &pcie_intc_1 2>,
|
||||
<0 0 0 4 &pcie_intc_1 3>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
|
||||
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
|
||||
msi-map = <0x0 &its_gic 0x0 0x10000>;
|
||||
reg = <0x00 0xfcdd0000 0x00 0x1000>,
|
||||
<0x06 0x00000000 0x00 0x1000000>,
|
||||
<0x00 0xfce20000 0x00 0x1000000>;
|
||||
reg-names = "cpm_slcr", "cfg", "cpm_csr";
|
||||
|
||||
pcie_intc_1: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
pcie@fcdd0000 {
|
||||
compatible = "xlnx,versal-cpm5-host";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <0 72 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
|
||||
<0 0 0 2 &pcie_intc_1 1>,
|
||||
<0 0 0 3 &pcie_intc_1 2>,
|
||||
<0 0 0 4 &pcie_intc_1 3>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
|
||||
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
|
||||
msi-map = <0x0 &its_gic 0x0 0x10000>;
|
||||
reg = <0x00 0xfcdd0000 0x00 0x1000>,
|
||||
<0x06 0x00000000 0x00 0x1000000>,
|
||||
<0x00 0xfce20000 0x00 0x1000000>;
|
||||
reg-names = "cpm_slcr", "cfg", "cpm_csr";
|
||||
|
||||
pcie_intc_1: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user