dt-bindings: clock: fsl-sai: Document i.MX8M support

The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
shifted by +8 bytes and requires additional bus clock. Document support
for the i.MX8M variant of the IP with this register shift and additional
clock. Update the description slightly.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marek Vasut <marex@nabladev.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Marek Vasut 2026-04-09 02:29:01 +02:00 committed by Stephen Boyd
parent c369299895
commit 29e64a3708
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@ -10,10 +10,10 @@ maintainers:
- Michael Walle <michael@walle.cc>
description: |
It is possible to use the BCLK pin of a SAI module as a generic clock
output. Some SoC are very constrained in their pin multiplexer
configuration. Eg. pins can only be changed groups. For example, on the
LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
It is possible to use the BCLK pin of a SAI module as a generic
clock output. Some SoC are very constrained in their pin multiplexer
configuration. E.g. pins can only be changed in groups. For example, on
the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
the second pins are wasted. Using this binding it is possible to use the
clock of the second SAI as a MCLK clock for an audio codec, for example.
@ -21,17 +21,46 @@ description: |
properties:
compatible:
const: fsl,vf610-sai-clock
oneOf:
- items:
- enum:
- fsl,imx8mm-sai-clock
- fsl,imx8mn-sai-clock
- fsl,imx8mp-sai-clock
- const: fsl,imx8mq-sai-clock
- items:
- enum:
- fsl,imx8mq-sai-clock
- fsl,vf610-sai-clock
reg:
maxItems: 1
clocks:
maxItems: 1
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: bus
- const: mclk1
'#clock-cells':
const: 0
allOf:
- if:
properties:
compatible:
contains:
const: fsl,vf610-sai-clock
then:
properties:
clocks:
maxItems: 1
clock-names: false
required:
- compatible
- reg