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dt-bindings: clock: fsl-sai: Document i.MX8M support
The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers shifted by +8 bytes and requires additional bus clock. Document support for the i.MX8M variant of the IP with this register shift and additional clock. Update the description slightly. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Marek Vasut <marex@nabladev.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -10,10 +10,10 @@ maintainers:
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- Michael Walle <michael@walle.cc>
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description: |
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It is possible to use the BCLK pin of a SAI module as a generic clock
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output. Some SoC are very constrained in their pin multiplexer
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configuration. Eg. pins can only be changed groups. For example, on the
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LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
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It is possible to use the BCLK pin of a SAI module as a generic
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clock output. Some SoC are very constrained in their pin multiplexer
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configuration. E.g. pins can only be changed in groups. For example, on
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the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
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the second pins are wasted. Using this binding it is possible to use the
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clock of the second SAI as a MCLK clock for an audio codec, for example.
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@ -21,17 +21,46 @@ description: |
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properties:
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compatible:
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const: fsl,vf610-sai-clock
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oneOf:
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- items:
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- enum:
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- fsl,imx8mm-sai-clock
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- fsl,imx8mn-sai-clock
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- fsl,imx8mp-sai-clock
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- const: fsl,imx8mq-sai-clock
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- items:
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- enum:
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- fsl,imx8mq-sai-clock
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- fsl,vf610-sai-clock
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: bus
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- const: mclk1
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'#clock-cells':
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const: 0
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,vf610-sai-clock
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names: false
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required:
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- compatible
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- reg
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