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arm64/mm: Re-organise setting up FEAT_S1PIE registers PIRE0_EL1 and PIR_EL1
mov_q cannot really move PIE_E[0|1] macros into a general purpose register as expected if those macro constants contain some 128 bit layout elements, that are required for D128 page tables. The primary issue is that for D128, PIE_E[0|1] are defined in terms of 128-bit types with shifting and masking, which the assembler can't accommodate. Instead pre-calculate these PIRE0_EL1/PIR_EL1 constants into asm-offsets.h based PIE_E0_ASM/PIE_E1_ASM which can then be used in arch/arm64/mm/proc.S. While here also drop PTE_MAYBE_NG/PTE_MAYBE_SHARED assembly overrides which are not required any longer, as the compiler toolchains are smart enough to compute both the PIE_[E0|E1]_ASM constants in all scenarios. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Ryan Roberts <ryan.roberts@arm.com> Link: https://lore.kernel.org/r/20250429050511.1663235-1-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -182,5 +182,7 @@ int main(void)
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#ifdef CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS
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DEFINE(FTRACE_OPS_DIRECT_CALL, offsetof(struct ftrace_ops, direct_call));
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#endif
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DEFINE(PIE_E0_ASM, PIE_E0);
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DEFINE(PIE_E1_ASM, PIE_E1);
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return 0;
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}
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@ -512,26 +512,11 @@ alternative_else_nop_endif
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ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
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cbz x1, .Lskip_indirection
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/*
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* The PROT_* macros describing the various memory types may resolve to
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* C expressions if they include the PTE_MAYBE_* macros, and so they
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* can only be used from C code. The PIE_E* constants below are also
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* defined in terms of those macros, but will mask out those
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* PTE_MAYBE_* constants, whether they are set or not. So #define them
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* as 0x0 here so we can evaluate the PIE_E* constants in asm context.
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*/
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#define PTE_MAYBE_NG 0
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#define PTE_MAYBE_SHARED 0
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mov_q x0, PIE_E0
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mov_q x0, PIE_E0_ASM
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msr REG_PIRE0_EL1, x0
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mov_q x0, PIE_E1
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mov_q x0, PIE_E1_ASM
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msr REG_PIR_EL1, x0
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#undef PTE_MAYBE_NG
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#undef PTE_MAYBE_SHARED
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orr tcr2, tcr2, TCR2_EL1_PIE
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msr REG_TCR2_EL1, x0
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