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clk: rockchip: add clock controller for rk1808

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Add the clock tree definition for the new rk1808 SoC.

Change-Id: I86e502b27e0695c77e9937dfd7cffa14b5711954
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-07-03 08:51:37 +08:00 committed by Tao Huang
parent d4cc0ecf0c
commit 29c4d612eb
4 changed files with 1255 additions and 3 deletions
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1
drivers/clk/rockchip/Makefile
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@ -14,6 +14,7 @@ obj-y += clk-half-divider.o
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_CPU_PX30) += clk-px30.o
obj-$(CONFIG_CPU_RK1808) += clk-rk1808.o
obj-$(CONFIG_CPU_RK3036) += clk-rk3036.o
obj-$(CONFIG_CPU_RK312X) += clk-rk3128.o
obj-$(CONFIG_CPU_RK3188) += clk-rk3188.o

1225
drivers/clk/rockchip/clk-rk1808.c Normal file
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File diff suppressed because it is too large Load Diff

27
drivers/clk/rockchip/clk.h
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@ -73,7 +73,32 @@ struct clk;
#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
#define PX30_PMU_MODE 0x0020
/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
/*
* register positions shared by RK1808 RK2928, RK3036,
* RK3066, RK3188 and RK3228
*/
#define RK1808_PLL_CON(x) ((x) * 0x4)
#define RK1808_MODE_CON 0xa0
#define RK1808_MISC_CON 0xa4
#define RK1808_MISC1_CON 0xa8
#define RK1808_GLB_SRST_FST 0xb8
#define RK1808_GLB_SRST_SND 0xbc
#define RK1808_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK1808_CLKGATE_CON(x) ((x) * 0x4 + 0x230)
#define RK1808_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
#define RK1808_SDMMC_CON0 0x380
#define RK1808_SDMMC_CON1 0x384
#define RK1808_SDIO_CON0 0x388
#define RK1808_SDIO_CON1 0x38c
#define RK1808_EMMC_CON0 0x390
#define RK1808_EMMC_CON1 0x394
#define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000)
#define RK1808_PMU_MODE_CON 0x4020
#define RK1808_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x4040)
#define RK1808_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x4080)
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)

5
include/dt-bindings/clock/rk1808-cru.h
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@ -351,8 +351,9 @@
#define SRST_SFC_H 136
#define SRST_SFC 137
#define SRST_GMAC_NIU_A 140
#define SRST_GMAC_NIU_P 141
#define SRST_GAMC_A 142
#define SRST_GMAC_NIU_H 141
#define SRST_GMAC_NIU_P 142
#define SRST_GAMC_A 143
/* cru_softrst_con9 */
#define SRST_PMU_NIU_P 144