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net: mdio: realtek-rtl9300: Add prefix to register field defines

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The current Realtek Otto MDIO driver has some define leftovers without
a SoC prefix. When adding new devices there will be an overlap for some
of them. Sort this out as follows:

- PHY_CTRL_CMD/PHY_CTRL_MMD_DEVAD/PHY_CTRL_MMD_REG are common for all
  series. Leave them as is but move them into a separate block.
- Add RTL9300 prefix to all other defines and adapt the callers.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://patch.msgid.link/20260610194145.4153668-3-markus.stockhausen@gmx.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Markus Stockhausen 2026-06-10 21:41:42 +02:00 committed by Jakub Kicinski
parent a390863b49
commit 29a540b56e
1 changed files with 32 additions and 31 deletions
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63
drivers/net/mdio/mdio-realtek-rtl9300.c
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@ -59,23 +59,24 @@
#define RTL9300_SMI_PORT0_15_POLLING_SEL 0xca08
#define RTL9300_SMI_ACCESS_PHY_CTRL_0 0xcb70
#define RTL9300_SMI_ACCESS_PHY_CTRL_1 0xcb74
#define PHY_CTRL_REG_ADDR GENMASK(24, 20)
#define PHY_CTRL_PARK_PAGE GENMASK(19, 15)
#define PHY_CTRL_MAIN_PAGE GENMASK(14, 3)
#define PHY_CTRL_WRITE BIT(2)
#define PHY_CTRL_READ 0
#define PHY_CTRL_TYPE_C45 BIT(1)
#define PHY_CTRL_TYPE_C22 0
#define PHY_CTRL_CMD BIT(0)
#define PHY_CTRL_FAIL BIT(25)
#define RTL9300_PHY_CTRL_REG_ADDR GENMASK(24, 20)
#define RTL9300_PHY_CTRL_PARK_PAGE GENMASK(19, 15)
#define RTL9300_PHY_CTRL_MAIN_PAGE GENMASK(14, 3)
#define RTL9300_PHY_CTRL_WRITE BIT(2)
#define RTL9300_PHY_CTRL_READ 0
#define RTL9300_PHY_CTRL_TYPE_C45 BIT(1)
#define RTL9300_PHY_CTRL_TYPE_C22 0
#define RTL9300_PHY_CTRL_FAIL BIT(25)
#define RTL9300_SMI_ACCESS_PHY_CTRL_2 0xcb78
#define PHY_CTRL_INDATA GENMASK(31, 16)
#define PHY_CTRL_DATA GENMASK(15, 0)
#define RTL9300_PHY_CTRL_INDATA GENMASK(31, 16)
#define RTL9300_PHY_CTRL_DATA GENMASK(15, 0)
#define RTL9300_SMI_ACCESS_PHY_CTRL_3 0xcb7c
#define PHY_CTRL_MMD_DEVAD GENMASK(20, 16)
#define PHY_CTRL_MMD_REG GENMASK(15, 0)
#define RTL9300_SMI_PORT0_5_ADDR_CTRL 0xcb80
#define PHY_CTRL_CMD BIT(0)
#define PHY_CTRL_MMD_DEVAD GENMASK(20, 16)
#define PHY_CTRL_MMD_REG GENMASK(15, 0)
#define MAP_ADDRS_PER_REG 6
#define MAP_BITS_PER_ADDR 5
#define MAP_BITS_PER_BUS 2
@ -204,7 +205,7 @@ static int otto_emdio_read_cmd(struct mii_bus *bus, u32 cmd,
if (ret)
return ret;
*value = FIELD_GET(PHY_CTRL_DATA, *value);
*value = FIELD_GET(RTL9300_PHY_CTRL_DATA, *value);
return 0;
}
@ -223,27 +224,27 @@ static int otto_emdio_9300_read_c22(struct mii_bus *bus, int port, int regnum, u
{
struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
struct otto_emdio_cmd_regs cmd_data = {
.c22_data = FIELD_PREP(PHY_CTRL_REG_ADDR, regnum) |
FIELD_PREP(PHY_CTRL_PARK_PAGE, 0x1f) |
FIELD_PREP(PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
.io_data = FIELD_PREP(PHY_CTRL_INDATA, port),
.c22_data = FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) |
FIELD_PREP(RTL9300_PHY_CTRL_PARK_PAGE, 0x1f) |
FIELD_PREP(RTL9300_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
.io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, port),
};
return otto_emdio_read_cmd(bus, PHY_CTRL_TYPE_C22, &cmd_data, value);
return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, &cmd_data, value);
}
static int otto_emdio_9300_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)
{
struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
struct otto_emdio_cmd_regs cmd_data = {
.c22_data = FIELD_PREP(PHY_CTRL_REG_ADDR, regnum) |
FIELD_PREP(PHY_CTRL_PARK_PAGE, 0x1f) |
FIELD_PREP(PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
.io_data = FIELD_PREP(PHY_CTRL_INDATA, value),
.c22_data = FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) |
FIELD_PREP(RTL9300_PHY_CTRL_PARK_PAGE, 0x1f) |
FIELD_PREP(RTL9300_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
.io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, value),
.port_mask_low = BIT(port),
};
return otto_emdio_write_cmd(bus, PHY_CTRL_TYPE_C22, &cmd_data);
return otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, &cmd_data);
}
static int otto_emdio_9300_read_c45(struct mii_bus *bus, int port,
@ -252,10 +253,10 @@ static int otto_emdio_9300_read_c45(struct mii_bus *bus, int port,
struct otto_emdio_cmd_regs cmd_data = {
.c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
.io_data = FIELD_PREP(PHY_CTRL_INDATA, port),
.io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, port),
};
return otto_emdio_read_cmd(bus, PHY_CTRL_TYPE_C45, &cmd_data, value);
return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data, value);
}
static int otto_emdio_9300_write_c45(struct mii_bus *bus, int port,
@ -264,11 +265,11 @@ static int otto_emdio_9300_write_c45(struct mii_bus *bus, int port,
struct otto_emdio_cmd_regs cmd_data = {
.c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
.io_data = FIELD_PREP(PHY_CTRL_INDATA, value),
.io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, value),
.port_mask_low = BIT(port),
};
return otto_emdio_write_cmd(bus, PHY_CTRL_TYPE_C45, &cmd_data);
return otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data);
}
static int otto_emdio_read_c22(struct mii_bus *bus, int phy_id, int regnum)
@ -582,9 +583,9 @@ static int otto_emdio_probe(struct platform_device *pdev)
static const struct otto_emdio_info otto_emdio_9300_info = {
.addr_map_base = RTL9300_SMI_PORT0_5_ADDR_CTRL,
.bus_map_base = RTL9300_SMI_PORT0_15_POLLING_SEL,
.cmd_fail = PHY_CTRL_FAIL,
.cmd_read = PHY_CTRL_READ,
.cmd_write = PHY_CTRL_WRITE,
.cmd_fail = RTL9300_PHY_CTRL_FAIL,
.cmd_read = RTL9300_PHY_CTRL_READ,
.cmd_write = RTL9300_PHY_CTRL_WRITE,
.cmd_regs = {
.c22_data = RTL9300_SMI_ACCESS_PHY_CTRL_1,
.c45_data = RTL9300_SMI_ACCESS_PHY_CTRL_3,