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phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REF

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According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097)
to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0
selects the ROPLL.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-2-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Damon Ding 2025-02-05 18:51:54 +08:00 committed by Vinod Koul
parent 279950205d
commit 2947c8065e
1 changed files with 2 additions and 2 deletions
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4
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@ -94,8 +94,8 @@
#define LCPLL_ALONE_MODE BIT(1)
/* CMN_REG(0097) */
#define DIG_CLK_SEL BIT(1)
#define ROPLL_REF BIT(1)
#define LCPLL_REF 0
#define LCPLL_REF BIT(1)
#define ROPLL_REF 0
/* CMN_REG(0099) */
#define CMN_ROPLL_ALONE_MODE BIT(2)
#define ROPLL_ALONE_MODE BIT(2)