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riscv: dts: starfive: add PCIe dts configuration for JH7110

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Add PCIe dts configuraion for JH7110 SoC platform. The Star64 only has
one exposed PCIe port, so only the Mars and VisionFive 2 get two
enabled.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
[conor: squash in star64's single exposed port]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Minda Chen 2024-06-21 16:22:31 +08:00 committed by Conor Dooley
parent 3f41368fbf
commit 2904244a8c
5 changed files with 167 additions and 0 deletions
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62
arch/riscv/boot/dts/starfive/jh7110-common.dtsi
View File

@ -294,6 +294,20 @@ &mmc1 {
status = "okay";
};
&pcie0 {
perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
phys = <&pciephy0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
};
&pcie1 {
perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
phys = <&pciephy1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
};
&pwmdac {
pinctrl-names = "default";
pinctrl-0 = <&pwmdac_pins>;
@ -473,6 +487,54 @@ GPOEN_SYS_SDIO1_DATA3,
};
};
pcie0_pins: pcie0-0 {
clkreq-pins {
pinmux = <GPIOMUX(27, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-down;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
wake-pins {
pinmux = <GPIOMUX(32, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
pcie1_pins: pcie1-0 {
clkreq-pins {
pinmux = <GPIOMUX(29, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-down;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
wake-pins {
pinmux = <GPIOMUX(21, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
pwmdac_pins: pwmdac-0 {
pwmdac-pins {
pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,

7
arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
View File

@ -17,6 +17,13 @@ &gmac0 {
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&phy0 {
motorcomm,tx-clk-adj-enabled;

4
arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
View File

@ -39,6 +39,10 @@ phy1: ethernet-phy@1 {
};
};
&pcie1 {
status = "okay";
};
&phy0 {
rx-internal-delay-ps = <1900>;
tx-internal-delay-ps = <1500>;

8
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
View File

@ -32,3 +32,11 @@ phy1: ethernet-phy@1 {
&mmc0 {
non-removable;
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};

86
arch/riscv/boot/dts/starfive/jh7110.dtsi
View File

@ -1214,5 +1214,91 @@ voutcrg: clock-controller@295c0000 {
#reset-cells = <1>;
power-domains = <&pwrc JH7110_PD_VOUT>;
};
pcie0: pcie@940000000 {
compatible = "starfive,jh7110-pcie";
reg = <0x9 0x40000000 0x0 0x1000000>,
<0x0 0x2b000000 0x0 0x100000>;
reg-names = "cfg", "apb";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
interrupts = <56>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
msi-controller;
device_type = "pci";
starfive,stg-syscon = <&stg_syscon>;
bus-range = <0x0 0xff>;
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
<&stgcrg JH7110_STGCLK_PCIE0_TL>,
<&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
<&stgcrg JH7110_STGCLK_PCIE0_APB>;
clock-names = "noc", "tl", "axi_mst0", "apb";
resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
<&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
<&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
<&stgcrg JH7110_STGRST_PCIE0_BRG>,
<&stgcrg JH7110_STGRST_PCIE0_CORE>,
<&stgcrg JH7110_STGRST_PCIE0_APB>;
reset-names = "mst0", "slv0", "slv", "brg",
"core", "apb";
status = "disabled";
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
pcie1: pcie@9c0000000 {
compatible = "starfive,jh7110-pcie";
reg = <0x9 0xc0000000 0x0 0x1000000>,
<0x0 0x2c000000 0x0 0x100000>;
reg-names = "cfg", "apb";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
<0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
interrupts = <57>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
msi-controller;
device_type = "pci";
starfive,stg-syscon = <&stg_syscon>;
bus-range = <0x0 0xff>;
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
<&stgcrg JH7110_STGCLK_PCIE1_TL>,
<&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
<&stgcrg JH7110_STGCLK_PCIE1_APB>;
clock-names = "noc", "tl", "axi_mst0", "apb";
resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
<&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
<&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
<&stgcrg JH7110_STGRST_PCIE1_BRG>,
<&stgcrg JH7110_STGRST_PCIE1_CORE>,
<&stgcrg JH7110_STGRST_PCIE1_APB>;
reset-names = "mst0", "slv0", "slv", "brg",
"core", "apb";
status = "disabled";
pcie_intc1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
};