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spi: mchp-pci1xxxx: Fix minor bugs in spi-pci1xxxx
Merge series from Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>: This patch series fixes the following bugs in spi-pci1xxxx driver: 1. Length of SPI transactions is improper 2. SPI transactions fail after suspend and resume 3. Incorrect implementation of pci1xxxx_spi_set_cs API
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commit
28e0377c3a
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@ -58,7 +58,7 @@
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#define VENDOR_ID_MCHP 0x1055
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#define SPI_SUSPEND_CONFIG 0x101
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#define SPI_RESUME_CONFIG 0x303
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#define SPI_RESUME_CONFIG 0x203
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struct pci1xxxx_spi_internal {
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u8 hw_inst;
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@ -114,17 +114,14 @@ static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable)
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/* Set the DEV_SEL bits of the SPI_MST_CTL_REG */
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regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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if (enable) {
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if (!enable) {
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regval |= SPI_FORCE_CE;
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regval &= ~SPI_MST_CTL_DEVSEL_MASK;
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regval |= (spi_get_chipselect(spi, 0) << 25);
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writel(regval,
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par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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} else {
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regval &= ~(spi_get_chipselect(spi, 0) << 25);
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writel(regval,
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par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval &= ~SPI_FORCE_CE;
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}
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writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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}
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static u8 pci1xxxx_get_clock_div(u32 hz)
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@ -199,8 +196,9 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
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else
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regval &= ~SPI_MST_CTL_MODE_SEL;
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regval |= ((clkdiv << 5) | SPI_FORCE_CE | (len << 8));
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regval |= (clkdiv << 5);
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regval &= ~SPI_MST_CTL_CMD_LEN_MASK;
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regval |= (len << 8);
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writel(regval, par->reg_base +
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SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval = readl(par->reg_base +
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@ -222,10 +220,6 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
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}
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}
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}
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regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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regval &= ~SPI_FORCE_CE;
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writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
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p->spi_xfer_in_progress = false;
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return 0;
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