From 0209861877531ae0744552f3fd0531303d665b52 Mon Sep 17 00:00:00 2001 From: Furkan Kardame Date: Mon, 27 Jun 2022 23:22:08 +0300 Subject: [PATCH 01/19] arm64: dts: rockchip: Enable video output on rk3566-roc-pc Add the device tree nodes to enable video output on the Station M2. Enable the GPU and HDMI nodes and fix the GPU regulator range. Signed-off-by: Furkan Kardame Link: https://lore.kernel.org/r/20220627202208.45770-1-f.kardame@manjaro.org Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts index 57759b66d44d..dba648c2f57e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -4,6 +4,7 @@ #include #include +#include #include "rk3566.dtsi" / { @@ -27,6 +28,17 @@ gmac1_clkin: external-gmac1-clock { #clock-cells = <0>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -149,6 +161,29 @@ &gmac1m0_clkinout status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; @@ -577,3 +612,20 @@ &usb_host0_ehci { &usb_host0_ohci { status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 3a5247120668041c8e9eb190497296656b66bf9a Mon Sep 17 00:00:00 2001 From: Hugh Cole-Baker Date: Tue, 19 Oct 2021 22:58:43 +0100 Subject: [PATCH 02/19] arm64: dts: rockchip: enable gamma control on RK3399 Define the memory region on RK3399 VOPs containing the gamma LUT at base+0x2000. Signed-off-by: Hugh Cole-Baker Tested-by: Linus Heckemann Link: https://lore.kernel.org/r/20211019215843.42718-4-sigmaris@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index f4fbd5bece0e..92c2207e686c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1702,7 +1702,7 @@ i2s2: i2s@ff8a0000 { vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit"; - reg = <0x0 0xff8f0000 0x0 0x3efc>; + reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; interrupts = ; assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; assigned-clock-rates = <400000000>, <100000000>; @@ -1758,7 +1758,7 @@ vopl_mmu: iommu@ff8f3f00 { vopb: vop@ff900000 { compatible = "rockchip,rk3399-vop-big"; - reg = <0x0 0xff900000 0x0 0x3efc>; + reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; interrupts = ; assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; assigned-clock-rates = <400000000>, <100000000>; From b360cfbf86a918b835e673b9da5faf972a9bf146 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 17 Aug 2022 12:33:55 -0700 Subject: [PATCH 03/19] dt-bindings: arm: rockchip: Add gru-scarlet sku{2,4} variants The Gru-Scarlet family includes a variety of SKU identifiers, using parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few different manufacturer names) also use the Innolux display. For reference, the original vendor tree source: CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc Signed-off-by: Brian Norris Link: https://lore.kernel.org/r/20220817123350.1.Ibb15bab32dbfa0d89f86321c4eae7adbc8d7ad4a@changeid Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ae7fe15a3b89..58fc4b677321 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -373,30 +373,55 @@ properties: - const: google,gru - const: rockchip,rk3399 - - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) + - description: | + Google Scarlet - Innolux display (Acer Chromebook Tab 10 and more) items: + - const: google,scarlet-rev15-sku2 + - const: google,scarlet-rev15-sku4 - const: google,scarlet-rev15-sku6 - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku2 + - const: google,scarlet-rev14-sku4 - const: google,scarlet-rev14-sku6 - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku2 + - const: google,scarlet-rev13-sku4 - const: google,scarlet-rev13-sku6 - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku2 + - const: google,scarlet-rev12-sku4 - const: google,scarlet-rev12-sku6 - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku2 + - const: google,scarlet-rev11-sku4 - const: google,scarlet-rev11-sku6 - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku2 + - const: google,scarlet-rev10-sku4 - const: google,scarlet-rev10-sku6 - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku2 + - const: google,scarlet-rev9-sku4 - const: google,scarlet-rev9-sku6 - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku2 + - const: google,scarlet-rev8-sku4 - const: google,scarlet-rev8-sku6 - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku2 + - const: google,scarlet-rev7-sku4 - const: google,scarlet-rev7-sku6 - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku2 + - const: google,scarlet-rev6-sku4 - const: google,scarlet-rev6-sku6 - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku2 + - const: google,scarlet-rev5-sku4 - const: google,scarlet-rev5-sku6 - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku2 + - const: google,scarlet-rev4-sku4 - const: google,scarlet-rev4-sku6 - const: google,scarlet-rev4 - const: google,scarlet From 578980728868fcd99bbb5af12e50b38d2e66f5aa Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 17 Aug 2022 12:33:56 -0700 Subject: [PATCH 04/19] arm64: dts: rockchip: Support gru-scarlet sku{2,4} variants The Gru-Scarlet family includes a variety of SKU identifiers, using parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few different manufacturer names) also use the Innolux display. Without this, a SKU2 device may non-deterministically (depending on the matching order of DTBs and bootloader behavior) select either one of the INX DTBs (rk3399-gru-scarlet-dumo.dtb or rk3399-gru-scarlet-inx.dtb) or the KingDisplay DTB (rk3399-gru-scarlet-kd.dtb), to ill effect. For reference, the original vendor tree source: CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc Signed-off-by: Brian Norris Link: https://lore.kernel.org/r/20220817123350.2.I5f4fd0808a927b08e267c189712fb4a85931fd3b@changeid Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-gru-scarlet-inx.dts | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts index 2d721a974790..5d1879033e7c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts @@ -11,17 +11,29 @@ / { model = "Google Scarlet"; - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", + compatible = "google,scarlet-rev15-sku2", "google,scarlet-rev15-sku4", + "google,scarlet-rev15-sku6", "google,scarlet-rev15", + "google,scarlet-rev14-sku2", "google,scarlet-rev14-sku4", "google,scarlet-rev14-sku6", "google,scarlet-rev14", + "google,scarlet-rev13-sku2", "google,scarlet-rev13-sku4", "google,scarlet-rev13-sku6", "google,scarlet-rev13", + "google,scarlet-rev12-sku2", "google,scarlet-rev12-sku4", "google,scarlet-rev12-sku6", "google,scarlet-rev12", + "google,scarlet-rev11-sku2", "google,scarlet-rev11-sku4", "google,scarlet-rev11-sku6", "google,scarlet-rev11", + "google,scarlet-rev10-sku2", "google,scarlet-rev10-sku4", "google,scarlet-rev10-sku6", "google,scarlet-rev10", + "google,scarlet-rev9-sku2", "google,scarlet-rev9-sku4", "google,scarlet-rev9-sku6", "google,scarlet-rev9", + "google,scarlet-rev8-sku2", "google,scarlet-rev8-sku4", "google,scarlet-rev8-sku6", "google,scarlet-rev8", + "google,scarlet-rev7-sku2", "google,scarlet-rev7-sku4", "google,scarlet-rev7-sku6", "google,scarlet-rev7", + "google,scarlet-rev6-sku2", "google,scarlet-rev6-sku4", "google,scarlet-rev6-sku6", "google,scarlet-rev6", + "google,scarlet-rev5-sku2", "google,scarlet-rev5-sku4", "google,scarlet-rev5-sku6", "google,scarlet-rev5", + "google,scarlet-rev4-sku2", "google,scarlet-rev4-sku4", "google,scarlet-rev4-sku6", "google,scarlet-rev4", "google,scarlet", "google,gru", "rockchip,rk3399"; }; From 1c33f8508b625e8c792b396155f6ef7cbc8f4212 Mon Sep 17 00:00:00 2001 From: Markus Reichl Date: Thu, 15 Sep 2022 13:11:36 +0200 Subject: [PATCH 05/19] arm64: dts: rockchip: Add HDMI supplies on rk3399-roc-pc Add avdd-0v9-supply and avdd-1v8-supply to hdmi node for rk3399-roc-pc to silence dmesg warning and match the name of the 1v8 supply to the circuit sheet. Signed-off-by: Markus Reichl Link: https://lore.kernel.org/r/20220915111138.1108-1-m.reichl@fivetechno.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index acb174d3a8c5..2f4b1b2e3ac7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -271,6 +271,8 @@ &gpu { }; &hdmi { + avdd-0v9-supply = <&vcca0v9_hdmi>; + avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; @@ -369,8 +371,8 @@ regulator-state-mem { }; }; - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; From 27c92c60d1e6d37e2c34fc18e1e36186fade2186 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 16 Sep 2022 11:17:46 +0200 Subject: [PATCH 06/19] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30 The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are 2-channel I2S/PCM controllers handled by the same controller driver, and i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller driver. This adds the device tree node required to enable I2S0 on PX30. This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX (rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20220916091746.35108-1-foss+kernel@0leil.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 214f94fea3dc..bfa3580429d1 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -365,6 +365,28 @@ uart0: serial@ff030000 { status = "disabled"; }; + i2s0_8ch: i2s@ff060000 { + compatible = "rockchip,px30-i2s-tdm"; + reg = <0x0 0xff060000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac 16>, <&dmac 17>; + dma-names = "tx", "rx"; + rockchip,grf = <&grf>; + resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; + reset-names = "tx-m", "rx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx + &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx + &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 + &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 + &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 + &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s1_2ch: i2s@ff070000 { compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff070000 0x0 0x1000>; From 3503c0eb4d1058b7eda87bf4e432463813c43759 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 15 Sep 2022 10:25:10 +0800 Subject: [PATCH 07/19] dt-bindings: Add doc for FriendlyARM NanoPi R4S Enterprise Edition Add devicetree binding documentation for the FriendlyARM NanoPi R4S Enterprise Edition. Signed-off-by: Tianling Shen Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220915022511.4267-1-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 58fc4b677321..4c64d9ff089c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -161,6 +161,7 @@ properties: - friendlyarm,nanopi-m4b - friendlyarm,nanopi-neo4 - friendlyarm,nanopi-r4s + - friendlyarm,nanopi-r4s-enterprise - const: rockchip,rk3399 - description: GeekBuying GeekBox From fd573b2bf2d2cf61e835ea68bbaa34c71d4a70d7 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 15 Sep 2022 10:25:11 +0800 Subject: [PATCH 08/19] arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise Edition The only diffrence against the standrard edition is that the enterprise one has a built-in EEPROM chip which stores a globally unique MAC address. Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20220915022511.4267-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3399-nanopi-r4s-enterprise.dts | 29 +++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 94639380ec1e..8c15593c0ca4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts new file mode 100644 index 000000000000..a23d11ca0eb6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3399-nanopi-r4s.dts" + +/ { + model = "FriendlyElec NanoPi R4S Enterprise Edition"; + compatible = "friendlyarm,nanopi-r4s-enterprise", "rockchip,rk3399"; +}; + +&gmac { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; +}; + +&i2c2 { + eeprom@51 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + size = <256>; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@fa { + reg = <0xfa 0x06>; + }; + }; +}; From d99efdaba9027bf70a4f78f42c0ddc0639e0918d Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Tue, 20 Sep 2022 16:34:46 +0200 Subject: [PATCH 09/19] arm64: dts: rockchip: Enable HDMI and GPU on quartz64-b This enables the GPU and HDMI output (including HDMI audio) on the PINE64 Quartz64 Model B single board computer. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20220920143446.633956-1-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3566-quartz64-b.dts | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts index 1f709e5d8a87..c3f38ecd1d3d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -4,6 +4,7 @@ #include #include +#include #include "rk3566.dtsi" / { @@ -28,6 +29,17 @@ gmac1_clkin: external-gmac1-clock { #clock-cells = <0>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -183,6 +195,33 @@ &gmac1m1_clkinout status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -456,6 +495,10 @@ &i2c5 { status = "disabled"; }; +&i2s0_8ch { + status = "okay"; +}; + &i2s1_8ch { pinctrl-names = "default"; pinctrl-0 = <&i2s1m0_sclktx @@ -677,3 +720,20 @@ &usb_host0_ehci { &usb_host0_ohci { status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From e18d9b093006d8abd53e1ce13c0d5a8d0fcd5f64 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 19 Sep 2022 11:46:16 -0500 Subject: [PATCH 10/19] arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x This adds the DSI controller nodes and DSI-DPHY controller nodes to the rk356x device tree. Signed-off-by: Chris Morgan Acked-by: Michael Riesch Link: https://lore.kernel.org/r/20220919164616.12492-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 80 ++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index fd903e697aa2..164708f1eb67 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -739,6 +739,62 @@ vop_mmu: iommu@fe043e00 { status = "disabled"; }; + dsi0: dsi@fe060000 { + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x00 0xfe060000 0x00 0x10000>; + interrupts = ; + clock-names = "pclk", "hclk"; + clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; + phy-names = "dphy"; + phys = <&dsi_dphy0>; + power-domains = <&power RK3568_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_P_DSITX_0>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in: port@0 { + reg = <0>; + }; + + dsi0_out: port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi@fe070000 { + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xfe070000 0x0 0x10000>; + interrupts = ; + clock-names = "pclk", "hclk"; + clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; + phy-names = "dphy"; + phys = <&dsi_dphy1>; + power-domains = <&power RK3568_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_P_DSITX_1>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + }; + + dsi1_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi: hdmi@fe0a0000 { compatible = "rockchip,rk3568-dw-hdmi"; reg = <0x0 0xfe0a0000 0x0 0x20000>; @@ -1646,6 +1702,30 @@ csi_dphy: phy@fe870000 { status = "disabled"; }; + dsi_dphy0: mipi-dphy@fe850000 { + compatible = "rockchip,rk3568-dsi-dphy"; + reg = <0x0 0xfe850000 0x0 0x10000>; + clock-names = "ref", "pclk"; + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; + #phy-cells = <0>; + power-domains = <&power RK3568_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_P_MIPIDSIPHY0>; + status = "disabled"; + }; + + dsi_dphy1: mipi-dphy@fe860000 { + compatible = "rockchip,rk3568-dsi-dphy"; + reg = <0x0 0xfe860000 0x0 0x10000>; + clock-names = "ref", "pclk"; + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; + #phy-cells = <0>; + power-domains = <&power RK3568_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_P_MIPIDSIPHY1>; + status = "disabled"; + }; + usb2phy0: usb2phy@fe8a0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x0 0xfe8a0000 0x0 0x10000>; From 110a1f0eea148a4c444e2327483e0e765d26704e Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 9 Sep 2022 19:50:01 +0000 Subject: [PATCH 11/19] arm64: dts: rockchip: connect vcca_1v8 to APIO5_VDD on rk3399-rock-4c-plus GPIO pins for LEDs on ROCK 4C+ are in APIO5 Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20220909195006.127957-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index 3f01772c66ad..d7051b5d4904 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -427,6 +427,7 @@ &i2s2 { &io_domains { bt656-supply = <&vcc_3v0>; + audio-supply = <&vcca_1v8>; gpio1830-supply = <&vcc_3v0>; sdmmc-supply = <&vccio_sd>; status = "okay"; From a088c855acb85ab52fdbffd9b3473f6c9a3f0b35 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 9 Sep 2022 19:50:02 +0000 Subject: [PATCH 12/19] arm64: dts: rockchip: fix regulator structure on rk3399-rock-4c-plus fix regulator name. also, add vcc_3v3 and vdd_log. ref: https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4c_plus_v12_sch_220304.pdf Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20220909195006.127957-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-rock-4c-plus.dts | 83 ++++++++++++------- 1 file changed, 52 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index d7051b5d4904..c88a7512e296 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -61,6 +61,16 @@ led-1 { }; }; + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -94,13 +104,24 @@ vcc5v0_typec: vcc5v0-typec-regulator { vin-supply = <&vcc5v0_sys>; }; - vcc_lan: vcc3v3-phy-regulator { + vcc3v3_phy1: vcc3v3-phy1-regulator { compatible = "regulator-fixed"; - regulator-name = "vcc_lan"; + regulator-name = "vcc3v3_phy1"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vdd_log: vdd-log-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + vin-supply = <&vcc5v0_sys>; }; }; @@ -136,7 +157,7 @@ &gmac { assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; clock_in_out = "input"; - phy-supply = <&vcc_lan>; + phy-supply = <&vcc3v3_phy1>; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; @@ -186,20 +207,20 @@ rk809: pmic@20 { vcc2-supply = <&vcc5v0_sys>; vcc3-supply = <&vcc5v0_sys>; vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc_buck5>; - vcc6-supply = <&vcc_buck5>; + vcc5-supply = <&vcc_buck5_s3>; + vcc6-supply = <&vcc_buck5_s3>; vcc7-supply = <&vcc5v0_sys>; vcc8-supply = <&vcc3v3_sys>; vcc9-supply = <&vcc5v0_sys>; regulators { - vdd_log: DCDC_REG1 { + vdd_center: DCDC_REG1 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1350000>; regulator-initial-mode = <0x2>; - regulator-name = "vdd_log"; + regulator-name = "vdd_center"; regulator-state-mem { regulator-off-in-suspend; regulator-suspend-microvolt = <900000>; @@ -242,59 +263,59 @@ regulator-state-mem { }; }; - vcc_buck5: DCDC_REG5 { + vcc_buck5_s3: DCDC_REG5 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc_buck5"; + regulator-name = "vcc_buck5_s3"; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3300000>; }; }; - vcca_0v9: LDO_REG1 { + vcc_0v9_s3: LDO_REG1 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; - regulator-name = "vcca_0v9"; + regulator-name = "vcc_0v9_s3"; regulator-state-mem { regulator-off-in-suspend; }; }; - vcc_1v8: LDO_REG2 { + vcc_1v8_s3: LDO_REG2 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; + regulator-name = "vcc_1v8_s3"; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; - vcc0v9_soc: LDO_REG3 { + vcc_0v9_s0: LDO_REG3 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; - regulator-name = "vcc0v9_soc"; + regulator-name = "vcc_0v9_s0"; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <900000>; }; }; - vcca_1v8: LDO_REG4 { + vcc_1v8_s0: LDO_REG4 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcca_1v8"; + regulator-name = "vcc_1v8_s0"; regulator-state-mem { regulator-off-in-suspend; }; @@ -311,34 +332,34 @@ regulator-state-mem { }; }; - vcc_1v5: LDO_REG6 { + vcc_1v5_s0: LDO_REG6 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; - regulator-name = "vcc_1v5"; + regulator-name = "vcc_1v5_s0"; regulator-state-mem { regulator-off-in-suspend; }; }; - vcc_3v0: LDO_REG7 { + vcc_3v0_s0: LDO_REG7 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - regulator-name = "vcc_3v0"; + regulator-name = "vcc_3v0_s0"; regulator-state-mem { regulator-off-in-suspend; }; }; - vccio_sd: LDO_REG8 { + vcc_sdio_s0: LDO_REG8 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; + regulator-name = "vcc_sdio_s0"; regulator-state-mem { regulator-off-in-suspend; }; @@ -426,10 +447,10 @@ &i2s2 { }; &io_domains { - bt656-supply = <&vcc_3v0>; - audio-supply = <&vcca_1v8>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vccio_sd>; + bt656-supply = <&vcc_3v0_s0>; + audio-supply = <&vcc_1v8_s0>; + gpio1830-supply = <&vcc_3v0_s0>; + sdmmc-supply = <&vcc_sdio_s0>; status = "okay"; }; @@ -513,13 +534,13 @@ wifi_host_wake_l: wifi-host-wake-l { }; &pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; + pmu1830-supply = <&vcc_3v0_s0>; status = "okay"; }; &saradc { status = "okay"; - vref-supply = <&vcc_1v8>; + vref-supply = <&vcc_1v8_s3>; }; &sdhci { @@ -566,7 +587,7 @@ &sdmmc { pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vccio_sd>; + vqmmc-supply = <&vcc_sdio_s0>; status = "okay"; }; @@ -620,7 +641,7 @@ bluetooth { pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; + vddio-supply = <&vcc_1v8_s3>; }; }; From b153f26d2c557ca49b5f98d256b3e44bc37244cd Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 9 Sep 2022 19:50:03 +0000 Subject: [PATCH 13/19] arm64: dts: rockchip: sort nodes/properties on rk3399-rock-4c-plus sort nodes/properties alphabetically Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20220909195006.127957-3-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-rock-4c-plus.dts | 48 +++++++++---------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index c88a7512e296..fdee9d7b2372 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -23,15 +23,6 @@ chosen { stdout-path = "serial2:1500000n8"; }; - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -61,6 +52,15 @@ led-1 { }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + vcc_3v3: vcc-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_3v3"; @@ -71,13 +71,14 @@ vcc_3v3: vcc-3v3-regulator { vin-supply = <&vcc3v3_sys>; }; - vcc5v0_sys: vcc5v0-sys-regulator { + vcc3v3_phy1: vcc3v3-phy1-regulator { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; + regulator-name = "vcc3v3_phy1"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; }; vcc5v0_host1: vcc5v0-host-regulator { @@ -92,6 +93,15 @@ vcc5v0_host1: vcc5v0-host-regulator { vin-supply = <&vcc5v0_host0_s0>; }; + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + vcc5v0_typec: vcc5v0-typec-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -104,16 +114,6 @@ vcc5v0_typec: vcc5v0-typec-regulator { vin-supply = <&vcc5v0_sys>; }; - vcc3v3_phy1: vcc3v3-phy1-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_phy1"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3>; - }; - vdd_log: vdd-log-regulator { compatible = "regulator-fixed"; regulator-name = "vdd_log"; @@ -447,8 +447,8 @@ &i2s2 { }; &io_domains { - bt656-supply = <&vcc_3v0_s0>; audio-supply = <&vcc_1v8_s0>; + bt656-supply = <&vcc_3v0_s0>; gpio1830-supply = <&vcc_3v0_s0>; sdmmc-supply = <&vcc_sdio_s0>; status = "okay"; From 69448624b770aa88a71536a16900dd3cc6002919 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 9 Sep 2022 19:50:04 +0000 Subject: [PATCH 14/19] arm64: dts: rockchip: fix regulator name on rk3399-rock-4 fix regulator name ref: https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4_v13_sch_20181112.pdf Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20220909195006.127957-4-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 25 ++++++++++--------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 6464a6729729..bb1dcf319b02 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -136,24 +136,25 @@ vcc5v0_host: vcc5v0-host-regulator { vin-supply = <&vcc5v0_sys>; }; - vcc5v0_typec: vcc5v0-typec-regulator { + vbus_typec: vbus-typec-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; + regulator-name = "vbus_typec"; regulator-always-on; vin-supply = <&vcc5v0_sys>; }; - vcc_lan: vcc3v3-phy-regulator { + vcc3v3_lan: vcc3v3-lan-regulator { compatible = "regulator-fixed"; - regulator-name = "vcc_lan"; + regulator-name = "vcc3v3_lan"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; }; vdd_log: vdd-log { @@ -200,7 +201,7 @@ &gmac { assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; clock_in_out = "input"; - phy-supply = <&vcc_lan>; + phy-supply = <&vcc3v3_lan>; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; @@ -305,8 +306,8 @@ regulator-state-mem { }; }; - vcc1v8_codec: LDO_REG1 { - regulator-name = "vcc1v8_codec"; + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; @@ -316,8 +317,8 @@ regulator-state-mem { }; }; - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; @@ -374,8 +375,8 @@ regulator-state-mem { }; }; - vcc0v9_hdmi: LDO_REG7 { - regulator-name = "vcc0v9_hdmi"; + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <900000>; @@ -517,7 +518,7 @@ &io_domains { status = "okay"; bt656-supply = <&vcc_3v0>; - audio-supply = <&vcc1v8_codec>; + audio-supply = <&vcca1v8_codec>; sdmmc-supply = <&vcc_sdio>; gpio1830-supply = <&vcc_3v0>; }; From 06c5b5690a578514b3fe8f11a47a3c37d3af3696 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 9 Sep 2022 19:50:05 +0000 Subject: [PATCH 15/19] arm64: dts: rockchip: sort nodes/properties on rk3399-rock-4 sort nodes/properties alphabetically Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20220909195006.127957-5-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 134 +++++++++--------- 1 file changed, 66 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index bb1dcf319b02..485277f7ed17 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -74,6 +74,17 @@ dit_p0_0: endpoint { }; }; + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vbus_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + vcc12v_dcin: dc-12v { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -83,23 +94,13 @@ vcc12v_dcin: dc-12v { regulator-max-microvolt = <12000000>; }; - vcc5v0_sys: vcc-sys { + vcc3v3_lan: vcc3v3-lan-regulator { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; + regulator-name = "vcc3v3_lan"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; vin-supply = <&vcc3v3_sys>; }; @@ -136,24 +137,23 @@ vcc5v0_host: vcc5v0-host-regulator { vin-supply = <&vcc5v0_sys>; }; - vbus_typec: vbus-typec-regulator { + vcc5v0_sys: vcc-sys { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vbus_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_lan: vcc3v3-lan-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lan"; + regulator-name = "vcc5v0_sys"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; vin-supply = <&vcc3v3_sys>; }; @@ -515,21 +515,10 @@ &i2s2 { }; &io_domains { - status = "okay"; - - bt656-supply = <&vcc_3v0>; audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; + bt656-supply = <&vcc_3v0>; gpio1830-supply = <&vcc_3v0>; -}; - -&pmu_io_domains { - status = "okay"; - - pmu1830-supply = <&vcc_3v0>; -}; - -&pcie_phy { + sdmmc-supply = <&vcc_sdio>; status = "okay"; }; @@ -544,6 +533,10 @@ &pcie0 { status = "okay"; }; +&pcie_phy { + status = "okay"; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -581,6 +574,20 @@ pcie_pwr_en: pcie-pwr-en { }; }; + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + sdio0 { sdio0_bus4: sdio0-bus4 { rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, @@ -598,20 +605,6 @@ sdio0_clk: sdio0-clk { }; }; - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - usb-typec { vcc5v0_typec_en: vcc5v0-typec-en { rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; @@ -635,6 +628,11 @@ wifi_host_wake_l: wifi-host-wake-l { }; }; +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + &pwm2 { status = "okay"; }; @@ -645,6 +643,14 @@ &saradc { vref-supply = <&vcc_1v8>; }; +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + &sdio0 { #address-cells = <1>; #size-cells = <0>; @@ -672,14 +678,6 @@ &sdmmc { status = "okay"; }; -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - &spdif { spdif_p0: port { @@ -761,15 +759,15 @@ &usbdrd3_0 { status = "okay"; }; +&usbdrd3_1 { + status = "okay"; +}; + &usbdrd_dwc3_0 { status = "okay"; dr_mode = "host"; }; -&usbdrd3_1 { - status = "okay"; -}; - &usbdrd_dwc3_1 { status = "okay"; dr_mode = "host"; From b6047ba2caaca41da8706c66c55f7b34e0714e21 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 9 Sep 2022 19:50:06 +0000 Subject: [PATCH 16/19] arm64: dts: rockchip: add avdd-0v9-supply and avdd-1v8-supply on rk3399 rock 4c and pi4 this patch adds avdd-0v9-supply and avdd-1v8-supply to hdmi node for Radxa ROCK 4 series. Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20220909195006.127957-6-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index fdee9d7b2372..f9884902f874 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -175,6 +175,8 @@ &gpu { }; &hdmi { + avdd-0v9-supply = <&vcc_0v9_s0>; + avdd-1v8-supply = <&vcc_1v8_s0>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 485277f7ed17..645ced6617a6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -219,6 +219,8 @@ &gpu { }; &hdmi { + avdd-0v9-supply = <&vcca0v9_hdmi>; + avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; From 8cde9667137f2ca8def8aef518305a78e5f55279 Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Mon, 20 Jun 2022 18:13:18 +0200 Subject: [PATCH 17/19] arm64: dts: rockchip: set max drive-strength for cif_clkout_m0 on px30-evb Add max drive-strength for cif_clkout_m0. This fix the issue that sometimes camera ov5695 is not probed correctly. Tested on PX30_Mini_EVB_V11_20190507 Signed-off-by: Tommaso Merciai Link: https://lore.kernel.org/r/20220620161321.1898840-2-tommaso.merciai@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-evb.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index 848bc39cf86a..53930e28eadf 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -537,6 +537,13 @@ wifi_enable_h: wifi-enable-h { <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + cif-m0 { + cif_clkout_m0: cif-clkout-m0 { + rockchip,pins = + <2 RK_PB3 1 &pcfg_pull_none_12ma>; + }; + }; }; &pmu_io_domains { From 921890cae252ed7b7e4d9f98f63515c25cc0aede Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Mon, 20 Jun 2022 18:13:19 +0200 Subject: [PATCH 18/19] arm64: dts: rockchip: add pinctrl for mipi-pdn pin on px30-evb Add right mux for mipi-pdn. Mux this pad as gpio2 14 Signed-off-by: Tommaso Merciai Link: https://lore.kernel.org/r/20220620161321.1898840-3-tommaso.merciai@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-evb.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index 53930e28eadf..0d05a1b098bc 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -450,8 +450,8 @@ ov5695: ov5695@36 { dvdd-supply = <&vcc1v5_dvp>; dovdd-supply = <&vcc1v8_dvp>; pinctrl-names = "default"; - pinctrl-0 = <&cif_clkout_m0>; reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cif_clkout_m0 &mipi_pdn>; port { ucam_out: endpoint { @@ -544,6 +544,12 @@ cif_clkout_m0: cif-clkout-m0 { <2 RK_PB3 1 &pcfg_pull_none_12ma>; }; }; + + mipi { + mipi_pdn: mipi-pdn { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pmu_io_domains { From 19d4aaf640913c5a8f1b06c9ef46287c32635299 Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Mon, 20 Jun 2022 18:13:20 +0200 Subject: [PATCH 19/19] arm64: dts: rockchip: use pin constant for reset-gpios on px30-evb Use rk gpio naming convention into reset-gpios of ov5695 camera Signed-off-by: Tommaso Merciai Link: https://lore.kernel.org/r/20220620161321.1898840-4-tommaso.merciai@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-evb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts index 0d05a1b098bc..07008d84434c 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts @@ -450,8 +450,8 @@ ov5695: ov5695@36 { dvdd-supply = <&vcc1v5_dvp>; dovdd-supply = <&vcc1v8_dvp>; pinctrl-names = "default"; - reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; pinctrl-0 = <&cif_clkout_m0 &mipi_pdn>; + reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; port { ucam_out: endpoint {