github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-25 23:52:08 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

net: ag71xx: update FIFO bits and descriptions

Browse Source 
Taken from QCA SDK. No functional difference as same bits get applied.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Link: https://patch.msgid.link/20240905194938.8453-4-rosenp@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Rosen Penev 2024-09-05 12:49:34 -07:00 committed by Jakub Kicinski
parent 7c3736a129
commit 2854085057
1 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
drivers/net/ethernet/atheros/ag71xx.c
View File

@ -149,11 +149,11 @@
#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
#define FIFO_CFG4_DR BIT(10) /* Dribble */
#define FIFO_CFG4_LE BIT(11) /* Long Event */
#define FIFO_CFG4_CF BIT(12) /* Control Frame */
#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
#define FIFO_CFG4_CF BIT(11) /* Control Frame */
#define FIFO_CFG4_PF BIT(12) /* Pause Frame */
#define FIFO_CFG4_UO BIT(13) /* Unsupported Opcode */
#define FIFO_CFG4_VT BIT(14) /* VLAN tag detected */
#define FIFO_CFG4_LE BIT(15) /* Long Event */
#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
@ -168,28 +168,28 @@
#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
#define FIFO_CFG5_FC BIT(2) /* False Carrier */
#define FIFO_CFG5_CE BIT(3) /* Code Error */
#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
#define FIFO_CFG5_DR BIT(9) /* Dribble */
#define FIFO_CFG5_CF BIT(10) /* Control Frame */
#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
#define FIFO_CFG5_LE BIT(14) /* Long Event */
#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
#define FIFO_CFG5_16 BIT(16) /* unknown */
#define FIFO_CFG5_17 BIT(17) /* unknown */
#define FIFO_CFG5_CR BIT(4) /* CRC error */
#define FIFO_CFG5_LM BIT(5) /* Length Mismatch */
#define FIFO_CFG5_LO BIT(6) /* Length Out of Range */
#define FIFO_CFG5_OK BIT(7) /* Packet is OK */
#define FIFO_CFG5_MC BIT(8) /* Multicast Packet */
#define FIFO_CFG5_BC BIT(9) /* Broadcast Packet */
#define FIFO_CFG5_DR BIT(10) /* Dribble */
#define FIFO_CFG5_CF BIT(11) /* Control Frame */
#define FIFO_CFG5_PF BIT(12) /* Pause Frame */
#define FIFO_CFG5_UO BIT(13) /* Unsupported Opcode */
#define FIFO_CFG5_VT BIT(14) /* VLAN tag detected */
#define FIFO_CFG5_LE BIT(15) /* Long Event */
#define FIFO_CFG5_FT BIT(16) /* Frame Truncated */
#define FIFO_CFG5_UC BIT(17) /* Unicast Packet */
#define FIFO_CFG5_SF BIT(18) /* Short Frame */
#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
FIFO_CFG5_17 | FIFO_CFG5_SF)
FIFO_CFG5_CE | FIFO_CFG5_LM | FIFO_CFG5_LO | \
FIFO_CFG5_OK | FIFO_CFG5_MC | FIFO_CFG5_BC | \
FIFO_CFG5_DR | FIFO_CFG5_CF | FIFO_CFG5_UO | \
FIFO_CFG5_VT | FIFO_CFG5_LE | FIFO_CFG5_FT | \
FIFO_CFG5_UC | FIFO_CFG5_SF)
#define AG71XX_REG_TX_CTRL 0x0180
#define TX_CTRL_TXE BIT(0) /* Tx Enable */