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Qualcomm clock updates for v6.9

Browse Source 
This introduces support for Display, TCSR, GPU, and Camera clock
 controllers for X1 Elite.
 
 A number of typos are fixes in the IPQ5018 GCC driver. IPQ6018 gains a
 definition of the "qdss_at" clock, which is needed for WiFi operation.
 
 Table termination is added where missing across a range of frequency
 tables in different drivers.
 
 MSM8953 gains support for missing MDSS, crypto, and SDCC resets, and the
 missing CLKREF clocks for UFS in SC8180X are added.
 
 A softdep on rpmhpd is introduces for SDM845 gcc to assist AOSP with
 module load order, to avoid significant delays during boot.
 
 In the SM8150 GCC driver video resets are added and QUPv3 RCGs are
 registered for DFS.
 
 The support for supplying GDSCs with an external regulator is corrected
 for the custom GPU GX "do-nothing" method. An external supply is then
 specified for GX in the SC8280XP GPU clock controller.
 
 Display, GPU, Video, and Camera clock controller drivers are switched to
 module_platform_driver(), as they are not needed earlier than that.
 
 A variety of Venus resets across many platforms require a longer delay
 than the current 1us, support for larger delays is added and custom
 delays are specified across more than a dozen clock drivers.
 
 The GDSC wait times are corrected for GDSCs in the display clock
 controller for SDM845.
 
 The unused SC7180 modem subsystem clock driver is dropped.
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Merge tag 'qcom-clk-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Support for Display, TCSR, GPU, and Camera clock controllers for
   Qualcomm's X1 Elite SoC
 - Typo fixes in the IPQ5018 GCC driver
 - Add "qdss_at" clk on Qualcomm IPQ6018, needed for WiFi
 - Properly terminate frequency tables in different qcom clk drivers
 - Add MDSS, crypto, and SDCC resets on Qualcomm MSM8953
 - Add missing UFS CLKREF clks on Qualcomm SC8180X
 - Avoid significant delays during boot by adding a softdep on rpmhpd to SDM845 gcc driver
 - Add QUPv3 RCGS w/ DFS and video resets to Qualcomm SM8150 GCC driver
 - Fix the custom GPU GX "do-nothing" method in the GDSC driver
 - Add an external regulator to GX GDSC on SC8280XP GPU clk driver
 - Switch display, GPU, video, and camera clock drivers to module_platform_driver()
 - Set a longer delay for Venus resets on many Qualcomm SoCs
 - Correct the GDSC wait times in the Qualcomm SDM845 display clk driver
 - Remove the unused Qualcomm sc7180 modem clk driver

* tag 'qcom-clk-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (62 commits)
  clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset
  clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk'
  clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk'
  clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc
  clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays
  clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays
  clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays
  clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times
  dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controller
  clk: qcom: drop the SC7180 Modem subsystem clock driver
  clk: qcom: Use qcom_branch_set_clk_en()
  clk: qcom: branch: Add a helper for setting the enable bit
  clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco const
  clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks
  clk: qcom: gcc-msm8953: add more resets
  clk: qcom: videocc-*: switch to module_platform_driver
  ...
This commit is contained in:
Stephen Boyd 2024-03-08 15:27:48 -08:00
commit 27ec6a1919
92 changed files with 6176 additions and 1198 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
View File

@ -53,6 +53,9 @@ properties:
power-domains:
maxItems: 1
vdd-gfx-supply:
description: Regulator supply for the VDD_GFX pads
'#clock-cells':
const: 1
@ -74,6 +77,12 @@ required:
- '#reset-cells'
- '#power-domain-cells'
# Require that power-domains and vdd-gfx-supply are not both present
not:
required:
- power-domains
- vdd-gfx-supply
additionalProperties: false
examples:

2
Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Q6SSTOP clock Controller
maintainers:
- Govind Singh <govinds@codeaurora.org>
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:

61
Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml
View File

@ -1,61 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Modem Clock Controller on SC7180
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm modem clock control module provides the clocks on SC7180.
See also:: include/dt-bindings/clock/qcom,mss-sc7180.h
properties:
compatible:
const: qcom,sc7180-mss
clocks:
items:
- description: gcc_mss_mfab_axi clock from GCC
- description: gcc_mss_nav_axi clock from GCC
- description: gcc_mss_cfg_ahb clock from GCC
clock-names:
items:
- const: gcc_mss_mfab_axis
- const: gcc_mss_nav_axi
- const: cfg_ahb
'#clock-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
clock-controller@41a8000 {
compatible = "qcom,sc7180-mss";
reg = <0x041a8000 0x8000>;
clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>,
<&gcc GCC_MSS_NAV_AXI_CLK>,
<&gcc GCC_MSS_CFG_AHB_CLK>;
clock-names = "gcc_mss_mfab_axis",
"gcc_mss_nav_axi",
"cfg_ahb";
#clock-cells = <1>;
};
...

2
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -17,6 +17,7 @@ description: |
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
@ -27,6 +28,7 @@ properties:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
- qcom,x1e80100-camcc
clocks:
items:

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -18,6 +18,7 @@ description: |
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
properties:
compatible:
@ -25,6 +26,7 @@ properties:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
- qcom,x1e80100-gpucc
clocks:
items:

7
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@ -14,12 +14,17 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8550.
See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
See also:
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
properties:
compatible:
enum:
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc
- qcom,x1e80100-dispcc
clocks:
items:

1
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -23,6 +23,7 @@ properties:
- enum:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,x1e80100-tcsr
- const: syscon
clocks:

106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
View File

@ -1,106 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8650.
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
properties:
compatible:
enum:
- qcom,sm8650-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8650-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

45
drivers/clk/qcom/Kconfig
View File

@ -20,6 +20,24 @@ menuconfig COMMON_CLK_QCOM
if COMMON_CLK_QCOM
config CLK_X1E80100_CAMCC
tristate "X1E80100 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_X1E80100_GCC
help
Support for the camera clock controller on X1E80100 devices.
Say Y if you want to support camera devices and camera functionality.
config CLK_X1E80100_DISPCC
tristate "X1E80100 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_X1E80100_GCC
help
Support for the two display clock controllers on Qualcomm
Technologies, Inc. X1E80100 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config CLK_X1E80100_GCC
tristate "X1E80100 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -30,6 +48,23 @@ config CLK_X1E80100_GCC
Say Y if you want to use peripheral devices such as UART, SPI, I2C,
USB, UFS, SD/eMMC, PCIe, etc.
config CLK_X1E80100_GPUCC
tristate "X1E80100 Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_X1E80100_GCC
help
Support for the graphics clock controller on X1E80100 devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config CLK_X1E80100_TCSRCC
tristate "X1E80100 TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the TCSR clock controller on X1E80100 devices.
Say Y if you want to use peripheral devices such as SD/UFS.
config QCOM_A53PLL
tristate "MSM8916 A53 PLL"
help
@ -600,16 +635,6 @@ config SC_LPASS_CORECC_7280
Say Y if you want to use LPASS clocks and power domains of the LPASS
core clock controller.
config SC_MSS_7180
tristate "SC7180 Modem Clock Controller"
depends on ARM64 || COMPILE_TEST
select SC_GCC_7180
help
Support for the Modem Subsystem clock controller on Qualcomm
Technologies, Inc on SC7180 devices.
Say Y if you want to use the Modem branch clocks of the Modem
subsystem clock controller to reset the MSS subsystem.
config SC_VIDEOCC_7180
tristate "SC7180 Video Clock Controller"
depends on ARM64 || COMPILE_TEST

5
drivers/clk/qcom/Makefile
View File

@ -21,7 +21,11 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
@ -87,7 +91,6 @@ obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o
obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o
obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o
obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o
obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o
obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o

12
drivers/clk/qcom/camcc-sc7180.c
View File

@ -1703,17 +1703,7 @@ static struct platform_driver cam_cc_sc7180_driver = {
},
};
static int __init cam_cc_sc7180_init(void)
{
return platform_driver_register(&cam_cc_sc7180_driver);
}
subsys_initcall(cam_cc_sc7180_init);
static void __exit cam_cc_sc7180_exit(void)
{
platform_driver_unregister(&cam_cc_sc7180_driver);
}
module_exit(cam_cc_sc7180_exit);
module_platform_driver(cam_cc_sc7180_driver);
MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/camcc-sc7280.c
View File

@ -2468,17 +2468,7 @@ static struct platform_driver cam_cc_sc7280_driver = {
},
};
static int __init cam_cc_sc7280_init(void)
{
return platform_driver_register(&cam_cc_sc7280_driver);
}
subsys_initcall(cam_cc_sc7280_init);
static void __exit cam_cc_sc7280_exit(void)
{
platform_driver_unregister(&cam_cc_sc7280_driver);
}
module_exit(cam_cc_sc7280_exit);
module_platform_driver(cam_cc_sc7280_driver);
MODULE_DESCRIPTION("QTI CAM_CC SC7280 Driver");
MODULE_LICENSE("GPL v2");

27
drivers/clk/qcom/camcc-sc8280xp.c
View File

@ -630,6 +630,7 @@ static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {
F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_bps_clk_src = {
@ -654,6 +655,7 @@ static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = {
F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_camnoc_axi_clk_src = {
@ -673,6 +675,7 @@ static struct clk_rcg2 camcc_camnoc_axi_clk_src = {
static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
{ }
};
static struct clk_rcg2 camcc_cci_0_clk_src = {
@ -735,6 +738,7 @@ static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(240000000, P_CAMCC_PLL0_OUT_EVEN, 2.5, 0, 0),
F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_cphy_rx_clk_src = {
@ -754,6 +758,7 @@ static struct clk_rcg2 camcc_cphy_rx_clk_src = {
static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 camcc_csi0phytimer_clk_src = {
@ -818,6 +823,7 @@ static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {
F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 camcc_fast_ahb_clk_src = {
@ -838,6 +844,7 @@ static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 camcc_icp_clk_src = {
@ -860,6 +867,7 @@ static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {
F(558000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_0_clk_src = {
@ -883,6 +891,7 @@ static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = {
F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_0_csid_clk_src = {
@ -905,6 +914,7 @@ static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = {
F(558000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_1_clk_src = {
@ -941,6 +951,7 @@ static const struct freq_tbl ftbl_camcc_ife_2_clk_src[] = {
F(558000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
F(637000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
F(760000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_2_clk_src = {
@ -962,6 +973,7 @@ static const struct freq_tbl ftbl_camcc_ife_2_csid_clk_src[] = {
F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_2_csid_clk_src = {
@ -984,6 +996,7 @@ static const struct freq_tbl ftbl_camcc_ife_3_clk_src[] = {
F(558000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
F(637000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
F(760000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_3_clk_src = {
@ -1020,6 +1033,7 @@ static const struct freq_tbl ftbl_camcc_ife_lite_0_clk_src[] = {
F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_lite_0_clk_src = {
@ -1140,6 +1154,7 @@ static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {
F(475000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ipe_0_clk_src = {
@ -1163,6 +1178,7 @@ static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = {
F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 camcc_jpeg_clk_src = {
@ -1184,6 +1200,7 @@ static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {
F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 camcc_lrme_clk_src = {
@ -1204,6 +1221,7 @@ static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4),
F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
{ }
};
static struct clk_rcg2 camcc_mclk0_clk_src = {
@ -1320,6 +1338,7 @@ static struct clk_rcg2 camcc_mclk7_clk_src = {
static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_sleep_clk_src = {
@ -1339,6 +1358,7 @@ static struct clk_rcg2 camcc_sleep_clk_src = {
static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(80000000, P_CAMCC_PLL7_OUT_EVEN, 6, 0, 0),
{ }
};
static struct clk_rcg2 camcc_slow_ahb_clk_src = {
@ -1357,6 +1377,7 @@ static struct clk_rcg2 camcc_slow_ahb_clk_src = {
static const struct freq_tbl ftbl_camcc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_xo_clk_src = {
@ -3010,10 +3031,8 @@ static int camcc_sc8280xp_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config);
clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config);
/*
* Keep camcc_gdsc_clk always enabled:
*/
regmap_update_bits(regmap, 0xc1e4, BIT(0), 1);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */
ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap);
if (ret)

12
drivers/clk/qcom/camcc-sdm845.c
View File

@ -1746,17 +1746,7 @@ static struct platform_driver cam_cc_sdm845_driver = {
},
};
static int __init cam_cc_sdm845_init(void)
{
return platform_driver_register(&cam_cc_sdm845_driver);
}
subsys_initcall(cam_cc_sdm845_init);
static void __exit cam_cc_sdm845_exit(void)
{
platform_driver_unregister(&cam_cc_sdm845_driver);
}
module_exit(cam_cc_sdm845_exit);
module_platform_driver(cam_cc_sdm845_driver);
MODULE_DESCRIPTION("QTI CAM_CC SDM845 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/camcc-sm6350.c
View File

@ -1890,17 +1890,7 @@ static struct platform_driver camcc_sm6350_driver = {
},
};
static int __init camcc_sm6350_init(void)
{
return platform_driver_register(&camcc_sm6350_driver);
}
subsys_initcall(camcc_sm6350_init);
static void __exit camcc_sm6350_exit(void)
{
platform_driver_unregister(&camcc_sm6350_driver);
}
module_exit(camcc_sm6350_exit);
module_platform_driver(camcc_sm6350_driver);
MODULE_DESCRIPTION("QTI CAMCC SM6350 Driver");
MODULE_LICENSE("GPL");

10
drivers/clk/qcom/camcc-sm8550.c
View File

@ -3536,13 +3536,9 @@ static int cam_cc_sm8550_probe(struct platform_device *pdev)
clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config);
clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config);
/*
* Keep clocks always enabled:
* cam_cc_gdsc_clk
* cam_cc_sleep_clk
*/
regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */
ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap);

2487
drivers/clk/qcom/camcc-x1e80100.c Normal file
View File

File diff suppressed because it is too large Load Diff

16
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -52,6 +52,7 @@
#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
#define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
@ -228,6 +229,21 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_ALPHA_VAL] = 0x24,
[PLL_OFF_ALPHA_VAL_U] = 0x28,
},
[CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_USER_CTL_U] = 0x10,
[PLL_OFF_CONFIG_CTL] = 0x14,
[PLL_OFF_CONFIG_CTL_U] = 0x18,
[PLL_OFF_CONFIG_CTL_U1] = 0x1c,
[PLL_OFF_CONFIG_CTL_U2] = 0x20,
[PLL_OFF_TEST_CTL] = 0x24,
[PLL_OFF_TEST_CTL_U] = 0x28,
[PLL_OFF_TEST_CTL_U1] = 0x2c,
[PLL_OFF_OPMODE] = 0x30,
[PLL_OFF_STATUS] = 0x3c,
},
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);

4
drivers/clk/qcom/clk-alpha-pll.h
View File

@ -21,6 +21,7 @@ enum {
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_AGERA,
CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_LUCID_OLE,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
@ -42,6 +43,7 @@ enum {
PLL_OFF_CONFIG_CTL,
PLL_OFF_CONFIG_CTL_U,
PLL_OFF_CONFIG_CTL_U1,
PLL_OFF_CONFIG_CTL_U2,
PLL_OFF_TEST_CTL,
PLL_OFF_TEST_CTL_U,
PLL_OFF_TEST_CTL_U1,
@ -119,6 +121,7 @@ struct alpha_pll_config {
u32 config_ctl_val;
u32 config_ctl_hi_val;
u32 config_ctl_hi1_val;
u32 config_ctl_hi2_val;
u32 user_ctl_val;
u32 user_ctl_hi_val;
u32 user_ctl_hi1_val;
@ -173,6 +176,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_zonda_ops;
#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
#define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;

6
drivers/clk/qcom/clk-branch.h
View File

@ -64,6 +64,7 @@ struct clk_mem_branch {
#define CBCR_FORCE_MEM_PERIPH_OFF BIT(12)
#define CBCR_WAKEUP GENMASK(11, 8)
#define CBCR_SLEEP GENMASK(7, 4)
#define CBCR_CLOCK_ENABLE BIT(0)
static inline void qcom_branch_set_force_mem_core(struct regmap *regmap,
struct clk_branch clk, bool on)
@ -98,6 +99,11 @@ static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branc
FIELD_PREP(CBCR_SLEEP, val));
}
static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr)
{
regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, CBCR_CLOCK_ENABLE);
}
extern const struct clk_ops clk_branch_ops;
extern const struct clk_ops clk_branch2_ops;
extern const struct clk_ops clk_branch_simple_ops;

16
drivers/clk/qcom/dispcc-qcm2290.c
View File

@ -519,8 +519,8 @@ static int disp_cc_qcm2290_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep DISP_CC_XO_CLK always-ON */
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap);
if (ret) {
@ -539,17 +539,7 @@ static struct platform_driver disp_cc_qcm2290_driver = {
},
};
static int __init disp_cc_qcm2290_init(void)
{
return platform_driver_register(&disp_cc_qcm2290_driver);
}
subsys_initcall(disp_cc_qcm2290_init);
static void __exit disp_cc_qcm2290_exit(void)
{
platform_driver_unregister(&disp_cc_qcm2290_driver);
}
module_exit(disp_cc_qcm2290_exit);
module_platform_driver(disp_cc_qcm2290_driver);
MODULE_DESCRIPTION("QTI DISP_CC qcm2290 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/dispcc-sc7180.c
View File

@ -724,17 +724,7 @@ static struct platform_driver disp_cc_sc7180_driver = {
},
};
static int __init disp_cc_sc7180_init(void)
{
return platform_driver_register(&disp_cc_sc7180_driver);
}
subsys_initcall(disp_cc_sc7180_init);
static void __exit disp_cc_sc7180_exit(void)
{
platform_driver_unregister(&disp_cc_sc7180_driver);
}
module_exit(disp_cc_sc7180_exit);
module_platform_driver(disp_cc_sc7180_driver);
MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
MODULE_LICENSE("GPL v2");

19
drivers/clk/qcom/dispcc-sc7280.c
View File

@ -878,11 +878,8 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/*
* Keep the clocks always-ON
* DISP_CC_XO_CLK
*/
regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */
return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap);
}
@ -895,17 +892,7 @@ static struct platform_driver disp_cc_sc7280_driver = {
},
};
static int __init disp_cc_sc7280_init(void)
{
return platform_driver_register(&disp_cc_sc7280_driver);
}
subsys_initcall(disp_cc_sc7280_init);
static void __exit disp_cc_sc7280_exit(void)
{
platform_driver_unregister(&disp_cc_sc7280_driver);
}
module_exit(disp_cc_sc7280_exit);
module_platform_driver(disp_cc_sc7280_driver);
MODULE_DESCRIPTION("QTI DISP_CC sc7280 Driver");
MODULE_LICENSE("GPL v2");

16
drivers/clk/qcom/dispcc-sc8280xp.c
View File

@ -3178,8 +3178,8 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev)
goto out_pm_runtime_put;
}
/* DISP_CC_XO_CLK always-on */
regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */
out_pm_runtime_put:
pm_runtime_put_sync(&pdev->dev);
@ -3202,17 +3202,7 @@ static struct platform_driver disp_cc_sc8280xp_driver = {
},
};
static int __init disp_cc_sc8280xp_init(void)
{
return platform_driver_register(&disp_cc_sc8280xp_driver);
}
subsys_initcall(disp_cc_sc8280xp_init);
static void __exit disp_cc_sc8280xp_exit(void)
{
platform_driver_unregister(&disp_cc_sc8280xp_driver);
}
module_exit(disp_cc_sc8280xp_exit);
module_platform_driver(disp_cc_sc8280xp_driver);
MODULE_DESCRIPTION("Qualcomm SC8280XP dispcc driver");
MODULE_LICENSE("GPL");

14
drivers/clk/qcom/dispcc-sdm845.c
View File

@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.en_few_wait_val = 0x6,
.en_rest_wait_val = 0x5,
.pd = {
.name = "mdss_gdsc",
},
@ -872,17 +874,7 @@ static struct platform_driver disp_cc_sdm845_driver = {
},
};
static int __init disp_cc_sdm845_init(void)
{
return platform_driver_register(&disp_cc_sdm845_driver);
}
subsys_initcall(disp_cc_sdm845_init);
static void __exit disp_cc_sdm845_exit(void)
{
platform_driver_unregister(&disp_cc_sdm845_driver);
}
module_exit(disp_cc_sdm845_exit);
module_platform_driver(disp_cc_sdm845_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI DISPCC SDM845 Driver");

4
drivers/clk/qcom/dispcc-sm6115.c
View File

@ -583,8 +583,8 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep DISP_CC_XO_CLK always-ON */
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap);
if (ret) {

12
drivers/clk/qcom/dispcc-sm6125.c
View File

@ -693,17 +693,7 @@ static struct platform_driver disp_cc_sm6125_driver = {
},
};
static int __init disp_cc_sm6125_init(void)
{
return platform_driver_register(&disp_cc_sm6125_driver);
}
subsys_initcall(disp_cc_sm6125_init);
static void __exit disp_cc_sm6125_exit(void)
{
platform_driver_unregister(&disp_cc_sm6125_driver);
}
module_exit(disp_cc_sm6125_exit);
module_platform_driver(disp_cc_sm6125_driver);
MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/dispcc-sm6350.c
View File

@ -781,17 +781,7 @@ static struct platform_driver disp_cc_sm6350_driver = {
},
};
static int __init disp_cc_sm6350_init(void)
{
return platform_driver_register(&disp_cc_sm6350_driver);
}
subsys_initcall(disp_cc_sm6350_init);
static void __exit disp_cc_sm6350_exit(void)
{
platform_driver_unregister(&disp_cc_sm6350_driver);
}
module_exit(disp_cc_sm6350_exit);
module_platform_driver(disp_cc_sm6350_driver);
MODULE_DESCRIPTION("QTI DISP_CC SM6350 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/dispcc-sm6375.c
View File

@ -594,17 +594,7 @@ static struct platform_driver disp_cc_sm6375_driver = {
},
};
static int __init disp_cc_sm6375_init(void)
{
return platform_driver_register(&disp_cc_sm6375_driver);
}
subsys_initcall(disp_cc_sm6375_init);
static void __exit disp_cc_sm6375_exit(void)
{
platform_driver_unregister(&disp_cc_sm6375_driver);
}
module_exit(disp_cc_sm6375_exit);
module_platform_driver(disp_cc_sm6375_driver);
MODULE_DESCRIPTION("QTI DISPCC SM6375 Driver");
MODULE_LICENSE("GPL");

134
drivers/clk/qcom/dispcc-sm8250.c
View File

@ -39,11 +39,11 @@ enum {
P_DSI1_PHY_PLL_OUT_DSICLK,
};
static struct pll_vco vco_table[] = {
static const struct pll_vco vco_table[] = {
{ 249600000, 2000000000, 0 },
};
static struct pll_vco lucid_5lpe_vco[] = {
static const struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1750000000, 0 },
};
@ -214,7 +214,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
@ -233,7 +233,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
@ -247,7 +247,7 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
@ -262,7 +262,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_aux1_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@ -277,7 +277,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@ -291,7 +291,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_link1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@ -304,7 +304,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@ -317,7 +317,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_pixel1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@ -330,7 +330,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_pixel2_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@ -343,7 +343,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@ -357,7 +357,7 @@ static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@ -372,7 +372,7 @@ static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_gtc_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
@ -386,7 +386,7 @@ static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_link_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
@ -400,7 +400,7 @@ static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_pixel_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
@ -414,7 +414,7 @@ static struct clk_branch disp_cc_mdss_edp_aux_clk = {
.clkr = {
.enable_reg = 0x2078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_aux_clk_src.clkr.hw,
@ -432,7 +432,7 @@ static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
.clkr = {
.enable_reg = 0x207c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_gtc_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
@ -450,7 +450,7 @@ static struct clk_branch disp_cc_mdss_edp_link_clk = {
.clkr = {
.enable_reg = 0x2070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
@ -466,7 +466,7 @@ static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
.reg = 0x2288,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
@ -482,7 +482,7 @@ static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
.clkr = {
.enable_reg = 0x2074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_div_clk_src.clkr.hw,
@ -500,7 +500,7 @@ static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
.clkr = {
.enable_reg = 0x206c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_edp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
@ -518,7 +518,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
@ -533,7 +533,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
@ -574,7 +574,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
@ -588,7 +588,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
@ -612,7 +612,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
@ -627,7 +627,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@ -640,7 +640,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x2128,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
@ -655,7 +655,7 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
.reg = 0x2144,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte1_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_clk_src.clkr.hw,
@ -665,12 +665,11 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
},
};
static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
.reg = 0x2224,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_link1_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link1_clk_src.clkr.hw,
@ -680,12 +679,11 @@ static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
},
};
static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
.reg = 0x2190,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
@ -701,7 +699,7 @@ static struct clk_branch disp_cc_mdss_ahb_clk = {
.clkr = {
.enable_reg = 0x2080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
@ -719,7 +717,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = {
.clkr = {
.enable_reg = 0x2028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
@ -737,7 +735,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
@ -755,7 +753,7 @@ static struct clk_branch disp_cc_mdss_byte1_clk = {
.clkr = {
.enable_reg = 0x2030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_clk_src.clkr.hw,
@ -773,7 +771,7 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
.clkr = {
.enable_reg = 0x2034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
@ -791,7 +789,7 @@ static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
.clkr = {
.enable_reg = 0x2068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_aux1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
@ -809,7 +807,7 @@ static struct clk_branch disp_cc_mdss_dp_aux_clk = {
.clkr = {
.enable_reg = 0x2054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
@ -827,7 +825,7 @@ static struct clk_branch disp_cc_mdss_dp_link1_clk = {
.clkr = {
.enable_reg = 0x205c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_link1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link1_clk_src.clkr.hw,
@ -845,7 +843,7 @@ static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
.clkr = {
.enable_reg = 0x2060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_link1_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
@ -862,7 +860,7 @@ static struct clk_branch disp_cc_mdss_dp_link_clk = {
.clkr = {
.enable_reg = 0x2040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
@ -880,7 +878,7 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
@ -897,7 +895,7 @@ static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
.clkr = {
.enable_reg = 0x2050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
@ -915,7 +913,7 @@ static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
.clkr = {
.enable_reg = 0x2058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_pixel2_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
@ -933,7 +931,7 @@ static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
.clkr = {
.enable_reg = 0x204c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
@ -951,7 +949,7 @@ static struct clk_branch disp_cc_mdss_esc0_clk = {
.clkr = {
.enable_reg = 0x2038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
@ -969,7 +967,7 @@ static struct clk_branch disp_cc_mdss_esc1_clk = {
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc1_clk_src.clkr.hw,
@ -987,7 +985,7 @@ static struct clk_branch disp_cc_mdss_mdp_clk = {
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
@ -1005,7 +1003,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.clkr = {
.enable_reg = 0x201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
@ -1022,7 +1020,7 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
@ -1040,7 +1038,7 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = {
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
@ -1058,7 +1056,7 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = {
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
@ -1076,7 +1074,7 @@ static struct clk_branch disp_cc_mdss_rot_clk = {
.clkr = {
.enable_reg = 0x2014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
@ -1094,7 +1092,7 @@ static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.clkr = {
.enable_reg = 0x400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
@ -1112,7 +1110,7 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.clkr = {
.enable_reg = 0x4008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
@ -1130,7 +1128,7 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
@ -1365,8 +1363,8 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
/* DISP_CC_XO_CLK always-on */
regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
@ -1383,17 +1381,7 @@ static struct platform_driver disp_cc_sm8250_driver = {
},
};
static int __init disp_cc_sm8250_init(void)
{
return platform_driver_register(&disp_cc_sm8250_driver);
}
subsys_initcall(disp_cc_sm8250_init);
static void __exit disp_cc_sm8250_exit(void)
{
platform_driver_unregister(&disp_cc_sm8250_driver);
}
module_exit(disp_cc_sm8250_exit);
module_platform_driver(disp_cc_sm8250_driver);
MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
MODULE_LICENSE("GPL v2");

19
drivers/clk/qcom/dispcc-sm8450.c
View File

@ -1787,11 +1787,8 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/*
* Keep clocks always enabled:
* disp_cc_xo_clk
*/
regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap);
if (ret)
@ -1815,17 +1812,7 @@ static struct platform_driver disp_cc_sm8450_driver = {
},
};
static int __init disp_cc_sm8450_init(void)
{
return platform_driver_register(&disp_cc_sm8450_driver);
}
subsys_initcall(disp_cc_sm8450_init);
static void __exit disp_cc_sm8450_exit(void)
{
platform_driver_unregister(&disp_cc_sm8450_driver);
}
module_exit(disp_cc_sm8450_exit);
module_platform_driver(disp_cc_sm8450_driver);
MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver");
MODULE_LICENSE("GPL");

19
drivers/clk/qcom/dispcc-sm8550.c
View File

@ -1780,11 +1780,8 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/*
* Keep clocks always enabled:
* disp_cc_xo_clk
*/
regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap);
if (ret)
@ -1808,17 +1805,7 @@ static struct platform_driver disp_cc_sm8550_driver = {
},
};
static int __init disp_cc_sm8550_init(void)
{
return platform_driver_register(&disp_cc_sm8550_driver);
}
subsys_initcall(disp_cc_sm8550_init);
static void __exit disp_cc_sm8550_exit(void)
{
platform_driver_unregister(&disp_cc_sm8550_driver);
}
module_exit(disp_cc_sm8550_exit);
module_platform_driver(disp_cc_sm8550_driver);
MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver");
MODULE_LICENSE("GPL");

16
drivers/clk/qcom/dispcc-sm8650.c
View File

@ -1777,8 +1777,8 @@ static int disp_cc_sm8650_probe(struct platform_device *pdev)
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/* Keep clocks always enabled */
regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap);
if (ret)
@ -1802,17 +1802,7 @@ static struct platform_driver disp_cc_sm8650_driver = {
},
};
static int __init disp_cc_sm8650_init(void)
{
return platform_driver_register(&disp_cc_sm8650_driver);
}
subsys_initcall(disp_cc_sm8650_init);
static void __exit disp_cc_sm8650_exit(void)
{
platform_driver_unregister(&disp_cc_sm8650_driver);
}
module_exit(disp_cc_sm8650_exit);
module_platform_driver(disp_cc_sm8650_driver);
MODULE_DESCRIPTION("QTI DISPCC SM8650 Driver");
MODULE_LICENSE("GPL");

1718
drivers/clk/qcom/dispcc-x1e80100.c Normal file
View File

File diff suppressed because it is too large Load Diff

9
drivers/clk/qcom/gcc-ipq5018.c
View File

@ -857,6 +857,7 @@ static struct clk_rcg2 lpass_sway_clk_src = {
static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
F(2000000, P_XO, 12, 0, 0),
{ }
};
static struct clk_rcg2 pcie0_aux_clk_src = {
@ -1099,6 +1100,7 @@ static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 qpic_io_macro_clk_src = {
@ -1194,6 +1196,7 @@ static struct clk_rcg2 ubi0_axi_clk_src = {
static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
F(850000000, P_UBI32_PLL, 1, 0, 0),
F(1000000000, P_UBI32_PLL, 1, 0, 0),
{ }
};
static struct clk_rcg2 ubi0_core_clk_src = {
@ -1754,7 +1757,7 @@ static struct clk_branch gcc_gmac0_sys_clk = {
.halt_check = BRANCH_HALT_DELAY,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x683190,
.enable_reg = 0x68190,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac0_sys_clk",
@ -2180,7 +2183,7 @@ static struct clk_branch gcc_pcie1_axi_s_clk = {
};
static struct clk_branch gcc_pcie1_pipe_clk = {
.halt_reg = 8,
.halt_reg = 0x76018,
.halt_check = BRANCH_HALT_DELAY,
.halt_bit = 31,
.clkr = {
@ -3632,7 +3635,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = {
[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
[GCC_TCSR_BCR] = { 0x28000, 0 },
[GCC_TLMM_BCR] = { 0x34000, 0 },
[GCC_UBI0_AXI_ARES] = { 0x680},
[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },

19
drivers/clk/qcom/gcc-ipq6018.c
View File

@ -1554,6 +1554,7 @@ static struct clk_regmap_div nss_ubi0_div_clk_src = {
static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
@ -1734,6 +1735,7 @@ static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
F(160000000, P_GPLL0, 5, 0, 0),
F(216000000, P_GPLL6, 5, 0, 0),
F(308570000, P_GPLL6, 3.5, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
@ -3522,6 +3524,22 @@ static struct clk_branch gcc_prng_ahb_clk = {
},
};
static struct clk_branch gcc_qdss_at_clk = {
.halt_reg = 0x29024,
.clkr = {
.enable_reg = 0x29024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qdss_at_clk",
.parent_hws = (const struct clk_hw *[]){
&qdss_at_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.clkr = {
@ -4361,6 +4379,7 @@ static struct clk_regmap *gcc_ipq6018_clks[] = {
[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,

2
drivers/clk/qcom/gcc-ipq8074.c
View File

@ -644,6 +644,7 @@ static struct clk_rcg2 pcie0_axi_clk_src = {
static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
@ -795,6 +796,7 @@ static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(308570000, P_GPLL6, 3.5, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {

1
drivers/clk/qcom/gcc-ipq9574.c
View File

@ -2082,6 +2082,7 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
F(150000000, P_GPLL4, 8, 0, 0),
F(300000000, P_GPLL4, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {

4
drivers/clk/qcom/gcc-msm8953.c
View File

@ -4171,6 +4171,10 @@ static const struct qcom_reset_map gcc_msm8953_resets[] = {
[GCC_USB3PHY_PHY_BCR] = { 0x3f03c },
[GCC_USB3_PHY_BCR] = { 0x3f034 },
[GCC_USB_30_BCR] = { 0x3f070 },
[GCC_MDSS_BCR] = { 0x4d074 },
[GCC_CRYPTO_BCR] = { 0x16000 },
[GCC_SDCC1_BCR] = { 0x42000 },
[GCC_SDCC2_BCR] = { 0x43000 },
};
static const struct regmap_config gcc_msm8953_regmap_config = {

29
drivers/clk/qcom/gcc-sa8775p.c
View File

@ -4662,8 +4662,8 @@ static const struct qcom_reset_map gcc_sa8775p_resets[] = {
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 },
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 },
[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 },
[GCC_VIDEO_BCR] = { 0x34000 },
};
@ -4742,21 +4742,16 @@ static int gcc_sa8775p_probe(struct platform_device *pdev)
if (ret)
return ret;
/*
* Keep the clocks always-ON
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK,
* GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
* GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK.
*/
regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */
return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap);
}

22
drivers/clk/qcom/gcc-sc7180.c
View File

@ -2443,19 +2443,15 @@ static int gcc_sc7180_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/*
* Keep the clocks always-ON
* GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
* GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK
*/
regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */
qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));

20
drivers/clk/qcom/gcc-sc7280.c
View File

@ -3453,18 +3453,14 @@ static int gcc_sc7280_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Keep the clocks always-ON
* GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK
* GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK
*/
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */
regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,

62
drivers/clk/qcom/gcc-sc8180x.c
View File

@ -3347,6 +3347,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = {
},
};
static struct clk_branch gcc_ufs_card_clkref_en = {
.halt_reg = 0x8c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x75014,
.halt_check = BRANCH_HALT,
@ -3561,6 +3574,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
},
};
static struct clk_branch gcc_ufs_mem_clkref_en = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_mem_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77014,
.halt_check = BRANCH_HALT,
@ -4413,6 +4439,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
[GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr,
[GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr,
[GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr,
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
@ -4429,6 +4456,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
[GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
@ -4528,9 +4556,9 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = {
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
[GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
[GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
[GCC_VIDEO_AXIC_CLK_BCR] = { .reg = 0xb02c, .bit = 2, .udelay = 150 },
[GCC_VIDEO_AXI0_CLK_BCR] = { .reg = 0xb024, .bit = 2, .udelay = 150 },
[GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },
};
static struct gdsc *gcc_sc8180x_gdscs[] = {
@ -4579,23 +4607,17 @@ static int gcc_sc8180x_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Enable the following always-on clocks:
* GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
* GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK,
* GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and
* GCC_GPU_CFG_AHB_CLK
*/
regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */
qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */
qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);

29
drivers/clk/qcom/gcc-sc8280xp.c
View File

@ -7448,8 +7448,8 @@ static const struct qcom_reset_map gcc_sc8280xp_resets[] = {
[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_BCR] = { 0x28000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
};
static struct gdsc *gcc_sc8280xp_gdscs[] = {
@ -7543,21 +7543,16 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
goto err_put_rpm;
}
/*
* Keep the clocks always-ON
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK,
* GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK,
* GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK
*/
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)

1
drivers/clk/qcom/gcc-sdm845.c
View File

@ -4037,3 +4037,4 @@ module_exit(gcc_sdm845_exit);
MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-sdm845");
MODULE_SOFTDEP("pre: rpmhpd");

12
drivers/clk/qcom/gcc-sdx55.c
View File

@ -1611,14 +1611,10 @@ static int gcc_sdx55_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Keep the clocks always-ON as they are critical to the functioning
* of the system:
* GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK
*/
regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap);
}

13
drivers/clk/qcom/gcc-sdx65.c
View File

@ -1574,14 +1574,11 @@ static int gcc_sdx65_probe(struct platform_device *pdev)
regmap = qcom_cc_map(pdev, &gcc_sdx65_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Keep the clocks always-ON as they are critical to the functioning
* of the system:
* GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK
*/
regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap);
}

10
drivers/clk/qcom/gcc-sdx75.c
View File

@ -2936,13 +2936,9 @@ static int gcc_sdx75_probe(struct platform_device *pdev)
if (ret)
return ret;
/*
* Keep clocks always enabled:
* gcc_ahb_pcie_link_clk
* gcc_xo_pcie_link_clk
*/
regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */
qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */
return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap);
}

32
drivers/clk/qcom/gcc-sm4450.c
View File

@ -2791,8 +2791,8 @@ static const struct qcom_reset_map gcc_sm4450_resets[] = {
[GCC_VENUS_BCR] = { 0xb601c },
[GCC_VIDEO_BCR] = { 0x42000 },
[GCC_VIDEO_VENUS_BCR] = { 0xb6000 },
[GCC_VENUS_CTL_AXI_CLK_ARES] = { 0x4201c, 2 },
[GCC_VIDEO_VENUS_CTL_CLK_ARES] = { 0xb6038, 2 },
[GCC_VENUS_CTL_AXI_CLK_ARES] = { .reg = 0x4201c, .bit = 2, .udelay = 400 },
[GCC_VIDEO_VENUS_CTL_CLK_ARES] = { .reg = 0xb6038, .bit = 2, .udelay = 400 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
@ -2849,25 +2849,15 @@ static int gcc_sm4450_probe(struct platform_device *pdev)
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
/*
* Keep clocks always enabled:
* gcc_camera_ahb_clk
* gcc_camera_sleep_clk
* gcc_camera_xo_clk
* gcc_disp_ahb_clk
* gcc_disp_xo_clk
* gcc_gpu_cfg_ahb_clk
* gcc_video_ahb_clk
* gcc_video_xo_clk
*/
regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x36018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x3601c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x37014, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x42018, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */
regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21));

11
drivers/clk/qcom/gcc-sm6375.c
View File

@ -3882,13 +3882,10 @@ static int gcc_sm6375_probe(struct platform_device *pdev)
if (ret)
return ret;
/*
* Keep the following clocks always on:
* GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK
*/
regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */
qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */
clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config);
clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config);

25
drivers/clk/qcom/gcc-sm7150.c
View File

@ -2918,7 +2918,7 @@ static const struct qcom_reset_map gcc_sm7150_resets[] = {
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
[GCC_VIDEO_AXI_CLK_BCR] = { 0xb01c, 2 },
[GCC_VIDEO_AXI_CLK_BCR] = { .reg = 0xb01c, .bit = 2, .udelay = 150 },
};
static const struct clk_rcg_dfs_data gcc_sm7150_dfs_desc[] = {
@ -3002,20 +3002,15 @@ static int gcc_sm7150_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/*
* Keep the critical clocks always-ON
* GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
* GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK,
* GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK
*/
regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */
qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc,
ARRAY_SIZE(gcc_sm7150_dfs_desc));

352
drivers/clk/qcom/gcc-sm8150.c
View File

@ -453,19 +453,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@ -474,13 +484,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@ -489,13 +501,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@ -504,13 +518,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@ -519,13 +535,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@ -534,13 +552,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@ -549,13 +569,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@ -564,13 +586,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@ -579,13 +603,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@ -594,13 +620,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@ -609,13 +637,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@ -624,13 +654,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@ -639,13 +671,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@ -654,13 +688,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@ -669,13 +705,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@ -684,13 +722,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@ -699,13 +739,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@ -714,13 +756,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@ -729,13 +773,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@ -744,13 +790,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@ -3738,6 +3778,9 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = {
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
[GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
[GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
};
static struct gdsc *gcc_sm8150_gdscs[] = {
@ -3750,6 +3793,29 @@ static struct gdsc *gcc_sm8150_gdscs[] = {
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
};
static const struct regmap_config gcc_sm8150_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -3777,6 +3843,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
static int gcc_sm8150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
if (IS_ERR(regmap))
@ -3786,6 +3853,11 @@ static int gcc_sm8150_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
dev_err_probe(&pdev->dev, ret, "Failed to register with DFS!\n");
return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
}

23
drivers/clk/qcom/gcc-sm8250.c
View File

@ -3576,8 +3576,8 @@ static const struct qcom_reset_map gcc_sm8250_resets[] = {
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, .bit = 2, .udelay = 150 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, .bit = 2, .udelay = 150 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
@ -3643,18 +3643,13 @@ static int gcc_sm8250_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/*
* Keep the clocks always-ON
* GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
* GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK,
* GCC_SYS_NOC_CPUSS_AHB_CLK
*/
regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));

24
drivers/clk/qcom/gcc-sm8350.c
View File

@ -3743,8 +3743,8 @@ static const struct qcom_reset_map gcc_sm8350_resets[] = {
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
[GCC_VIDEO_BCR] = { 0x28000 },
};
@ -3806,18 +3806,14 @@ static int gcc_sm8350_probe(struct platform_device *pdev)
return PTR_ERR(regmap);
}
/*
* Keep the critical clock always-On
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
* GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK
*/
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26018); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x2701c); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28020); /* GCC_VIDEO_XO_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)

25
drivers/clk/qcom/gcc-sm8450.c
View File

@ -3202,8 +3202,8 @@ static const struct qcom_reset_map gcc_sm8450_resets[] = {
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 },
[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_BCR] = { 0x42000 },
};
@ -3280,19 +3280,14 @@ static int gcc_sm8450_probe(struct platform_device *pdev)
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
/*
* Keep the critical clock always-On
* gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
* gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
* gcc_video_xo_clk
*/
regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */
return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
}

25
drivers/clk/qcom/gcc-sm8550.c
View File

@ -3276,8 +3276,8 @@ static const struct qcom_reset_map gcc_sm8550_resets[] = {
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 },
[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_BCR] = { 0x32000 },
};
@ -3352,19 +3352,14 @@ static int gcc_sm8550_probe(struct platform_device *pdev)
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
/*
* Keep the critical clock always-On
* gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
* gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
* gcc_video_xo_clk
*/
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52024, 0x0);

20
drivers/clk/qcom/gcc-sm8650.c
View File

@ -3734,8 +3734,8 @@ static const struct qcom_reset_map gcc_sm8650_resets[] = {
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 },
[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_BCR] = { 0x32000 },
};
@ -3808,14 +3808,14 @@ static int gcc_sm8650_probe(struct platform_device *pdev)
if (ret)
return ret;
/* Keep the critical clock always-On */
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */
regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */
regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */
regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */
regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);

16
drivers/clk/qcom/gcc-x1e80100.c
View File

@ -6769,14 +6769,14 @@ static int gcc_x1e80100_probe(struct platform_device *pdev)
if (ret)
return ret;
/* Keep the critical clock always-On */
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */
regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */
regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */
regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */
regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52224, 0x0);

12
drivers/clk/qcom/gdsc.c
View File

@ -557,7 +557,15 @@ void gdsc_unregister(struct gdsc_desc *desc)
*/
int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
{
/* Do nothing but give genpd the impression that we were successful */
return 0;
struct gdsc *sc = domain_to_gdsc(domain);
int ret = 0;
/* Enable the parent supply, when controlled through the regulator framework. */
if (sc->rsupply)
ret = regulator_enable(sc->rsupply);
/* Do nothing with the GDSC itself */
return ret;
}
EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);

12
drivers/clk/qcom/gpucc-sa8775p.c
View File

@ -609,17 +609,7 @@ static struct platform_driver gpu_cc_sa8775p_driver = {
},
};
static int __init gpu_cc_sa8775p_init(void)
{
return platform_driver_register(&gpu_cc_sa8775p_driver);
}
subsys_initcall(gpu_cc_sa8775p_init);
static void __exit gpu_cc_sa8775p_exit(void)
{
platform_driver_unregister(&gpu_cc_sa8775p_driver);
}
module_exit(gpu_cc_sa8775p_exit);
module_platform_driver(gpu_cc_sa8775p_driver);
MODULE_DESCRIPTION("SA8775P GPUCC driver");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/gpucc-sc7180.c
View File

@ -252,17 +252,7 @@ static struct platform_driver gpu_cc_sc7180_driver = {
},
};
static int __init gpu_cc_sc7180_init(void)
{
return platform_driver_register(&gpu_cc_sc7180_driver);
}
subsys_initcall(gpu_cc_sc7180_init);
static void __exit gpu_cc_sc7180_exit(void)
{
platform_driver_unregister(&gpu_cc_sc7180_driver);
}
module_exit(gpu_cc_sc7180_exit);
module_platform_driver(gpu_cc_sc7180_driver);
MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver");
MODULE_LICENSE("GPL v2");

21
drivers/clk/qcom/gpucc-sc7280.c
View File

@ -457,12 +457,9 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep the clocks always-ON
* GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK
*/
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */
qcom_branch_set_clk_en(regmap, 0x1098); /* GPUCC_CX_GMU_CLK */
regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13));
return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap);
@ -476,17 +473,7 @@ static struct platform_driver gpu_cc_sc7280_driver = {
},
};
static int __init gpu_cc_sc7280_init(void)
{
return platform_driver_register(&gpu_cc_sc7280_driver);
}
subsys_initcall(gpu_cc_sc7280_init);
static void __exit gpu_cc_sc7280_exit(void)
{
platform_driver_unregister(&gpu_cc_sc7280_driver);
}
module_exit(gpu_cc_sc7280_exit);
module_platform_driver(gpu_cc_sc7280_driver);
MODULE_DESCRIPTION("QTI GPU_CC SC7280 Driver");
MODULE_LICENSE("GPL v2");

10
drivers/clk/qcom/gpucc-sc8280xp.c
View File

@ -399,6 +399,7 @@ static struct gdsc gx_gdsc = {
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | RETAIN_FF_ENABLE,
.supply = "vdd-gfx",
};
static struct gdsc *gpu_cc_sc8280xp_gdscs[] = {
@ -444,12 +445,9 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep the clocks always-ON
* GPU_CC_CB_CLK, GPU_CC_CXO_CLK
*/
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */
qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */
ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
pm_runtime_put(&pdev->dev);

12
drivers/clk/qcom/gpucc-sdm845.c
View File

@ -203,17 +203,7 @@ static struct platform_driver gpu_cc_sdm845_driver = {
},
};
static int __init gpu_cc_sdm845_init(void)
{
return platform_driver_register(&gpu_cc_sdm845_driver);
}
subsys_initcall(gpu_cc_sdm845_init);
static void __exit gpu_cc_sdm845_exit(void)
{
platform_driver_unregister(&gpu_cc_sdm845_driver);
}
module_exit(gpu_cc_sdm845_exit);
module_platform_driver(gpu_cc_sdm845_driver);
MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/gpucc-sm8150.c
View File

@ -315,17 +315,7 @@ static struct platform_driver gpu_cc_sm8150_driver = {
},
};
static int __init gpu_cc_sm8150_init(void)
{
return platform_driver_register(&gpu_cc_sm8150_driver);
}
subsys_initcall(gpu_cc_sm8150_init);
static void __exit gpu_cc_sm8150_exit(void)
{
platform_driver_unregister(&gpu_cc_sm8150_driver);
}
module_exit(gpu_cc_sm8150_exit);
module_platform_driver(gpu_cc_sm8150_driver);
MODULE_DESCRIPTION("QTI GPUCC SM8150 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/gpucc-sm8250.c
View File

@ -331,17 +331,7 @@ static struct platform_driver gpu_cc_sm8250_driver = {
},
};
static int __init gpu_cc_sm8250_init(void)
{
return platform_driver_register(&gpu_cc_sm8250_driver);
}
subsys_initcall(gpu_cc_sm8250_init);
static void __exit gpu_cc_sm8250_exit(void)
{
platform_driver_unregister(&gpu_cc_sm8250_driver);
}
module_exit(gpu_cc_sm8250_exit);
module_platform_driver(gpu_cc_sm8250_driver);
MODULE_DESCRIPTION("QTI GPU_CC SM8250 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/gpucc-sm8350.c
View File

@ -621,17 +621,7 @@ static struct platform_driver gpu_cc_sm8350_driver = {
},
};
static int __init gpu_cc_sm8350_init(void)
{
return platform_driver_register(&gpu_cc_sm8350_driver);
}
subsys_initcall(gpu_cc_sm8350_init);
static void __exit gpu_cc_sm8350_exit(void)
{
platform_driver_unregister(&gpu_cc_sm8350_driver);
}
module_exit(gpu_cc_sm8350_exit);
module_platform_driver(gpu_cc_sm8350_driver);
MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver");
MODULE_LICENSE("GPL v2");

22
drivers/clk/qcom/gpucc-sm8550.c
View File

@ -575,13 +575,9 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev)
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep clocks always enabled:
* gpu_cc_cxo_aon_clk
* gpu_cc_demet_clk
*/
regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */
qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */
return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap);
}
@ -594,17 +590,7 @@ static struct platform_driver gpu_cc_sm8550_driver = {
},
};
static int __init gpu_cc_sm8550_init(void)
{
return platform_driver_register(&gpu_cc_sm8550_driver);
}
subsys_initcall(gpu_cc_sm8550_init);
static void __exit gpu_cc_sm8550_exit(void)
{
platform_driver_unregister(&gpu_cc_sm8550_driver);
}
module_exit(gpu_cc_sm8550_exit);
module_platform_driver(gpu_cc_sm8550_driver);
MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver");
MODULE_LICENSE("GPL");

656
drivers/clk/qcom/gpucc-x1e80100.c Normal file
View File

@ -0,0 +1,656 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
#include <dt-bindings/reset/qcom,x1e80100-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
static const struct pll_vco zonda_ole_vco[] = {
{ 700000000, 3600000000, 0 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x29,
.alpha = 0xa000,
.config_ctl_val = 0x08240800,
.config_ctl_hi_val = 0x05008001,
.config_ctl_hi1_val = 0x00000000,
.config_ctl_hi2_val = 0x00000000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x02000000,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = zonda_ole_vco,
.num_vco = ARRAY_SIZE(zonda_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_zonda_ole_ops,
},
},
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x16,
.alpha = 0xeaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = NULL,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x9054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
.reg = 0x9050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cxo_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_demet_clk = {
.halt_reg = 0x900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x900c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_demet_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_freq_measure_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x90bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_vsense_clk = {
.halt_reg = 0x90b0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_vsense_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x9288,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9288,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
.halt_reg = 0x928c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x928c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x9108,
.gds_hw_ctrl = 0x953c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x905c,
.clamp_io_ctrl = 0x9504,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
};
static struct clk_regmap *gpu_cc_x1e80100_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
};
static const struct qcom_reset_map gpu_cc_x1e80100_resets[] = {
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_CB_BCR] = { 0x93a0 },
};
static struct gdsc *gpu_cc_x1e80100_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_x1e80100_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9988,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_x1e80100_desc = {
.config = &gpu_cc_x1e80100_regmap_config,
.clks = gpu_cc_x1e80100_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_x1e80100_clocks),
.resets = gpu_cc_x1e80100_resets,
.num_resets = ARRAY_SIZE(gpu_cc_x1e80100_resets),
.gdscs = gpu_cc_x1e80100_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_x1e80100_gdscs),
};
static const struct of_device_id gpu_cc_x1e80100_match_table[] = {
{ .compatible = "qcom,x1e80100-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_x1e80100_match_table);
static int gpu_cc_x1e80100_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_x1e80100_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_zonda_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/* Keep clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */
return qcom_cc_really_probe(pdev, &gpu_cc_x1e80100_desc, regmap);
}
static struct platform_driver gpu_cc_x1e80100_driver = {
.probe = gpu_cc_x1e80100_probe,
.driver = {
.name = "gpucc-x1e80100",
.of_match_table = gpu_cc_x1e80100_match_table,
},
};
module_platform_driver(gpu_cc_x1e80100_driver);
MODULE_DESCRIPTION("QTI GPU Clock Controller X1E80100 Driver");
MODULE_LICENSE("GPL");

7
drivers/clk/qcom/lpasscorecc-sc7180.c
View File

@ -401,11 +401,8 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
goto exit;
}
/*
* Keep the CLK always-ON
* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK
*/
regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x24000); /* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK */
/* PLL settings */
regmap_write(regmap, 0x1008, 0x20);

2
drivers/clk/qcom/mmcc-apq8084.c
View File

@ -348,6 +348,7 @@ static struct freq_tbl ftbl_mmss_axi_clk[] = {
F(333430000, P_MMPLL1, 3.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(466800000, P_MMPLL1, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 mmss_axi_clk_src = {
@ -372,6 +373,7 @@ static struct freq_tbl ftbl_ocmemnoc_clk[] = {
F(150000000, P_GPLL0, 4, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 ocmemnoc_clk_src = {

2
drivers/clk/qcom/mmcc-msm8974.c
View File

@ -290,6 +290,7 @@ static struct freq_tbl ftbl_mmss_axi_clk[] = {
F(291750000, P_MMPLL1, 4, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(466800000, P_MMPLL1, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 mmss_axi_clk_src = {
@ -314,6 +315,7 @@ static struct freq_tbl ftbl_ocmemnoc_clk[] = {
F(150000000, P_GPLL0, 4, 0, 0),
F(291750000, P_MMPLL1, 4, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 ocmemnoc_clk_src = {

140
drivers/clk/qcom/mss-sc7180.c
View File

@ -1,140 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,mss-sc7180.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
static struct clk_branch mss_axi_nav_clk = {
.halt_reg = 0x20bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mss_axi_nav_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "gcc_mss_nav_axi",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mss_axi_crypto_clk = {
.halt_reg = 0x20cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mss_axi_crypto_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "gcc_mss_mfab_axis",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct regmap_config mss_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
.max_register = 0x41aa0cc,
};
static struct clk_regmap *mss_sc7180_clocks[] = {
[MSS_AXI_CRYPTO_CLK] = &mss_axi_crypto_clk.clkr,
[MSS_AXI_NAV_CLK] = &mss_axi_nav_clk.clkr,
};
static const struct qcom_cc_desc mss_sc7180_desc = {
.config = &mss_regmap_config,
.clks = mss_sc7180_clocks,
.num_clks = ARRAY_SIZE(mss_sc7180_clocks),
};
static int mss_sc7180_probe(struct platform_device *pdev)
{
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, "cfg_ahb");
if (ret < 0) {
dev_err(&pdev->dev, "failed to acquire iface clock\n");
return ret;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
ret = qcom_cc_probe(pdev, &mss_sc7180_desc);
if (ret < 0)
goto err_put_rpm;
pm_runtime_put(&pdev->dev);
return 0;
err_put_rpm:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static const struct dev_pm_ops mss_sc7180_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static const struct of_device_id mss_sc7180_match_table[] = {
{ .compatible = "qcom,sc7180-mss" },
{ }
};
MODULE_DEVICE_TABLE(of, mss_sc7180_match_table);
static struct platform_driver mss_sc7180_driver = {
.probe = mss_sc7180_probe,
.driver = {
.name = "sc7180-mss",
.of_match_table = mss_sc7180_match_table,
.pm = &mss_sc7180_pm_ops,
},
};
static int __init mss_sc7180_init(void)
{
return platform_driver_register(&mss_sc7180_driver);
}
subsys_initcall(mss_sc7180_init);
static void __exit mss_sc7180_exit(void)
{
platform_driver_unregister(&mss_sc7180_driver);
}
module_exit(mss_sc7180_exit);
MODULE_DESCRIPTION("QTI MSS SC7180 Driver");
MODULE_LICENSE("GPL v2");

27
drivers/clk/qcom/reset.c
View File

@ -22,8 +22,8 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
return 0;
}
static int
qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
static int qcom_reset_set_assert(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct qcom_reset_controller *rst;
const struct qcom_reset_map *map;
@ -33,21 +33,22 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
map = &rst->reset_map[id];
mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, mask);
regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
/* Read back the register to ensure write completion, ignore the value */
regmap_read(rst->regmap, map->reg, &mask);
return 0;
}
static int
qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
static int qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct qcom_reset_controller *rst;
const struct qcom_reset_map *map;
u32 mask;
return qcom_reset_set_assert(rcdev, id, true);
}
rst = to_qcom_reset_controller(rcdev);
map = &rst->reset_map[id];
mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, 0);
static int qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
{
return qcom_reset_set_assert(rcdev, id, false);
}
const struct reset_control_ops qcom_reset_ops = {

2
drivers/clk/qcom/reset.h
View File

@ -11,7 +11,7 @@
struct qcom_reset_map {
unsigned int reg;
u8 bit;
u8 udelay;
u16 udelay;
u32 bitmask;
};

285
drivers/clk/qcom/tcsrcc-x1e80100.c Normal file
View File

@ -0,0 +1,285 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include "clk-branch.h"
#include "clk-regmap.h"
#include "common.h"
#include "reset.h"
enum {
DT_BI_TCXO_PAD,
};
static struct clk_branch tcsr_edp_clkref_en = {
.halt_reg = 0x15130,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_edp_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_2l_4_clkref_en = {
.halt_reg = 0x15100,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_pcie_2l_4_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_2l_5_clkref_en = {
.halt_reg = 0x15104,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15104,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_pcie_2l_5_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_8l_clkref_en = {
.halt_reg = 0x15108,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_pcie_8l_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_mp0_clkref_en = {
.halt_reg = 0x1510c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1510c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb3_mp0_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_mp1_clkref_en = {
.halt_reg = 0x15110,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb3_mp1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_1_clkref_en = {
.halt_reg = 0x15114,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15114,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb2_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_ufs_phy_clkref_en = {
.halt_reg = 0x15118,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15118,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_ufs_phy_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb4_1_clkref_en = {
.halt_reg = 0x15120,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15120,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb4_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb4_2_clkref_en = {
.halt_reg = 0x15124,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb4_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_2_clkref_en = {
.halt_reg = 0x15128,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x15128,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb2_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_4l_clkref_en = {
.halt_reg = 0x1512c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1512c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_pcie_4l_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *tcsr_cc_x1e80100_clocks[] = {
[TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr,
[TCSR_PCIE_2L_4_CLKREF_EN] = &tcsr_pcie_2l_4_clkref_en.clkr,
[TCSR_PCIE_2L_5_CLKREF_EN] = &tcsr_pcie_2l_5_clkref_en.clkr,
[TCSR_PCIE_8L_CLKREF_EN] = &tcsr_pcie_8l_clkref_en.clkr,
[TCSR_USB3_MP0_CLKREF_EN] = &tcsr_usb3_mp0_clkref_en.clkr,
[TCSR_USB3_MP1_CLKREF_EN] = &tcsr_usb3_mp1_clkref_en.clkr,
[TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
[TCSR_UFS_PHY_CLKREF_EN] = &tcsr_ufs_phy_clkref_en.clkr,
[TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr,
[TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr,
[TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
[TCSR_PCIE_4L_CLKREF_EN] = &tcsr_pcie_4l_clkref_en.clkr,
};
static const struct regmap_config tcsr_cc_x1e80100_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x2f000,
.fast_io = true,
};
static const struct qcom_cc_desc tcsr_cc_x1e80100_desc = {
.config = &tcsr_cc_x1e80100_regmap_config,
.clks = tcsr_cc_x1e80100_clocks,
.num_clks = ARRAY_SIZE(tcsr_cc_x1e80100_clocks),
};
static const struct of_device_id tcsr_cc_x1e80100_match_table[] = {
{ .compatible = "qcom,x1e80100-tcsr" },
{ }
};
MODULE_DEVICE_TABLE(of, tcsr_cc_x1e80100_match_table);
static int tcsr_cc_x1e80100_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &tcsr_cc_x1e80100_desc);
}
static struct platform_driver tcsr_cc_x1e80100_driver = {
.probe = tcsr_cc_x1e80100_probe,
.driver = {
.name = "tcsrcc-x1e80100",
.of_match_table = tcsr_cc_x1e80100_match_table,
},
};
static int __init tcsr_cc_x1e80100_init(void)
{
return platform_driver_register(&tcsr_cc_x1e80100_driver);
}
subsys_initcall(tcsr_cc_x1e80100_init);
static void __exit tcsr_cc_x1e80100_exit(void)
{
platform_driver_unregister(&tcsr_cc_x1e80100_driver);
}
module_exit(tcsr_cc_x1e80100_exit);
MODULE_DESCRIPTION("QTI TCSR Clock Controller X1E80100 Driver");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/videocc-sc7180.c
View File

@ -237,17 +237,7 @@ static struct platform_driver video_cc_sc7180_driver = {
},
};
static int __init video_cc_sc7180_init(void)
{
return platform_driver_register(&video_cc_sc7180_driver);
}
subsys_initcall(video_cc_sc7180_init);
static void __exit video_cc_sc7180_exit(void)
{
platform_driver_unregister(&video_cc_sc7180_driver);
}
module_exit(video_cc_sc7180_exit);
module_platform_driver(video_cc_sc7180_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI VIDEOCC SC7180 Driver");

12
drivers/clk/qcom/videocc-sc7280.c
View File

@ -309,17 +309,7 @@ static struct platform_driver video_cc_sc7280_driver = {
},
};
static int __init video_cc_sc7280_init(void)
{
return platform_driver_register(&video_cc_sc7280_driver);
}
subsys_initcall(video_cc_sc7280_init);
static void __exit video_cc_sc7280_exit(void)
{
platform_driver_unregister(&video_cc_sc7280_driver);
}
module_exit(video_cc_sc7280_exit);
module_platform_driver(video_cc_sc7280_driver);
MODULE_DESCRIPTION("QTI VIDEO_CC sc7280 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/videocc-sdm845.c
View File

@ -340,16 +340,6 @@ static struct platform_driver video_cc_sdm845_driver = {
},
};
static int __init video_cc_sdm845_init(void)
{
return platform_driver_register(&video_cc_sdm845_driver);
}
subsys_initcall(video_cc_sdm845_init);
static void __exit video_cc_sdm845_exit(void)
{
platform_driver_unregister(&video_cc_sdm845_driver);
}
module_exit(video_cc_sdm845_exit);
module_platform_driver(video_cc_sdm845_driver);
MODULE_LICENSE("GPL v2");

14
drivers/clk/qcom/videocc-sm8150.c
View File

@ -215,7 +215,7 @@ static const struct regmap_config video_cc_sm8150_regmap_config = {
};
static const struct qcom_reset_map video_cc_sm8150_resets[] = {
[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
[VIDEO_CC_MVSC_CORE_CLK_BCR] = { .reg = 0x850, .bit = 2, .udelay = 150 },
[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
[VIDEO_CC_MVS0_BCR] = { 0x870 },
[VIDEO_CC_MVS1_BCR] = { 0x8b0 },
@ -277,17 +277,7 @@ static struct platform_driver video_cc_sm8150_driver = {
},
};
static int __init video_cc_sm8150_init(void)
{
return platform_driver_register(&video_cc_sm8150_driver);
}
subsys_initcall(video_cc_sm8150_init);
static void __exit video_cc_sm8150_exit(void)
{
platform_driver_unregister(&video_cc_sm8150_driver);
}
module_exit(video_cc_sm8150_exit);
module_platform_driver(video_cc_sm8150_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");

22
drivers/clk/qcom/videocc-sm8250.c
View File

@ -323,10 +323,10 @@ static struct clk_regmap *video_cc_sm8250_clocks[] = {
static const struct qcom_reset_map video_cc_sm8250_resets[] = {
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, .bit = 2, .udelay = 150 },
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, .bit = 2, .udelay = 150 },
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
};
@ -383,9 +383,9 @@ static int video_cc_sm8250_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
/* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap);
@ -402,17 +402,7 @@ static struct platform_driver video_cc_sm8250_driver = {
},
};
static int __init video_cc_sm8250_init(void)
{
return platform_driver_register(&video_cc_sm8250_driver);
}
subsys_initcall(video_cc_sm8250_init);
static void __exit video_cc_sm8250_exit(void)
{
platform_driver_unregister(&video_cc_sm8250_driver);
}
module_exit(video_cc_sm8250_exit);
module_platform_driver(video_cc_sm8250_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver");

14
drivers/clk/qcom/videocc-sm8350.c
View File

@ -488,10 +488,10 @@ static struct clk_regmap *video_cc_sm8350_clocks[] = {
static const struct qcom_reset_map video_cc_sm8350_resets[] = {
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0xc34, .bit = 2, .udelay = 400 },
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0xcd4, .bit = 2, .udelay = 400 },
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
};
@ -558,13 +558,9 @@ static int video_cc_sm8350_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
/*
* Keep clocks always enabled:
* video_cc_ahb_clk
* video_cc_xo_clk
*/
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, video_cc_xo_clk_cbcr); /* VIDEO_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap);
pm_runtime_put(&pdev->dev);

29
drivers/clk/qcom/videocc-sm8450.c
View File

@ -373,8 +373,8 @@ static const struct qcom_reset_map video_cc_sm8450_resets[] = {
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 },
};
static const struct regmap_config video_cc_sm8450_regmap_config = {
@ -423,15 +423,10 @@ static int video_cc_sm8450_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
/*
* Keep clocks always enabled:
* video_cc_ahb_clk
* video_cc_sleep_clk
* video_cc_xo_clk
*/
regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap);
@ -448,17 +443,7 @@ static struct platform_driver video_cc_sm8450_driver = {
},
};
static int __init video_cc_sm8450_init(void)
{
return platform_driver_register(&video_cc_sm8450_driver);
}
subsys_initcall(video_cc_sm8450_init);
static void __exit video_cc_sm8450_exit(void)
{
platform_driver_unregister(&video_cc_sm8450_driver);
}
module_exit(video_cc_sm8450_exit);
module_platform_driver(video_cc_sm8450_driver);
MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver");
MODULE_LICENSE("GPL");

29
drivers/clk/qcom/videocc-sm8550.c
View File

@ -378,8 +378,8 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = {
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 },
};
static const struct regmap_config video_cc_sm8550_regmap_config = {
@ -428,15 +428,10 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
/*
* Keep clocks always enabled:
* video_cc_ahb_clk
* video_cc_sleep_clk
* video_cc_xo_clk
*/
regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
@ -453,17 +448,7 @@ static struct platform_driver video_cc_sm8550_driver = {
},
};
static int __init video_cc_sm8550_init(void)
{
return platform_driver_register(&video_cc_sm8550_driver);
}
subsys_initcall(video_cc_sm8550_init);
static void __exit video_cc_sm8550_exit(void)
{
platform_driver_unregister(&video_cc_sm8550_driver);
}
module_exit(video_cc_sm8550_exit);
module_platform_driver(video_cc_sm8550_driver);
MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver");
MODULE_LICENSE("GPL");

4
include/dt-bindings/clock/qcom,gcc-msm8953.h
View File

@ -218,6 +218,10 @@
#define GCC_USB3PHY_PHY_BCR 3
#define GCC_USB3_PHY_BCR 4
#define GCC_USB_30_BCR 5
#define GCC_MDSS_BCR 6
#define GCC_CRYPTO_BCR 7
#define GCC_SDCC1_BCR 8
#define GCC_SDCC2_BCR 9
/* GDSCs */
#define CPP_GDSC 0

2
include/dt-bindings/clock/qcom,gcc-sc8180x.h
View File

@ -246,6 +246,8 @@
#define GCC_PCIE_3_CLKREF_CLK 236
#define GCC_USB3_PRIM_CLKREF_CLK 237
#define GCC_USB3_SEC_CLKREF_CLK 238
#define GCC_UFS_MEM_CLKREF_EN 239
#define GCC_UFS_CARD_CLKREF_EN 240
#define GCC_EMAC_BCR 0
#define GCC_GPU_BCR 1

3
include/dt-bindings/clock/qcom,gcc-sm8150.h
View File

@ -239,6 +239,9 @@
#define GCC_USB30_PRIM_BCR 26
#define GCC_USB30_SEC_BCR 27
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
#define GCC_VIDEO_AXIC_CLK_BCR 29
#define GCC_VIDEO_AXI0_CLK_BCR 30
#define GCC_VIDEO_AXI1_CLK_BCR 31
/* GCC GDSCRs */
#define PCIE_0_GDSC 0

135
include/dt-bindings/clock/qcom,x1e80100-camcc.h Normal file
View File

@ -0,0 +1,135 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_CLK 1
#define CAM_CC_BPS_CLK_SRC 2
#define CAM_CC_BPS_FAST_AHB_CLK 3
#define CAM_CC_CAMNOC_AXI_NRT_CLK 4
#define CAM_CC_CAMNOC_AXI_RT_CLK 5
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6
#define CAM_CC_CAMNOC_DCD_XO_CLK 7
#define CAM_CC_CAMNOC_XO_CLK 8
#define CAM_CC_CCI_0_CLK 9
#define CAM_CC_CCI_0_CLK_SRC 10
#define CAM_CC_CCI_1_CLK 11
#define CAM_CC_CCI_1_CLK_SRC 12
#define CAM_CC_CORE_AHB_CLK 13
#define CAM_CC_CPAS_AHB_CLK 14
#define CAM_CC_CPAS_BPS_CLK 15
#define CAM_CC_CPAS_FAST_AHB_CLK 16
#define CAM_CC_CPAS_IFE_0_CLK 17
#define CAM_CC_CPAS_IFE_1_CLK 18
#define CAM_CC_CPAS_IFE_LITE_CLK 19
#define CAM_CC_CPAS_IPE_NPS_CLK 20
#define CAM_CC_CPAS_SFE_0_CLK 21
#define CAM_CC_CPHY_RX_CLK_SRC 22
#define CAM_CC_CSI0PHYTIMER_CLK 23
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 24
#define CAM_CC_CSI1PHYTIMER_CLK 25
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 26
#define CAM_CC_CSI2PHYTIMER_CLK 27
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 28
#define CAM_CC_CSI3PHYTIMER_CLK 29
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 30
#define CAM_CC_CSI4PHYTIMER_CLK 31
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 32
#define CAM_CC_CSI5PHYTIMER_CLK 33
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 34
#define CAM_CC_CSID_CLK 35
#define CAM_CC_CSID_CLK_SRC 36
#define CAM_CC_CSID_CSIPHY_RX_CLK 37
#define CAM_CC_CSIPHY0_CLK 38
#define CAM_CC_CSIPHY1_CLK 39
#define CAM_CC_CSIPHY2_CLK 40
#define CAM_CC_CSIPHY3_CLK 41
#define CAM_CC_CSIPHY4_CLK 42
#define CAM_CC_CSIPHY5_CLK 43
#define CAM_CC_FAST_AHB_CLK_SRC 44
#define CAM_CC_GDSC_CLK 45
#define CAM_CC_ICP_AHB_CLK 46
#define CAM_CC_ICP_CLK 47
#define CAM_CC_ICP_CLK_SRC 48
#define CAM_CC_IFE_0_CLK 49
#define CAM_CC_IFE_0_CLK_SRC 50
#define CAM_CC_IFE_0_DSP_CLK 51
#define CAM_CC_IFE_0_FAST_AHB_CLK 52
#define CAM_CC_IFE_1_CLK 53
#define CAM_CC_IFE_1_CLK_SRC 54
#define CAM_CC_IFE_1_DSP_CLK 55
#define CAM_CC_IFE_1_FAST_AHB_CLK 56
#define CAM_CC_IFE_LITE_AHB_CLK 57
#define CAM_CC_IFE_LITE_CLK 58
#define CAM_CC_IFE_LITE_CLK_SRC 59
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 60
#define CAM_CC_IFE_LITE_CSID_CLK 61
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 62
#define CAM_CC_IPE_NPS_AHB_CLK 63
#define CAM_CC_IPE_NPS_CLK 64
#define CAM_CC_IPE_NPS_CLK_SRC 65
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 66
#define CAM_CC_IPE_PPS_CLK 67
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 68
#define CAM_CC_JPEG_CLK 69
#define CAM_CC_JPEG_CLK_SRC 70
#define CAM_CC_MCLK0_CLK 71
#define CAM_CC_MCLK0_CLK_SRC 72
#define CAM_CC_MCLK1_CLK 73
#define CAM_CC_MCLK1_CLK_SRC 74
#define CAM_CC_MCLK2_CLK 75
#define CAM_CC_MCLK2_CLK_SRC 76
#define CAM_CC_MCLK3_CLK 77
#define CAM_CC_MCLK3_CLK_SRC 78
#define CAM_CC_MCLK4_CLK 79
#define CAM_CC_MCLK4_CLK_SRC 80
#define CAM_CC_MCLK5_CLK 81
#define CAM_CC_MCLK5_CLK_SRC 82
#define CAM_CC_MCLK6_CLK 83
#define CAM_CC_MCLK6_CLK_SRC 84
#define CAM_CC_MCLK7_CLK 85
#define CAM_CC_MCLK7_CLK_SRC 86
#define CAM_CC_PLL0 87
#define CAM_CC_PLL0_OUT_EVEN 88
#define CAM_CC_PLL0_OUT_ODD 89
#define CAM_CC_PLL1 90
#define CAM_CC_PLL1_OUT_EVEN 91
#define CAM_CC_PLL2 92
#define CAM_CC_PLL3 93
#define CAM_CC_PLL3_OUT_EVEN 94
#define CAM_CC_PLL4 95
#define CAM_CC_PLL4_OUT_EVEN 96
#define CAM_CC_PLL6 97
#define CAM_CC_PLL6_OUT_EVEN 98
#define CAM_CC_PLL8 99
#define CAM_CC_PLL8_OUT_EVEN 100
#define CAM_CC_SFE_0_CLK 101
#define CAM_CC_SFE_0_CLK_SRC 102
#define CAM_CC_SFE_0_FAST_AHB_CLK 103
#define CAM_CC_SLEEP_CLK 104
#define CAM_CC_SLEEP_CLK_SRC 105
#define CAM_CC_SLOW_AHB_CLK_SRC 106
#define CAM_CC_XO_CLK_SRC 107
/* CAM_CC power domains */
#define CAM_CC_BPS_GDSC 0
#define CAM_CC_IFE_0_GDSC 1
#define CAM_CC_IFE_1_GDSC 2
#define CAM_CC_IPE_0_GDSC 3
#define CAM_CC_SFE_0_GDSC 4
#define CAM_CC_TITAN_TOP_GDSC 5
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_ICP_BCR 1
#define CAM_CC_IFE_0_BCR 2
#define CAM_CC_IFE_1_BCR 3
#define CAM_CC_IPE_0_BCR 4
#define CAM_CC_SFE_0_BCR 5
#endif

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include/dt-bindings/clock/qcom,x1e80100-dispcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_ACCU_CLK 0
#define DISP_CC_MDSS_AHB1_CLK 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_BYTE1_CLK 8
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
#define DISP_CC_MDSS_DPTX0_LINK_CLK 14
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22
#define DISP_CC_MDSS_DPTX1_AUX_CLK 23
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24
#define DISP_CC_MDSS_DPTX1_LINK_CLK 25
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33
#define DISP_CC_MDSS_DPTX2_AUX_CLK 34
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35
#define DISP_CC_MDSS_DPTX2_LINK_CLK 36
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43
#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44
#define DISP_CC_MDSS_DPTX3_AUX_CLK 45
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46
#define DISP_CC_MDSS_DPTX3_LINK_CLK 47
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52
#define DISP_CC_MDSS_ESC0_CLK 53
#define DISP_CC_MDSS_ESC0_CLK_SRC 54
#define DISP_CC_MDSS_ESC1_CLK 55
#define DISP_CC_MDSS_ESC1_CLK_SRC 56
#define DISP_CC_MDSS_MDP1_CLK 57
#define DISP_CC_MDSS_MDP_CLK 58
#define DISP_CC_MDSS_MDP_CLK_SRC 59
#define DISP_CC_MDSS_MDP_LUT1_CLK 60
#define DISP_CC_MDSS_MDP_LUT_CLK 61
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62
#define DISP_CC_MDSS_PCLK0_CLK 63
#define DISP_CC_MDSS_PCLK0_CLK_SRC 64
#define DISP_CC_MDSS_PCLK1_CLK 65
#define DISP_CC_MDSS_PCLK1_CLK_SRC 66
#define DISP_CC_MDSS_RSCC_AHB_CLK 67
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68
#define DISP_CC_MDSS_VSYNC1_CLK 69
#define DISP_CC_MDSS_VSYNC_CLK 70
#define DISP_CC_MDSS_VSYNC_CLK_SRC 71
#define DISP_CC_PLL0 72
#define DISP_CC_PLL1 73
#define DISP_CC_SLEEP_CLK 74
#define DISP_CC_SLEEP_CLK_SRC 75
#define DISP_CC_XO_CLK 76
#define DISP_CC_XO_CLK_SRC 77
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#define MDSS_INT2_GDSC 1
#endif

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include/dt-bindings/clock/qcom,x1e80100-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CB_CLK 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GMU_CLK 4
#define GPU_CC_CXO_AON_CLK 5
#define GPU_CC_CXO_CLK 6
#define GPU_CC_DEMET_CLK 7
#define GPU_CC_DEMET_DIV_CLK_SRC 8
#define GPU_CC_FF_CLK_SRC 9
#define GPU_CC_FREQ_MEASURE_CLK 10
#define GPU_CC_GMU_CLK_SRC 11
#define GPU_CC_GX_GMU_CLK 12
#define GPU_CC_GX_VSENSE_CLK 13
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
#define GPU_CC_HUB_AON_CLK 15
#define GPU_CC_HUB_CLK_SRC 16
#define GPU_CC_HUB_CX_INT_CLK 17
#define GPU_CC_MEMNOC_GFX_CLK 18
#define GPU_CC_MND1X_0_GFX3D_CLK 19
#define GPU_CC_MND1X_1_GFX3D_CLK 20
#define GPU_CC_PLL0 21
#define GPU_CC_PLL1 22
#define GPU_CC_SLEEP_CLK 23
#define GPU_CC_XO_CLK_SRC 24
#define GPU_CC_XO_DIV_CLK_SRC 25
/* GDSCs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif

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include/dt-bindings/clock/qcom,x1e80100-tcsr.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
/* TCSR CC clocks */
#define TCSR_PCIE_2L_4_CLKREF_EN 0
#define TCSR_PCIE_2L_5_CLKREF_EN 1
#define TCSR_PCIE_8L_CLKREF_EN 2
#define TCSR_USB3_MP0_CLKREF_EN 3
#define TCSR_USB3_MP1_CLKREF_EN 4
#define TCSR_USB2_1_CLKREF_EN 5
#define TCSR_UFS_PHY_CLKREF_EN 6
#define TCSR_USB4_1_CLKREF_EN 7
#define TCSR_USB4_2_CLKREF_EN 8
#define TCSR_USB2_2_CLKREF_EN 9
#define TCSR_PCIE_4L_CLKREF_EN 10
#define TCSR_EDP_CLKREF_EN 11
#endif

19
include/dt-bindings/reset/qcom,x1e80100-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CB_BCR 1
#define GPUCC_GPU_CC_CX_BCR 2
#define GPUCC_GPU_CC_FAST_HUB_BCR 3
#define GPUCC_GPU_CC_FF_BCR 4
#define GPUCC_GPU_CC_GFX3D_AON_BCR 5
#define GPUCC_GPU_CC_GMU_BCR 6
#define GPUCC_GPU_CC_GX_BCR 7
#define GPUCC_GPU_CC_XO_BCR 8
#endif