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drivers: clk: Add clock controller snapshot for Kalama SoC
Add Kalama clock controller snapshot from msm-5.15 branch with base commit <a79cccfc9d06> (Merge "Revert "arm64: defconfig: Enable QCOM_DYN_MINIDUMP_STACK for kalama""). Change-Id: I7822e2910d360a76611cf900da4f9533e0593114 Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
This commit is contained in:
Vivek Aknurwar
Huang Yiwei
parent
766d3a4d9a
commit
27d471f260
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@ -817,4 +817,67 @@ config QCOM_GDSC_REGULATOR
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Say Y if you want to support clients using regulator framework APIs
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to control GDSCs.
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config SM_GCC_KALAMA
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tristate "Kalama Global Clock Controller"
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depends on COMMON_CLK_QCOM
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help
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Support for the global clock controller on Qualcomm Technologies, Inc
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Kalama devices.
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Say Y if you want to use peripheral devices such as UART, SPI, I2C,
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USB, UFS, SD/eMMC, PCIe, etc.
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config SM_VIDEOCC_KALAMA
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tristate "Kalama Video Clock Controller"
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depends on SM_GCC_KALAMA
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help
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Support for the video clock controller on Qualcomm Technologies, Inc.
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Kalama devices.
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Say Y if you want to support video devices and functionality such as
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video encode/decode.
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config SM_CAMCC_KALAMA
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tristate "Kalama Camera Clock Controller"
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depends on SM_GCC_KALAMA
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help
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Support for the camera clock controller on Qualcomm Technologies, Inc
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Kalama devices.
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Say Y if you want to support camera devices and functionality such as
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capturing pictures.
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config SM_DISPCC_KALAMA
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tristate "Kalama Display Clock Controller"
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depends on SM_GCC_KALAMA
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help
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Support for the display clock controller on Qualcomm Technologies, Inc
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Kalama devices.
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Say Y if you want to support display devices and functionality such as
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splash screen.
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config SM_DEBUGCC_KALAMA
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tristate "Kalama Debug Clock Controller"
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depends on COMMON_CLK_QCOM
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help
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Support for the debug clock controller on Qualcomm Technologies, Inc
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Kalama devices.
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Say Y if you want to support the debug clocks such as
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clock measurement functionality.
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config SM_GPUCC_KALAMA
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tristate "Kalama Graphics Clock Controller"
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depends on SM_GCC_KALAMA
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help
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Support for the graphics clock controller on Qualcomm Technologies, Inc
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Kalama devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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config SM_TCSRCC_KALAMA
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tristate "Kalama Top-Level CSR Clock Controller"
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depends on SM_GCC_KALAMA
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help
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Support for the TCSR clock controller on Qualcomm Technologies, Inc
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Kalama devices.
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Say Y if you want to support miscellaneous top-level clocks
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such as for the PHY references.
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endif
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@ -107,6 +107,13 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
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obj-$(CONFIG_SM_GCC_PINEAPPLE) += gcc-pineapple.o
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obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
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obj-$(CONFIG_SM_CAMCC_PINEAPPLE) += camcc-pineapple.o
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obj-$(CONFIG_SM_GCC_KALAMA) += gcc-kalama.o
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obj-$(CONFIG_SM_VIDEOCC_KALAMA) += videocc-kalama.o
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obj-$(CONFIG_SM_CAMCC_KALAMA) += camcc-kalama.o
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obj-$(CONFIG_SM_DISPCC_KALAMA) += dispcc-kalama.o
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obj-$(CONFIG_SM_DEBUGCC_KALAMA) += debugcc-kalama.o
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obj-$(CONFIG_SM_GPUCC_KALAMA) += gpucc-kalama.o
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obj-$(CONFIG_SM_TCSRCC_KALAMA) += tcsrcc-kalama.o
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obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
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obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
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obj-$(CONFIG_SM_GPUCC_PINEAPPLE) += gpucc-pineapple.o
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4111
drivers/clk/qcom/camcc-kalama.c
Normal file
4111
drivers/clk/qcom/camcc-kalama.c
Normal file
File diff suppressed because it is too large
Load Diff
996
drivers/clk/qcom/debugcc-kalama.c
Normal file
996
drivers/clk/qcom/debugcc-kalama.c
Normal file
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@ -0,0 +1,996 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "clk-debug.h"
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#include "common.h"
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static struct measure_clk_data debug_mux_priv = {
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.ctl_reg = 0x62048,
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.status_reg = 0x6204C,
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.xo_div4_cbcr = 0x62008,
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};
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static const char *const apss_cc_debug_mux_parent_names[] = {
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"measure_only_apcs_gold_post_acd_clk",
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"measure_only_apcs_goldplus_post_acd_clk",
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"measure_only_apcs_l3_post_acd_clk",
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"measure_only_apcs_silver_post_acd_clk",
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};
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static int apss_cc_debug_mux_sels[] = {
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0x4, /* measure_only_apcs_gold_post_acd_clk */
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0x8, /* measure_only_apcs_goldplus_post_acd_clk */
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0x6, /* measure_only_apcs_l3_post_acd_clk */
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0x2, /* measure_only_apcs_silver_post_acd_clk */
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};
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static int apss_cc_debug_mux_pre_divs[] = {
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0x8, /* measure_only_apcs_gold_post_acd_clk */
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0x8, /* measure_only_apcs_goldplus_post_acd_clk */
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0x4, /* measure_only_apcs_l3_post_acd_clk */
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0x4, /* measure_only_apcs_silver_post_acd_clk */
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};
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static struct clk_debug_mux apss_cc_debug_mux = {
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.priv = &debug_mux_priv,
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.debug_offset = 0x20100,
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.post_div_offset = 0x20104,
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.cbcr_offset = 0x20108,
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.src_sel_mask = 0xFF,
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.src_sel_shift = 0,
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.post_div_mask = 0xF,
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.post_div_shift = 0,
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.post_div_val = 4,
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.mux_sels = apss_cc_debug_mux_sels,
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.num_mux_sels = ARRAY_SIZE(apss_cc_debug_mux_sels),
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.pre_div_vals = apss_cc_debug_mux_pre_divs,
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.hw.init = &(struct clk_init_data){
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.name = "apss_cc_debug_mux",
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.ops = &clk_debug_mux_ops,
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.parent_names = apss_cc_debug_mux_parent_names,
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.num_parents = ARRAY_SIZE(apss_cc_debug_mux_parent_names),
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},
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};
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static const char *const cam_cc_debug_mux_parent_names[] = {
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"cam_cc_bps_ahb_clk",
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"cam_cc_bps_clk",
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"cam_cc_bps_fast_ahb_clk",
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"cam_cc_camnoc_axi_clk",
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"cam_cc_camnoc_dcd_xo_clk",
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"cam_cc_camnoc_xo_clk",
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"cam_cc_cci_0_clk",
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"cam_cc_cci_1_clk",
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"cam_cc_cci_2_clk",
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"cam_cc_core_ahb_clk",
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"cam_cc_cpas_ahb_clk",
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"cam_cc_cpas_bps_clk",
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"cam_cc_cpas_cre_clk",
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"cam_cc_cpas_fast_ahb_clk",
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"cam_cc_cpas_ife_0_clk",
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"cam_cc_cpas_ife_1_clk",
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"cam_cc_cpas_ife_2_clk",
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"cam_cc_cpas_ife_lite_clk",
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"cam_cc_cpas_ipe_nps_clk",
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"cam_cc_cpas_sbi_clk",
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"cam_cc_cpas_sfe_0_clk",
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"cam_cc_cpas_sfe_1_clk",
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"cam_cc_cre_ahb_clk",
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"cam_cc_cre_clk",
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"cam_cc_csi0phytimer_clk",
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"cam_cc_csi1phytimer_clk",
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"cam_cc_csi2phytimer_clk",
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"cam_cc_csi3phytimer_clk",
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"cam_cc_csi4phytimer_clk",
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"cam_cc_csi5phytimer_clk",
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"cam_cc_csi6phytimer_clk",
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"cam_cc_csi7phytimer_clk",
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"cam_cc_csid_clk",
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"cam_cc_csid_csiphy_rx_clk",
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"cam_cc_csiphy0_clk",
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"cam_cc_csiphy1_clk",
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"cam_cc_csiphy2_clk",
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"cam_cc_csiphy3_clk",
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"cam_cc_csiphy4_clk",
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"cam_cc_csiphy5_clk",
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"cam_cc_csiphy6_clk",
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"cam_cc_csiphy7_clk",
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"cam_cc_drv_ahb_clk",
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"cam_cc_drv_xo_clk",
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"cam_cc_gdsc_clk",
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"cam_cc_icp_ahb_clk",
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"cam_cc_icp_clk",
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"cam_cc_ife_0_clk",
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"cam_cc_ife_0_dsp_clk",
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"cam_cc_ife_0_fast_ahb_clk",
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"cam_cc_ife_1_clk",
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"cam_cc_ife_1_dsp_clk",
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"cam_cc_ife_1_fast_ahb_clk",
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"cam_cc_ife_2_clk",
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"cam_cc_ife_2_dsp_clk",
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"cam_cc_ife_2_fast_ahb_clk",
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"cam_cc_ife_lite_ahb_clk",
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"cam_cc_ife_lite_clk",
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"cam_cc_ife_lite_cphy_rx_clk",
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"cam_cc_ife_lite_csid_clk",
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"cam_cc_ipe_nps_ahb_clk",
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"cam_cc_ipe_nps_clk",
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"cam_cc_ipe_nps_fast_ahb_clk",
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"cam_cc_ipe_pps_clk",
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"cam_cc_ipe_pps_fast_ahb_clk",
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"cam_cc_jpeg_1_clk",
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"cam_cc_jpeg_clk",
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"cam_cc_mclk0_clk",
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"cam_cc_mclk1_clk",
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"cam_cc_mclk2_clk",
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"cam_cc_mclk3_clk",
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"cam_cc_mclk4_clk",
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"cam_cc_mclk5_clk",
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"cam_cc_mclk6_clk",
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"cam_cc_mclk7_clk",
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"cam_cc_qdss_debug_clk",
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"cam_cc_qdss_debug_xo_clk",
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"cam_cc_sbi_clk",
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"cam_cc_sbi_fast_ahb_clk",
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"cam_cc_sfe_0_clk",
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"cam_cc_sfe_0_fast_ahb_clk",
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"cam_cc_sfe_1_clk",
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"cam_cc_sfe_1_fast_ahb_clk",
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"cam_cc_sleep_clk",
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};
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static int cam_cc_debug_mux_sels[] = {
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0x17, /* cam_cc_bps_ahb_clk */
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0x18, /* cam_cc_bps_clk */
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0x16, /* cam_cc_bps_fast_ahb_clk */
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0x49, /* cam_cc_camnoc_axi_clk */
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0x4A, /* cam_cc_camnoc_dcd_xo_clk */
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0x60, /* cam_cc_camnoc_xo_clk */
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0x44, /* cam_cc_cci_0_clk */
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0x45, /* cam_cc_cci_1_clk */
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0x61, /* cam_cc_cci_2_clk */
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0x4D, /* cam_cc_core_ahb_clk */
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0x46, /* cam_cc_cpas_ahb_clk */
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0x19, /* cam_cc_cpas_bps_clk */
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0x5D, /* cam_cc_cpas_cre_clk */
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0x47, /* cam_cc_cpas_fast_ahb_clk */
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0x25, /* cam_cc_cpas_ife_0_clk */
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0x2A, /* cam_cc_cpas_ife_1_clk */
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0x2F, /* cam_cc_cpas_ife_2_clk */
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0x34, /* cam_cc_cpas_ife_lite_clk */
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0x1B, /* cam_cc_cpas_ipe_nps_clk */
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0x22, /* cam_cc_cpas_sbi_clk */
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0x39, /* cam_cc_cpas_sfe_0_clk */
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0x3D, /* cam_cc_cpas_sfe_1_clk */
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0x5E, /* cam_cc_cre_ahb_clk */
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0x5C, /* cam_cc_cre_clk */
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0x9, /* cam_cc_csi0phytimer_clk */
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0xC, /* cam_cc_csi1phytimer_clk */
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0xE, /* cam_cc_csi2phytimer_clk */
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0x10, /* cam_cc_csi3phytimer_clk */
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0x12, /* cam_cc_csi4phytimer_clk */
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0x14, /* cam_cc_csi5phytimer_clk */
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0x58, /* cam_cc_csi6phytimer_clk */
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0x5A, /* cam_cc_csi7phytimer_clk */
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0x48, /* cam_cc_csid_clk */
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0xB, /* cam_cc_csid_csiphy_rx_clk */
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0xA, /* cam_cc_csiphy0_clk */
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0xD, /* cam_cc_csiphy1_clk */
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0xF, /* cam_cc_csiphy2_clk */
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0x11, /* cam_cc_csiphy3_clk */
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0x13, /* cam_cc_csiphy4_clk */
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0x15, /* cam_cc_csiphy5_clk */
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0x59, /* cam_cc_csiphy6_clk */
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0x5B, /* cam_cc_csiphy7_clk */
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0x75, /* cam_cc_drv_ahb_clk */
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0x74, /* cam_cc_drv_xo_clk */
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0x4E, /* cam_cc_gdsc_clk */
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0x43, /* cam_cc_icp_ahb_clk */
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0x42, /* cam_cc_icp_clk */
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0x24, /* cam_cc_ife_0_clk */
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0x26, /* cam_cc_ife_0_dsp_clk */
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0x28, /* cam_cc_ife_0_fast_ahb_clk */
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0x29, /* cam_cc_ife_1_clk */
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0x2B, /* cam_cc_ife_1_dsp_clk */
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0x2D, /* cam_cc_ife_1_fast_ahb_clk */
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0x2E, /* cam_cc_ife_2_clk */
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0x30, /* cam_cc_ife_2_dsp_clk */
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0x32, /* cam_cc_ife_2_fast_ahb_clk */
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0x37, /* cam_cc_ife_lite_ahb_clk */
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0x33, /* cam_cc_ife_lite_clk */
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0x36, /* cam_cc_ife_lite_cphy_rx_clk */
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0x35, /* cam_cc_ife_lite_csid_clk */
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0x1E, /* cam_cc_ipe_nps_ahb_clk */
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0x1A, /* cam_cc_ipe_nps_clk */
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0x1F, /* cam_cc_ipe_nps_fast_ahb_clk */
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0x1C, /* cam_cc_ipe_pps_clk */
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0x20, /* cam_cc_ipe_pps_fast_ahb_clk */
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0x5F, /* cam_cc_jpeg_1_clk */
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0x40, /* cam_cc_jpeg_clk */
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0x1, /* cam_cc_mclk0_clk */
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0x2, /* cam_cc_mclk1_clk */
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0x3, /* cam_cc_mclk2_clk */
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0x4, /* cam_cc_mclk3_clk */
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0x5, /* cam_cc_mclk4_clk */
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0x6, /* cam_cc_mclk5_clk */
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0x7, /* cam_cc_mclk6_clk */
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0x8, /* cam_cc_mclk7_clk */
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0x4B, /* cam_cc_qdss_debug_clk */
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0x4C, /* cam_cc_qdss_debug_xo_clk */
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0x21, /* cam_cc_sbi_clk */
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0x23, /* cam_cc_sbi_fast_ahb_clk */
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0x38, /* cam_cc_sfe_0_clk */
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0x3B, /* cam_cc_sfe_0_fast_ahb_clk */
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0x3C, /* cam_cc_sfe_1_clk */
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0x3F, /* cam_cc_sfe_1_fast_ahb_clk */
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0x4F, /* cam_cc_sleep_clk */
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};
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static struct clk_debug_mux cam_cc_debug_mux = {
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.priv = &debug_mux_priv,
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.debug_offset = 0x16000,
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.post_div_offset = 0x14004,
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.cbcr_offset = 0x14008,
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.src_sel_mask = 0xFF,
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.src_sel_shift = 0,
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.post_div_mask = 0xF,
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.post_div_shift = 0,
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.post_div_val = 4,
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.mux_sels = cam_cc_debug_mux_sels,
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.num_mux_sels = ARRAY_SIZE(cam_cc_debug_mux_sels),
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.hw.init = &(struct clk_init_data){
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.name = "cam_cc_debug_mux",
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.ops = &clk_debug_mux_ops,
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.parent_names = cam_cc_debug_mux_parent_names,
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.num_parents = ARRAY_SIZE(cam_cc_debug_mux_parent_names),
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},
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};
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static const char *const disp_cc_debug_mux_parent_names[] = {
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"disp_cc_mdss_accu_clk",
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"disp_cc_mdss_ahb1_clk",
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"disp_cc_mdss_ahb_clk",
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"disp_cc_mdss_byte0_clk",
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"disp_cc_mdss_byte0_intf_clk",
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"disp_cc_mdss_byte1_clk",
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"disp_cc_mdss_byte1_intf_clk",
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"disp_cc_mdss_dptx0_aux_clk",
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"disp_cc_mdss_dptx0_crypto_clk",
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"disp_cc_mdss_dptx0_link_clk",
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"disp_cc_mdss_dptx0_link_intf_clk",
|
||||
"disp_cc_mdss_dptx0_pixel0_clk",
|
||||
"disp_cc_mdss_dptx0_pixel1_clk",
|
||||
"disp_cc_mdss_dptx0_usb_router_link_intf_clk",
|
||||
"disp_cc_mdss_dptx1_aux_clk",
|
||||
"disp_cc_mdss_dptx1_crypto_clk",
|
||||
"disp_cc_mdss_dptx1_link_clk",
|
||||
"disp_cc_mdss_dptx1_link_intf_clk",
|
||||
"disp_cc_mdss_dptx1_pixel0_clk",
|
||||
"disp_cc_mdss_dptx1_pixel1_clk",
|
||||
"disp_cc_mdss_dptx1_usb_router_link_intf_clk",
|
||||
"disp_cc_mdss_dptx2_aux_clk",
|
||||
"disp_cc_mdss_dptx2_crypto_clk",
|
||||
"disp_cc_mdss_dptx2_link_clk",
|
||||
"disp_cc_mdss_dptx2_link_intf_clk",
|
||||
"disp_cc_mdss_dptx2_pixel0_clk",
|
||||
"disp_cc_mdss_dptx2_pixel1_clk",
|
||||
"disp_cc_mdss_dptx3_aux_clk",
|
||||
"disp_cc_mdss_dptx3_crypto_clk",
|
||||
"disp_cc_mdss_dptx3_link_clk",
|
||||
"disp_cc_mdss_dptx3_link_intf_clk",
|
||||
"disp_cc_mdss_dptx3_pixel0_clk",
|
||||
"disp_cc_mdss_esc0_clk",
|
||||
"disp_cc_mdss_esc1_clk",
|
||||
"disp_cc_mdss_mdp1_clk",
|
||||
"disp_cc_mdss_mdp_clk",
|
||||
"disp_cc_mdss_mdp_lut1_clk",
|
||||
"disp_cc_mdss_mdp_lut_clk",
|
||||
"disp_cc_mdss_non_gdsc_ahb_clk",
|
||||
"disp_cc_mdss_pclk0_clk",
|
||||
"disp_cc_mdss_pclk1_clk",
|
||||
"disp_cc_mdss_rscc_ahb_clk",
|
||||
"disp_cc_mdss_rscc_vsync_clk",
|
||||
"disp_cc_mdss_vsync1_clk",
|
||||
"disp_cc_mdss_vsync_clk",
|
||||
"disp_cc_sleep_clk",
|
||||
"disp_cc_xo_clk",
|
||||
};
|
||||
|
||||
static int disp_cc_debug_mux_sels[] = {
|
||||
0x46, /* disp_cc_mdss_accu_clk */
|
||||
0x37, /* disp_cc_mdss_ahb1_clk */
|
||||
0x33, /* disp_cc_mdss_ahb_clk */
|
||||
0x14, /* disp_cc_mdss_byte0_clk */
|
||||
0x15, /* disp_cc_mdss_byte0_intf_clk */
|
||||
0x16, /* disp_cc_mdss_byte1_clk */
|
||||
0x17, /* disp_cc_mdss_byte1_intf_clk */
|
||||
0x20, /* disp_cc_mdss_dptx0_aux_clk */
|
||||
0x1D, /* disp_cc_mdss_dptx0_crypto_clk */
|
||||
0x1A, /* disp_cc_mdss_dptx0_link_clk */
|
||||
0x1C, /* disp_cc_mdss_dptx0_link_intf_clk */
|
||||
0x1E, /* disp_cc_mdss_dptx0_pixel0_clk */
|
||||
0x1F, /* disp_cc_mdss_dptx0_pixel1_clk */
|
||||
0x1B, /* disp_cc_mdss_dptx0_usb_router_link_intf_clk */
|
||||
0x27, /* disp_cc_mdss_dptx1_aux_clk */
|
||||
0x26, /* disp_cc_mdss_dptx1_crypto_clk */
|
||||
0x23, /* disp_cc_mdss_dptx1_link_clk */
|
||||
0x25, /* disp_cc_mdss_dptx1_link_intf_clk */
|
||||
0x21, /* disp_cc_mdss_dptx1_pixel0_clk */
|
||||
0x22, /* disp_cc_mdss_dptx1_pixel1_clk */
|
||||
0x24, /* disp_cc_mdss_dptx1_usb_router_link_intf_clk */
|
||||
0x2D, /* disp_cc_mdss_dptx2_aux_clk */
|
||||
0x2C, /* disp_cc_mdss_dptx2_crypto_clk */
|
||||
0x2A, /* disp_cc_mdss_dptx2_link_clk */
|
||||
0x2B, /* disp_cc_mdss_dptx2_link_intf_clk */
|
||||
0x28, /* disp_cc_mdss_dptx2_pixel0_clk */
|
||||
0x29, /* disp_cc_mdss_dptx2_pixel1_clk */
|
||||
0x31, /* disp_cc_mdss_dptx3_aux_clk */
|
||||
0x32, /* disp_cc_mdss_dptx3_crypto_clk */
|
||||
0x2F, /* disp_cc_mdss_dptx3_link_clk */
|
||||
0x30, /* disp_cc_mdss_dptx3_link_intf_clk */
|
||||
0x2E, /* disp_cc_mdss_dptx3_pixel0_clk */
|
||||
0x18, /* disp_cc_mdss_esc0_clk */
|
||||
0x19, /* disp_cc_mdss_esc1_clk */
|
||||
0x34, /* disp_cc_mdss_mdp1_clk */
|
||||
0x11, /* disp_cc_mdss_mdp_clk */
|
||||
0x35, /* disp_cc_mdss_mdp_lut1_clk */
|
||||
0x12, /* disp_cc_mdss_mdp_lut_clk */
|
||||
0x38, /* disp_cc_mdss_non_gdsc_ahb_clk */
|
||||
0xF, /* disp_cc_mdss_pclk0_clk */
|
||||
0x10, /* disp_cc_mdss_pclk1_clk */
|
||||
0x3A, /* disp_cc_mdss_rscc_ahb_clk */
|
||||
0x39, /* disp_cc_mdss_rscc_vsync_clk */
|
||||
0x36, /* disp_cc_mdss_vsync1_clk */
|
||||
0x13, /* disp_cc_mdss_vsync_clk */
|
||||
0x47, /* disp_cc_sleep_clk */
|
||||
0x45, /* disp_cc_xo_clk */
|
||||
};
|
||||
|
||||
static struct clk_debug_mux disp_cc_debug_mux = {
|
||||
.priv = &debug_mux_priv,
|
||||
.debug_offset = 0x11000,
|
||||
.post_div_offset = 0xD000,
|
||||
.cbcr_offset = 0xD004,
|
||||
.src_sel_mask = 0x1FF,
|
||||
.src_sel_shift = 0,
|
||||
.post_div_mask = 0xF,
|
||||
.post_div_shift = 0,
|
||||
.post_div_val = 4,
|
||||
.mux_sels = disp_cc_debug_mux_sels,
|
||||
.num_mux_sels = ARRAY_SIZE(disp_cc_debug_mux_sels),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_debug_mux",
|
||||
.ops = &clk_debug_mux_ops,
|
||||
.parent_names = disp_cc_debug_mux_parent_names,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_debug_mux_parent_names),
|
||||
},
|
||||
};
|
||||
|
||||
static const char *const gcc_debug_mux_parent_names[] = {
|
||||
"apss_cc_debug_mux",
|
||||
"cam_cc_debug_mux",
|
||||
"disp_cc_debug_mux",
|
||||
"gcc_aggre_noc_pcie_axi_clk",
|
||||
"gcc_aggre_ufs_phy_axi_clk",
|
||||
"gcc_aggre_usb3_prim_axi_clk",
|
||||
"gcc_ahb2phy_0_clk",
|
||||
"gcc_boot_rom_ahb_clk",
|
||||
"gcc_camera_ahb_clk",
|
||||
"gcc_camera_hf_axi_clk",
|
||||
"gcc_camera_sf_axi_clk",
|
||||
"gcc_camera_xo_clk",
|
||||
"gcc_cfg_noc_pcie_anoc_ahb_clk",
|
||||
"gcc_cfg_noc_usb3_prim_axi_clk",
|
||||
"gcc_cnoc_pcie_sf_axi_clk",
|
||||
"gcc_ddrss_gpu_axi_clk",
|
||||
"gcc_ddrss_pcie_sf_qtb_clk",
|
||||
"gcc_disp_ahb_clk",
|
||||
"gcc_disp_hf_axi_clk",
|
||||
"gcc_disp_xo_clk",
|
||||
"gcc_gp1_clk",
|
||||
"gcc_gp2_clk",
|
||||
"gcc_gp3_clk",
|
||||
"gcc_gpu_cfg_ahb_clk",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src",
|
||||
"gcc_gpu_memnoc_gfx_clk",
|
||||
"gcc_gpu_snoc_dvm_gfx_clk",
|
||||
"gcc_pcie_0_aux_clk",
|
||||
"gcc_pcie_0_cfg_ahb_clk",
|
||||
"gcc_pcie_0_mstr_axi_clk",
|
||||
"gcc_pcie_0_phy_rchng_clk",
|
||||
"gcc_pcie_0_pipe_clk",
|
||||
"gcc_pcie_0_slv_axi_clk",
|
||||
"gcc_pcie_0_slv_q2a_axi_clk",
|
||||
"gcc_pcie_1_aux_clk",
|
||||
"gcc_pcie_1_cfg_ahb_clk",
|
||||
"gcc_pcie_1_mstr_axi_clk",
|
||||
"gcc_pcie_1_phy_aux_clk",
|
||||
"gcc_pcie_1_phy_rchng_clk",
|
||||
"gcc_pcie_1_pipe_clk",
|
||||
"gcc_pcie_1_slv_axi_clk",
|
||||
"gcc_pcie_1_slv_q2a_axi_clk",
|
||||
"gcc_pdm2_clk",
|
||||
"gcc_pdm_ahb_clk",
|
||||
"gcc_pdm_xo4_clk",
|
||||
"gcc_qmip_camera_nrt_ahb_clk",
|
||||
"gcc_qmip_camera_rt_ahb_clk",
|
||||
"gcc_qmip_disp_ahb_clk",
|
||||
"gcc_qmip_gpu_ahb_clk",
|
||||
"gcc_qmip_pcie_ahb_clk",
|
||||
"gcc_qmip_video_cv_cpu_ahb_clk",
|
||||
"gcc_qmip_video_cvp_ahb_clk",
|
||||
"gcc_qmip_video_v_cpu_ahb_clk",
|
||||
"gcc_qmip_video_vcodec_ahb_clk",
|
||||
"gcc_qupv3_i2c_core_clk",
|
||||
"gcc_qupv3_i2c_s0_clk",
|
||||
"gcc_qupv3_i2c_s1_clk",
|
||||
"gcc_qupv3_i2c_s2_clk",
|
||||
"gcc_qupv3_i2c_s3_clk",
|
||||
"gcc_qupv3_i2c_s4_clk",
|
||||
"gcc_qupv3_i2c_s5_clk",
|
||||
"gcc_qupv3_i2c_s6_clk",
|
||||
"gcc_qupv3_i2c_s7_clk",
|
||||
"gcc_qupv3_i2c_s8_clk",
|
||||
"gcc_qupv3_i2c_s9_clk",
|
||||
"gcc_qupv3_i2c_s_ahb_clk",
|
||||
"gcc_qupv3_wrap1_core_2x_clk",
|
||||
"gcc_qupv3_wrap1_core_clk",
|
||||
"gcc_qupv3_wrap1_s0_clk",
|
||||
"gcc_qupv3_wrap1_s1_clk",
|
||||
"gcc_qupv3_wrap1_s2_clk",
|
||||
"gcc_qupv3_wrap1_s3_clk",
|
||||
"gcc_qupv3_wrap1_s4_clk",
|
||||
"gcc_qupv3_wrap1_s5_clk",
|
||||
"gcc_qupv3_wrap1_s6_clk",
|
||||
"gcc_qupv3_wrap1_s7_clk",
|
||||
"gcc_qupv3_wrap2_core_2x_clk",
|
||||
"gcc_qupv3_wrap2_core_clk",
|
||||
"gcc_qupv3_wrap2_s0_clk",
|
||||
"gcc_qupv3_wrap2_s1_clk",
|
||||
"gcc_qupv3_wrap2_s2_clk",
|
||||
"gcc_qupv3_wrap2_s3_clk",
|
||||
"gcc_qupv3_wrap2_s4_clk",
|
||||
"gcc_qupv3_wrap2_s5_clk",
|
||||
"gcc_qupv3_wrap2_s6_clk",
|
||||
"gcc_qupv3_wrap2_s7_clk",
|
||||
"gcc_qupv3_wrap_1_m_ahb_clk",
|
||||
"gcc_qupv3_wrap_1_s_ahb_clk",
|
||||
"gcc_qupv3_wrap_2_m_ahb_clk",
|
||||
"gcc_qupv3_wrap_2_s_ahb_clk",
|
||||
"gcc_sdcc2_ahb_clk",
|
||||
"gcc_sdcc2_apps_clk",
|
||||
"gcc_sdcc4_ahb_clk",
|
||||
"gcc_sdcc4_apps_clk",
|
||||
"gcc_ufs_phy_ahb_clk",
|
||||
"gcc_ufs_phy_axi_clk",
|
||||
"gcc_ufs_phy_ice_core_clk",
|
||||
"gcc_ufs_phy_phy_aux_clk",
|
||||
"gcc_ufs_phy_rx_symbol_0_clk",
|
||||
"gcc_ufs_phy_rx_symbol_1_clk",
|
||||
"gcc_ufs_phy_tx_symbol_0_clk",
|
||||
"gcc_ufs_phy_unipro_core_clk",
|
||||
"gcc_usb30_prim_master_clk",
|
||||
"gcc_usb30_prim_mock_utmi_clk",
|
||||
"gcc_usb30_prim_sleep_clk",
|
||||
"gcc_usb3_prim_phy_aux_clk",
|
||||
"gcc_usb3_prim_phy_com_aux_clk",
|
||||
"gcc_usb3_prim_phy_pipe_clk",
|
||||
"gcc_video_ahb_clk",
|
||||
"gcc_video_axi0_clk",
|
||||
"gcc_video_axi1_clk",
|
||||
"gcc_video_xo_clk",
|
||||
"gpu_cc_debug_mux",
|
||||
"measure_only_cnoc_clk",
|
||||
"measure_only_ipa_2x_clk",
|
||||
"measure_only_memnoc_clk",
|
||||
"measure_only_snoc_clk",
|
||||
"pcie_0_pipe_clk",
|
||||
"pcie_1_phy_aux_clk",
|
||||
"pcie_1_pipe_clk",
|
||||
"ufs_phy_rx_symbol_0_clk",
|
||||
"ufs_phy_rx_symbol_1_clk",
|
||||
"ufs_phy_tx_symbol_0_clk",
|
||||
"usb3_phy_wrapper_gcc_usb30_pipe_clk",
|
||||
"video_cc_debug_mux",
|
||||
"mc_cc_debug_mux",
|
||||
};
|
||||
|
||||
static int gcc_debug_mux_sels[] = {
|
||||
0x122, /* apss_cc_debug_mux */
|
||||
0x69, /* cam_cc_debug_mux */
|
||||
0x6E, /* disp_cc_debug_mux */
|
||||
0x3E, /* gcc_aggre_noc_pcie_axi_clk */
|
||||
0x40, /* gcc_aggre_ufs_phy_axi_clk */
|
||||
0x3F, /* gcc_aggre_usb3_prim_axi_clk */
|
||||
0x9A, /* gcc_ahb2phy_0_clk */
|
||||
0xD7, /* gcc_boot_rom_ahb_clk */
|
||||
0x61, /* gcc_camera_ahb_clk */
|
||||
0x64, /* gcc_camera_hf_axi_clk */
|
||||
0x66, /* gcc_camera_sf_axi_clk */
|
||||
0x68, /* gcc_camera_xo_clk */
|
||||
0x2C, /* gcc_cfg_noc_pcie_anoc_ahb_clk */
|
||||
0x1F, /* gcc_cfg_noc_usb3_prim_axi_clk */
|
||||
0x19, /* gcc_cnoc_pcie_sf_axi_clk */
|
||||
0xF1, /* gcc_ddrss_gpu_axi_clk */
|
||||
0xF2, /* gcc_ddrss_pcie_sf_qtb_clk */
|
||||
0x6A, /* gcc_disp_ahb_clk */
|
||||
0x6C, /* gcc_disp_hf_axi_clk */
|
||||
0x6D, /* gcc_disp_xo_clk */
|
||||
0x12F, /* gcc_gp1_clk */
|
||||
0x130, /* gcc_gp2_clk */
|
||||
0x131, /* gcc_gp3_clk */
|
||||
0x175, /* gcc_gpu_cfg_ahb_clk */
|
||||
0x17C, /* gcc_gpu_gpll0_clk_src */
|
||||
0x17D, /* gcc_gpu_gpll0_div_clk_src */
|
||||
0x179, /* gcc_gpu_memnoc_gfx_clk */
|
||||
0x17B, /* gcc_gpu_snoc_dvm_gfx_clk */
|
||||
0x137, /* gcc_pcie_0_aux_clk */
|
||||
0x136, /* gcc_pcie_0_cfg_ahb_clk */
|
||||
0x135, /* gcc_pcie_0_mstr_axi_clk */
|
||||
0x139, /* gcc_pcie_0_phy_rchng_clk */
|
||||
0x138, /* gcc_pcie_0_pipe_clk */
|
||||
0x134, /* gcc_pcie_0_slv_axi_clk */
|
||||
0x133, /* gcc_pcie_0_slv_q2a_axi_clk */
|
||||
0x140, /* gcc_pcie_1_aux_clk */
|
||||
0x13F, /* gcc_pcie_1_cfg_ahb_clk */
|
||||
0x13E, /* gcc_pcie_1_mstr_axi_clk */
|
||||
0x141, /* gcc_pcie_1_phy_aux_clk */
|
||||
0x143, /* gcc_pcie_1_phy_rchng_clk */
|
||||
0x142, /* gcc_pcie_1_pipe_clk */
|
||||
0x13D, /* gcc_pcie_1_slv_axi_clk */
|
||||
0x13C, /* gcc_pcie_1_slv_q2a_axi_clk */
|
||||
0xC8, /* gcc_pdm2_clk */
|
||||
0xC6, /* gcc_pdm_ahb_clk */
|
||||
0xC7, /* gcc_pdm_xo4_clk */
|
||||
0x62, /* gcc_qmip_camera_nrt_ahb_clk */
|
||||
0x63, /* gcc_qmip_camera_rt_ahb_clk */
|
||||
0x6B, /* gcc_qmip_disp_ahb_clk */
|
||||
0x176, /* gcc_qmip_gpu_ahb_clk */
|
||||
0x132, /* gcc_qmip_pcie_ahb_clk */
|
||||
0x73, /* gcc_qmip_video_cv_cpu_ahb_clk */
|
||||
0x70, /* gcc_qmip_video_cvp_ahb_clk */
|
||||
0x72, /* gcc_qmip_video_v_cpu_ahb_clk */
|
||||
0x71, /* gcc_qmip_video_vcodec_ahb_clk */
|
||||
0xA2, /* gcc_qupv3_i2c_core_clk */
|
||||
0xA3, /* gcc_qupv3_i2c_s0_clk */
|
||||
0xA4, /* gcc_qupv3_i2c_s1_clk */
|
||||
0xA5, /* gcc_qupv3_i2c_s2_clk */
|
||||
0xA6, /* gcc_qupv3_i2c_s3_clk */
|
||||
0xA7, /* gcc_qupv3_i2c_s4_clk */
|
||||
0xA8, /* gcc_qupv3_i2c_s5_clk */
|
||||
0xA9, /* gcc_qupv3_i2c_s6_clk */
|
||||
0xAA, /* gcc_qupv3_i2c_s7_clk */
|
||||
0xAB, /* gcc_qupv3_i2c_s8_clk */
|
||||
0xAC, /* gcc_qupv3_i2c_s9_clk */
|
||||
0xA1, /* gcc_qupv3_i2c_s_ahb_clk */
|
||||
0xB0, /* gcc_qupv3_wrap1_core_2x_clk */
|
||||
0xAF, /* gcc_qupv3_wrap1_core_clk */
|
||||
0xB2, /* gcc_qupv3_wrap1_s0_clk */
|
||||
0xB3, /* gcc_qupv3_wrap1_s1_clk */
|
||||
0xB4, /* gcc_qupv3_wrap1_s2_clk */
|
||||
0xB5, /* gcc_qupv3_wrap1_s3_clk */
|
||||
0xB6, /* gcc_qupv3_wrap1_s4_clk */
|
||||
0xB7, /* gcc_qupv3_wrap1_s5_clk */
|
||||
0xB8, /* gcc_qupv3_wrap1_s6_clk */
|
||||
0xB9, /* gcc_qupv3_wrap1_s7_clk */
|
||||
0xBD, /* gcc_qupv3_wrap2_core_2x_clk */
|
||||
0xBC, /* gcc_qupv3_wrap2_core_clk */
|
||||
0xBE, /* gcc_qupv3_wrap2_s0_clk */
|
||||
0xBF, /* gcc_qupv3_wrap2_s1_clk */
|
||||
0xC0, /* gcc_qupv3_wrap2_s2_clk */
|
||||
0xC1, /* gcc_qupv3_wrap2_s3_clk */
|
||||
0xC2, /* gcc_qupv3_wrap2_s4_clk */
|
||||
0xC3, /* gcc_qupv3_wrap2_s5_clk */
|
||||
0xC4, /* gcc_qupv3_wrap2_s6_clk */
|
||||
0xC5, /* gcc_qupv3_wrap2_s7_clk */
|
||||
0xAD, /* gcc_qupv3_wrap_1_m_ahb_clk */
|
||||
0xAE, /* gcc_qupv3_wrap_1_s_ahb_clk */
|
||||
0xBA, /* gcc_qupv3_wrap_2_m_ahb_clk */
|
||||
0xBB, /* gcc_qupv3_wrap_2_s_ahb_clk */
|
||||
0x9C, /* gcc_sdcc2_ahb_clk */
|
||||
0x9B, /* gcc_sdcc2_apps_clk */
|
||||
0x9F, /* gcc_sdcc4_ahb_clk */
|
||||
0x9E, /* gcc_sdcc4_apps_clk */
|
||||
0x148, /* gcc_ufs_phy_ahb_clk */
|
||||
0x147, /* gcc_ufs_phy_axi_clk */
|
||||
0x14E, /* gcc_ufs_phy_ice_core_clk */
|
||||
0x14F, /* gcc_ufs_phy_phy_aux_clk */
|
||||
0x14A, /* gcc_ufs_phy_rx_symbol_0_clk */
|
||||
0x150, /* gcc_ufs_phy_rx_symbol_1_clk */
|
||||
0x149, /* gcc_ufs_phy_tx_symbol_0_clk */
|
||||
0x14D, /* gcc_ufs_phy_unipro_core_clk */
|
||||
0x8E, /* gcc_usb30_prim_master_clk */
|
||||
0x90, /* gcc_usb30_prim_mock_utmi_clk */
|
||||
0x8F, /* gcc_usb30_prim_sleep_clk */
|
||||
0x91, /* gcc_usb3_prim_phy_aux_clk */
|
||||
0x92, /* gcc_usb3_prim_phy_com_aux_clk */
|
||||
0x93, /* gcc_usb3_prim_phy_pipe_clk */
|
||||
0x6F, /* gcc_video_ahb_clk */
|
||||
0x74, /* gcc_video_axi0_clk */
|
||||
0x75, /* gcc_video_axi1_clk */
|
||||
0x76, /* gcc_video_xo_clk */
|
||||
0x178, /* gpu_cc_debug_mux */
|
||||
0x17, /* measure_only_cnoc_clk */
|
||||
0x161, /* measure_only_ipa_2x_clk */
|
||||
0xF7, /* measure_only_memnoc_clk */
|
||||
0xB, /* measure_only_snoc_clk */
|
||||
0x13A, /* pcie_0_pipe_clk */
|
||||
0x145, /* pcie_1_phy_aux_clk */
|
||||
0x144, /* pcie_1_pipe_clk */
|
||||
0x14C, /* ufs_phy_rx_symbol_0_clk */
|
||||
0x152, /* ufs_phy_rx_symbol_1_clk */
|
||||
0x14B, /* ufs_phy_tx_symbol_0_clk */
|
||||
0x97, /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
|
||||
0x77, /* video_cc_debug_mux */
|
||||
0xFD, /* mc_cc_debug_mux or ddrss_gcc_debug_clk */
|
||||
};
|
||||
|
||||
static struct clk_debug_mux gcc_debug_mux = {
|
||||
.priv = &debug_mux_priv,
|
||||
.debug_offset = 0x62024,
|
||||
.post_div_offset = 0x62000,
|
||||
.cbcr_offset = 0x62004,
|
||||
.src_sel_mask = 0x3FF,
|
||||
.src_sel_shift = 0,
|
||||
.post_div_mask = 0xF,
|
||||
.post_div_shift = 0,
|
||||
.post_div_val = 2,
|
||||
.mux_sels = gcc_debug_mux_sels,
|
||||
.num_mux_sels = ARRAY_SIZE(gcc_debug_mux_sels),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_debug_mux",
|
||||
.ops = &clk_debug_mux_ops,
|
||||
.parent_names = gcc_debug_mux_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gcc_debug_mux_parent_names),
|
||||
},
|
||||
};
|
||||
|
||||
static const char *const gpu_cc_debug_mux_parent_names[] = {
|
||||
"gpu_cc_ahb_clk",
|
||||
"gpu_cc_crc_ahb_clk",
|
||||
"gpu_cc_cx_ff_clk",
|
||||
"gpu_cc_cx_gmu_clk",
|
||||
"gpu_cc_cxo_aon_clk",
|
||||
"gpu_cc_cxo_clk",
|
||||
"gpu_cc_demet_clk",
|
||||
"gpu_cc_freq_measure_clk",
|
||||
"gpu_cc_gx_ff_clk",
|
||||
"gpu_cc_gx_gfx3d_rdvm_clk",
|
||||
"gpu_cc_gx_gmu_clk",
|
||||
"gpu_cc_gx_vsense_clk",
|
||||
"gpu_cc_hub_aon_clk",
|
||||
"gpu_cc_hub_cx_int_clk",
|
||||
"gpu_cc_memnoc_gfx_clk",
|
||||
"gpu_cc_mnd1x_0_gfx3d_clk",
|
||||
"gpu_cc_mnd1x_1_gfx3d_clk",
|
||||
"gpu_cc_sleep_clk",
|
||||
"measure_only_gpu_cc_cx_gfx3d_clk",
|
||||
"measure_only_gpu_cc_cx_gfx3d_slv_clk",
|
||||
"measure_only_gpu_cc_gx_gfx3d_clk",
|
||||
};
|
||||
|
||||
static int gpu_cc_debug_mux_sels[] = {
|
||||
0x16, /* gpu_cc_ahb_clk */
|
||||
0x17, /* gpu_cc_crc_ahb_clk */
|
||||
0x20, /* gpu_cc_cx_ff_clk */
|
||||
0x1D, /* gpu_cc_cx_gmu_clk */
|
||||
0xB, /* gpu_cc_cxo_aon_clk */
|
||||
0x1E, /* gpu_cc_cxo_clk */
|
||||
0xD, /* gpu_cc_demet_clk */
|
||||
0xC, /* gpu_cc_freq_measure_clk */
|
||||
0x13, /* gpu_cc_gx_ff_clk */
|
||||
0x15, /* gpu_cc_gx_gfx3d_rdvm_clk */
|
||||
0x12, /* gpu_cc_gx_gmu_clk */
|
||||
0xF, /* gpu_cc_gx_vsense_clk */
|
||||
0x2D, /* gpu_cc_hub_aon_clk */
|
||||
0x1F, /* gpu_cc_hub_cx_int_clk */
|
||||
0x21, /* gpu_cc_memnoc_gfx_clk */
|
||||
0x28, /* gpu_cc_mnd1x_0_gfx3d_clk */
|
||||
0x29, /* gpu_cc_mnd1x_1_gfx3d_clk */
|
||||
0x1B, /* gpu_cc_sleep_clk */
|
||||
0x24, /* measure_only_gpu_cc_cx_gfx3d_clk */
|
||||
0x25, /* measure_only_gpu_cc_cx_gfx3d_slv_clk */
|
||||
0xE, /* measure_only_gpu_cc_gx_gfx3d_clk */
|
||||
};
|
||||
|
||||
static struct clk_debug_mux gpu_cc_debug_mux = {
|
||||
.priv = &debug_mux_priv,
|
||||
.debug_offset = 0x9564,
|
||||
.post_div_offset = 0x9270,
|
||||
.cbcr_offset = 0x9274,
|
||||
.src_sel_mask = 0xFF,
|
||||
.src_sel_shift = 0,
|
||||
.post_div_mask = 0xF,
|
||||
.post_div_shift = 0,
|
||||
.post_div_val = 2,
|
||||
.mux_sels = gpu_cc_debug_mux_sels,
|
||||
.num_mux_sels = ARRAY_SIZE(gpu_cc_debug_mux_sels),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_debug_mux",
|
||||
.ops = &clk_debug_mux_ops,
|
||||
.parent_names = gpu_cc_debug_mux_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_debug_mux_parent_names),
|
||||
},
|
||||
};
|
||||
|
||||
static const char *const video_cc_debug_mux_parent_names[] = {
|
||||
"video_cc_ahb_clk",
|
||||
"video_cc_mvs0_clk",
|
||||
"video_cc_mvs0c_clk",
|
||||
"video_cc_mvs1_clk",
|
||||
"video_cc_mvs1c_clk",
|
||||
"video_cc_sleep_clk",
|
||||
"video_cc_xo_clk",
|
||||
};
|
||||
|
||||
static int video_cc_debug_mux_sels[] = {
|
||||
0x7, /* video_cc_ahb_clk */
|
||||
0x3, /* video_cc_mvs0_clk */
|
||||
0x1, /* video_cc_mvs0c_clk */
|
||||
0x5, /* video_cc_mvs1_clk */
|
||||
0x9, /* video_cc_mvs1c_clk */
|
||||
0xC, /* video_cc_sleep_clk */
|
||||
0xB, /* video_cc_xo_clk */
|
||||
};
|
||||
|
||||
static struct clk_debug_mux video_cc_debug_mux = {
|
||||
.priv = &debug_mux_priv,
|
||||
.debug_offset = 0x9A4C,
|
||||
.post_div_offset = 0x80F8,
|
||||
.cbcr_offset = 0x80FC,
|
||||
.src_sel_mask = 0x3F,
|
||||
.src_sel_shift = 0,
|
||||
.post_div_mask = 0xF,
|
||||
.post_div_shift = 0,
|
||||
.post_div_val = 3,
|
||||
.mux_sels = video_cc_debug_mux_sels,
|
||||
.num_mux_sels = ARRAY_SIZE(video_cc_debug_mux_sels),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_debug_mux",
|
||||
.ops = &clk_debug_mux_ops,
|
||||
.parent_names = video_cc_debug_mux_parent_names,
|
||||
.num_parents = ARRAY_SIZE(video_cc_debug_mux_parent_names),
|
||||
},
|
||||
};
|
||||
|
||||
static const char *const mc_cc_debug_mux_parent_names[] = {
|
||||
"measure_only_mccc_clk",
|
||||
};
|
||||
|
||||
static struct clk_debug_mux mc_cc_debug_mux = {
|
||||
.period_offset = 0x50,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mc_cc_debug_mux",
|
||||
.ops = &clk_debug_mux_ops,
|
||||
.parent_names = mc_cc_debug_mux_parent_names,
|
||||
.num_parents = ARRAY_SIZE(mc_cc_debug_mux_parent_names),
|
||||
},
|
||||
};
|
||||
|
||||
static struct mux_regmap_names mux_list[] = {
|
||||
{ .mux = &mc_cc_debug_mux, .regmap_name = "qcom,mccc" },
|
||||
{ .mux = &video_cc_debug_mux, .regmap_name = "qcom,videocc" },
|
||||
{ .mux = &gpu_cc_debug_mux, .regmap_name = "qcom,gpucc" },
|
||||
{ .mux = &disp_cc_debug_mux, .regmap_name = "qcom,dispcc" },
|
||||
{ .mux = &cam_cc_debug_mux, .regmap_name = "qcom,camcc" },
|
||||
{ .mux = &apss_cc_debug_mux, .regmap_name = "qcom,apsscc" },
|
||||
{ .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" },
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_apcs_gold_post_acd_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_apcs_gold_post_acd_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_apcs_goldplus_post_acd_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_apcs_goldplus_post_acd_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_apcs_l3_post_acd_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_apcs_l3_post_acd_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_apcs_silver_post_acd_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_apcs_silver_post_acd_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_cnoc_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_cnoc_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_gpu_cc_cx_gfx3d_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_slv_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_gpu_cc_cx_gfx3d_slv_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_gpu_cc_gx_gfx3d_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_gpu_cc_gx_gfx3d_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_mccc_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_mccc_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_ipa_2x_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_ipa_2x_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_memnoc_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_memnoc_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_snoc_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_snoc_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_hw *debugcc_kalama_hws[] = {
|
||||
&measure_only_apcs_gold_post_acd_clk.hw,
|
||||
&measure_only_apcs_goldplus_post_acd_clk.hw,
|
||||
&measure_only_apcs_l3_post_acd_clk.hw,
|
||||
&measure_only_apcs_silver_post_acd_clk.hw,
|
||||
&measure_only_cnoc_clk.hw,
|
||||
&measure_only_gpu_cc_cx_gfx3d_clk.hw,
|
||||
&measure_only_gpu_cc_cx_gfx3d_slv_clk.hw,
|
||||
&measure_only_gpu_cc_gx_gfx3d_clk.hw,
|
||||
&measure_only_mccc_clk.hw,
|
||||
&measure_only_ipa_2x_clk.hw,
|
||||
&measure_only_memnoc_clk.hw,
|
||||
&measure_only_snoc_clk.hw,
|
||||
};
|
||||
|
||||
static const struct of_device_id clk_debug_match_table[] = {
|
||||
{ .compatible = "qcom,kalama-debugcc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int clk_debug_kalama_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret = 0, i;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(apss_cc_debug_mux_parent_names) !=
|
||||
ARRAY_SIZE(apss_cc_debug_mux_sels));
|
||||
BUILD_BUG_ON(ARRAY_SIZE(cam_cc_debug_mux_parent_names) !=
|
||||
ARRAY_SIZE(cam_cc_debug_mux_sels));
|
||||
BUILD_BUG_ON(ARRAY_SIZE(disp_cc_debug_mux_parent_names) !=
|
||||
ARRAY_SIZE(disp_cc_debug_mux_sels));
|
||||
BUILD_BUG_ON(ARRAY_SIZE(gcc_debug_mux_parent_names) != ARRAY_SIZE(gcc_debug_mux_sels));
|
||||
BUILD_BUG_ON(ARRAY_SIZE(gpu_cc_debug_mux_parent_names) !=
|
||||
ARRAY_SIZE(gpu_cc_debug_mux_sels));
|
||||
BUILD_BUG_ON(ARRAY_SIZE(video_cc_debug_mux_parent_names) !=
|
||||
ARRAY_SIZE(video_cc_debug_mux_sels));
|
||||
|
||||
clk = devm_clk_get(&pdev->dev, "xo_clk_src");
|
||||
if (IS_ERR(clk)) {
|
||||
if (PTR_ERR(clk) != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Unable to get xo clock\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
debug_mux_priv.cxo = clk;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
|
||||
if (IS_ERR_OR_NULL(mux_list[i].mux->regmap)) {
|
||||
ret = map_debug_bases(pdev,
|
||||
mux_list[i].regmap_name, mux_list[i].mux);
|
||||
if (ret == -EBADR)
|
||||
continue;
|
||||
else if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(debugcc_kalama_hws); i++) {
|
||||
clk = devm_clk_register(&pdev->dev, debugcc_kalama_hws[i]);
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
|
||||
clk_hw_get_name(debugcc_kalama_hws[i]),
|
||||
PTR_ERR(clk));
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
|
||||
ret = devm_clk_register_debug_mux(&pdev->dev, mux_list[i].mux);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Unable to register mux clk %s, err:(%d)\n",
|
||||
qcom_clk_hw_get_name(&mux_list[i].mux->hw),
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_debug_measure_register(&gcc_debug_mux.hw);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Could not register Measure clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "Registered debug measure clocks\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_debug_driver = {
|
||||
.probe = clk_debug_kalama_probe,
|
||||
.driver = {
|
||||
.name = "kalama-debugcc",
|
||||
.of_match_table = clk_debug_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init clk_debug_kalama_init(void)
|
||||
{
|
||||
return platform_driver_register(&clk_debug_driver);
|
||||
}
|
||||
fs_initcall(clk_debug_kalama_init);
|
||||
|
||||
MODULE_DESCRIPTION("QTI DEBUG CC KALAMA Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
2029
drivers/clk/qcom/dispcc-kalama.c
Normal file
2029
drivers/clk/qcom/dispcc-kalama.c
Normal file
File diff suppressed because it is too large
Load Diff
3915
drivers/clk/qcom/gcc-kalama.c
Normal file
3915
drivers/clk/qcom/gcc-kalama.c
Normal file
File diff suppressed because it is too large
Load Diff
687
drivers/clk/qcom/gpucc-kalama.c
Normal file
687
drivers/clk/qcom/gpucc-kalama.c
Normal file
|
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@ -0,0 +1,687 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,gpucc-kalama.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-pll.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "common.h"
|
||||
#include "reset.h"
|
||||
#include "vdd-level.h"
|
||||
|
||||
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner);
|
||||
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH + 1, 1, vdd_corner);
|
||||
static DEFINE_VDD_REGULATORS(vdd_mxc, VDD_HIGH + 1, 1, vdd_corner);
|
||||
|
||||
static struct clk_vdd_class *gpu_cc_kalama_regulators[] = {
|
||||
&vdd_cx,
|
||||
&vdd_mx,
|
||||
&vdd_mxc,
|
||||
};
|
||||
|
||||
static struct clk_vdd_class *gpu_cc_kalama_regulators_1[] = {
|
||||
&vdd_cx,
|
||||
&vdd_mx,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_GPLL0_OUT_MAIN,
|
||||
P_GPLL0_OUT_MAIN_DIV,
|
||||
P_GPU_CC_PLL0_OUT_MAIN,
|
||||
P_GPU_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_ole_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll0_config = {
|
||||
.l = 0x1E,
|
||||
.cal_l = 0x44,
|
||||
.cal_l_ringosc = 0x44,
|
||||
.alpha = 0xBAAA,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82AA299C,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_ole_ops,
|
||||
},
|
||||
.vdd_data = {
|
||||
.vdd_class = &vdd_mxc,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 615000000,
|
||||
[VDD_LOW] = 1100000000,
|
||||
[VDD_LOW_L1] = 1600000000,
|
||||
[VDD_NOMINAL] = 2000000000},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config gpu_cc_pll1_config = {
|
||||
.l = 0x16,
|
||||
.cal_l = 0x44,
|
||||
.cal_l_ringosc = 0x44,
|
||||
.alpha = 0xEAAA,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82AA299C,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll gpu_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_ole_ops,
|
||||
},
|
||||
.vdd_data = {
|
||||
.vdd_class = &vdd_mx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 615000000,
|
||||
[VDD_LOW] = 1100000000,
|
||||
[VDD_LOW_L1] = 1600000000,
|
||||
[VDD_NOMINAL] = 2000000000},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "gpll0_out_main" },
|
||||
{ .fw_name = "gpll0_out_main_div" },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &gpu_cc_pll0.clkr.hw },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .fw_name = "gpll0_out_main" },
|
||||
{ .fw_name = "gpll0_out_main_div" },
|
||||
};
|
||||
|
||||
static const struct parent_map gpu_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .fw_name = "gpll0_out_main" },
|
||||
{ .fw_name = "gpll0_out_main_div" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_ff_clk_src = {
|
||||
.cmd_rcgr = 0x9474,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.flags = HW_CLK_CTRL_MODE,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ff_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 200000000},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
||||
F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.cmd_rcgr = 0x9318,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.flags = HW_CLK_CTRL_MODE,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_classes = gpu_cc_kalama_regulators_1,
|
||||
.num_vdd_classes = ARRAY_SIZE(gpu_cc_kalama_regulators_1),
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 220000000,
|
||||
[VDD_LOW] = 550000000},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
|
||||
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
|
||||
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
|
||||
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gpu_cc_hub_clk_src = {
|
||||
.cmd_rcgr = 0x93ec,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = gpu_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.flags = HW_CLK_CTRL_MODE,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_cx,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 200000000,
|
||||
[VDD_LOW] = 300000000,
|
||||
[VDD_NOMINAL] = 400000000},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_ahb_clk = {
|
||||
.halt_reg = 0x911c,
|
||||
.halt_check = BRANCH_HALT_DELAY,
|
||||
.clkr = {
|
||||
.enable_reg = 0x911c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
||||
.halt_reg = 0x9120,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9120,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_crc_ahb_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_ff_clk = {
|
||||
.halt_reg = 0x914c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x914c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
||||
.halt_reg = 0x913c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x913c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_aon_clk = {
|
||||
.halt_reg = 0x9004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_aon_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_cxo_clk = {
|
||||
.halt_reg = 0x9144,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9144,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_cxo_clk",
|
||||
.flags = CLK_DONT_HOLD_STATE,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_demet_clk = {
|
||||
.halt_reg = 0x900c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x900c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_demet_clk",
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_freq_measure_clk = {
|
||||
.halt_reg = 0x9008,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9008,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_freq_measure_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_ff_clk = {
|
||||
.halt_reg = 0x90c0,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90c0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_ff_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_ff_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
|
||||
.halt_reg = 0x90a8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90a8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
|
||||
.halt_reg = 0x90c8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90c8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
||||
.halt_reg = 0x90bc,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90bc,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_gmu_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_gmu_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_gx_vsense_clk = {
|
||||
.halt_reg = 0x90b0,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x90b0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gx_vsense_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
|
||||
.halt_reg = 0x7000,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x7000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_aon_clk = {
|
||||
.halt_reg = 0x93e8,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x93e8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_aon_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_hub_cx_int_clk = {
|
||||
.halt_reg = 0x9148,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9148,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_hub_cx_int_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gpu_cc_hub_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE,
|
||||
.ops = &clk_branch2_aon_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
|
||||
.halt_reg = 0x9150,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9150,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_memnoc_gfx_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
|
||||
.halt_reg = 0x9288,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9288,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
|
||||
.halt_reg = 0x928c,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x928c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gpu_cc_sleep_clk = {
|
||||
.halt_reg = 0x9134,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x9134,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_sleep_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_kalama_clocks[] = {
|
||||
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
||||
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
||||
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
|
||||
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
||||
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
||||
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
||||
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
|
||||
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
|
||||
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
|
||||
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
||||
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
|
||||
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
|
||||
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
||||
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
|
||||
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
|
||||
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
|
||||
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
|
||||
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
|
||||
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
|
||||
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
|
||||
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
|
||||
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
|
||||
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
||||
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gpu_cc_kalama_resets[] = {
|
||||
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
|
||||
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
|
||||
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
|
||||
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
|
||||
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
|
||||
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
|
||||
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
|
||||
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
|
||||
};
|
||||
|
||||
static const struct regmap_config gpu_cc_kalama_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x9988,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gpu_cc_kalama_desc = {
|
||||
.config = &gpu_cc_kalama_regmap_config,
|
||||
.clks = gpu_cc_kalama_clocks,
|
||||
.num_clks = ARRAY_SIZE(gpu_cc_kalama_clocks),
|
||||
.resets = gpu_cc_kalama_resets,
|
||||
.num_resets = ARRAY_SIZE(gpu_cc_kalama_resets),
|
||||
.clk_regulators = gpu_cc_kalama_regulators,
|
||||
.num_clk_regulators = ARRAY_SIZE(gpu_cc_kalama_regulators),
|
||||
};
|
||||
|
||||
static const struct of_device_id gpu_cc_kalama_match_table[] = {
|
||||
{ .compatible = "qcom,kalama-gpucc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpu_cc_kalama_match_table);
|
||||
|
||||
static int gpu_cc_kalama_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gpu_cc_kalama_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
||||
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &gpu_cc_kalama_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "Registered GPU CC clocks\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void gpu_cc_kalama_sync_state(struct device *dev)
|
||||
{
|
||||
qcom_cc_sync_state(dev, &gpu_cc_kalama_desc);
|
||||
}
|
||||
|
||||
static struct platform_driver gpu_cc_kalama_driver = {
|
||||
.probe = gpu_cc_kalama_probe,
|
||||
.driver = {
|
||||
.name = "gpu_cc-kalama",
|
||||
.of_match_table = gpu_cc_kalama_match_table,
|
||||
.sync_state = gpu_cc_kalama_sync_state,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init gpu_cc_kalama_init(void)
|
||||
{
|
||||
return platform_driver_register(&gpu_cc_kalama_driver);
|
||||
}
|
||||
subsys_initcall(gpu_cc_kalama_init);
|
||||
|
||||
static void __exit gpu_cc_kalama_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&gpu_cc_kalama_driver);
|
||||
}
|
||||
module_exit(gpu_cc_kalama_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI GPU_CC KALAMA Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
182
drivers/clk/qcom/tcsrcc-kalama.c
Normal file
182
drivers/clk/qcom/tcsrcc-kalama.c
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,tcsrcc-kalama.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-pll.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "common.h"
|
||||
#include "reset.h"
|
||||
#include "vdd-level.h"
|
||||
|
||||
static struct clk_branch tcsr_pcie_0_clkref_en = {
|
||||
.halt_reg = 0x15100,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x15100,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_pcie_0_clkref_en",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_pcie_1_clkref_en = {
|
||||
.halt_reg = 0x15114,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x15114,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_pcie_1_clkref_en",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_ufs_clkref_en = {
|
||||
.halt_reg = 0x15110,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x15110,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_ufs_clkref_en",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_ufs_pad_clkref_en = {
|
||||
.halt_reg = 0x15104,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x15104,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_ufs_pad_clkref_en",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_usb2_clkref_en = {
|
||||
.halt_reg = 0x15118,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x15118,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_usb2_clkref_en",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch tcsr_usb3_clkref_en = {
|
||||
.halt_reg = 0x15108,
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x15108,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tcsr_usb3_clkref_en",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap *tcsr_cc_kalama_clocks[] = {
|
||||
[TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
|
||||
[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
|
||||
[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
|
||||
[TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr,
|
||||
[TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
|
||||
[TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
|
||||
};
|
||||
|
||||
static const struct regmap_config tcsr_cc_kalama_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x2f000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc tcsr_cc_kalama_desc = {
|
||||
.config = &tcsr_cc_kalama_regmap_config,
|
||||
.clks = tcsr_cc_kalama_clocks,
|
||||
.num_clks = ARRAY_SIZE(tcsr_cc_kalama_clocks),
|
||||
};
|
||||
|
||||
static const struct of_device_id tcsr_cc_kalama_match_table[] = {
|
||||
{ .compatible = "qcom,kalama-tcsrcc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tcsr_cc_kalama_match_table);
|
||||
|
||||
static int tcsr_cc_kalama_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &tcsr_cc_kalama_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &tcsr_cc_kalama_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register TCSR CC clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "Registered TCSR CC clocks\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void tcsr_cc_kalama_sync_state(struct device *dev)
|
||||
{
|
||||
qcom_cc_sync_state(dev, &tcsr_cc_kalama_desc);
|
||||
}
|
||||
|
||||
static struct platform_driver tcsr_cc_kalama_driver = {
|
||||
.probe = tcsr_cc_kalama_probe,
|
||||
.driver = {
|
||||
.name = "tcsr_cc-kalama",
|
||||
.of_match_table = tcsr_cc_kalama_match_table,
|
||||
.sync_state = tcsr_cc_kalama_sync_state,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init tcsr_cc_kalama_init(void)
|
||||
{
|
||||
return platform_driver_register(&tcsr_cc_kalama_driver);
|
||||
}
|
||||
subsys_initcall(tcsr_cc_kalama_init);
|
||||
|
||||
static void __exit tcsr_cc_kalama_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tcsr_cc_kalama_driver);
|
||||
}
|
||||
module_exit(tcsr_cc_kalama_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI TCSR_CC KALAMA Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
670
drivers/clk/qcom/videocc-kalama.c
Normal file
670
drivers/clk/qcom/videocc-kalama.c
Normal file
|
|
@ -0,0 +1,670 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,videocc-kalama.h>
|
||||
|
||||
#include "clk-alpha-pll.h"
|
||||
#include "clk-branch.h"
|
||||
#include "clk-pll.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-regmap-divider.h"
|
||||
#include "clk-regmap-mux.h"
|
||||
#include "common.h"
|
||||
#include "reset.h"
|
||||
#include "vdd-level.h"
|
||||
|
||||
static DEFINE_VDD_REGULATORS(vdd_mm, VDD_HIGH + 1, 1, vdd_corner);
|
||||
static DEFINE_VDD_REGULATORS(vdd_mxc, VDD_HIGH + 1, 1, vdd_corner);
|
||||
|
||||
static struct clk_vdd_class *video_cc_kalama_regulators[] = {
|
||||
&vdd_mm,
|
||||
&vdd_mxc,
|
||||
};
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
P_SLEEP_CLK,
|
||||
P_VIDEO_CC_PLL0_OUT_MAIN,
|
||||
P_VIDEO_CC_PLL1_OUT_MAIN,
|
||||
};
|
||||
|
||||
static struct pll_vco lucid_ole_vco[] = {
|
||||
{ 249600000, 2000000000, 0 },
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_cc_pll0_config = {
|
||||
.l = 0x1E,
|
||||
.cal_l = 0x44,
|
||||
.cal_l_ringosc = 0x44,
|
||||
.alpha = 0x0,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82AA299C,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_cc_pll0_config_kalama_v2 = {
|
||||
.l = 0x25,
|
||||
.cal_l = 0x44,
|
||||
.cal_l_ringosc = 0x44,
|
||||
.alpha = 0x8000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82AA299C,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_cc_pll0 = {
|
||||
.offset = 0x0,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_pll0",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_ole_ops,
|
||||
},
|
||||
.vdd_data = {
|
||||
.vdd_class = &vdd_mxc,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 615000000,
|
||||
[VDD_LOW] = 1100000000,
|
||||
[VDD_LOW_L1] = 1600000000,
|
||||
[VDD_NOMINAL] = 2000000000},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_cc_pll1_config = {
|
||||
.l = 0x2B,
|
||||
.cal_l = 0x44,
|
||||
.cal_l_ringosc = 0x44,
|
||||
.alpha = 0xC000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82AA299C,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static const struct alpha_pll_config video_cc_pll1_config_kalama_v2 = {
|
||||
.l = 0x36,
|
||||
.cal_l = 0x44,
|
||||
.cal_l_ringosc = 0x44,
|
||||
.alpha = 0xB000,
|
||||
.config_ctl_val = 0x20485699,
|
||||
.config_ctl_hi_val = 0x00182261,
|
||||
.config_ctl_hi1_val = 0x82AA299C,
|
||||
.test_ctl_val = 0x00000000,
|
||||
.test_ctl_hi_val = 0x00000003,
|
||||
.test_ctl_hi1_val = 0x00009000,
|
||||
.test_ctl_hi2_val = 0x00000034,
|
||||
.user_ctl_val = 0x00000000,
|
||||
.user_ctl_hi_val = 0x00000005,
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll video_cc_pll1 = {
|
||||
.offset = 0x1000,
|
||||
.vco_table = lucid_ole_vco,
|
||||
.num_vco = ARRAY_SIZE(lucid_ole_vco),
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
|
||||
.clkr = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_pll1",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "bi_tcxo",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_alpha_pll_lucid_ole_ops,
|
||||
},
|
||||
.vdd_data = {
|
||||
.vdd_class = &vdd_mxc,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 615000000,
|
||||
[VDD_LOW] = 1100000000,
|
||||
[VDD_LOW_L1] = 1600000000,
|
||||
[VDD_NOMINAL] = 2000000000},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_0_ao[] = {
|
||||
{ .fw_name = "bi_tcxo_ao" },
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &video_cc_pll0.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_2[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &video_cc_pll1.clkr.hw },
|
||||
};
|
||||
|
||||
static const struct parent_map video_cc_parent_map_3[] = {
|
||||
{ P_SLEEP_CLK, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_3[] = {
|
||||
{ .fw_name = "sleep_clk" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
|
||||
F(19200000, P_BI_TCXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_ahb_clk_src = {
|
||||
.cmd_rcgr = 0x8030,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_video_cc_ahb_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.flags = HW_CLK_CTRL_MODE,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_ahb_clk_src",
|
||||
.parent_data = video_cc_parent_data_0_ao,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
|
||||
F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1443000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_kalama_v2[] = {
|
||||
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_mvs0_clk_src = {
|
||||
.cmd_rcgr = 0x8000,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_1,
|
||||
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.flags = HW_CLK_CTRL_MODE,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_mvs0_clk_src",
|
||||
.parent_data = video_cc_parent_data_1,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_classes = video_cc_kalama_regulators,
|
||||
.num_vdd_classes = ARRAY_SIZE(video_cc_kalama_regulators),
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 576000000,
|
||||
[VDD_LOWER] = 720000000,
|
||||
[VDD_LOW] = 1014000000,
|
||||
[VDD_LOW_L1] = 1098000000,
|
||||
[VDD_NOMINAL] = 1332000000,
|
||||
[VDD_HIGH] = 1443000000},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
|
||||
F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_kalama_v2[] = {
|
||||
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_mvs1_clk_src = {
|
||||
.cmd_rcgr = 0x8018,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_2,
|
||||
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
|
||||
.enable_safe_config = true,
|
||||
.flags = HW_CLK_CTRL_MODE,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_mvs1_clk_src",
|
||||
.parent_data = video_cc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_classes = video_cc_kalama_regulators,
|
||||
.num_vdd_classes = ARRAY_SIZE(video_cc_kalama_regulators),
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 840000000,
|
||||
[VDD_LOWER] = 1050000000,
|
||||
[VDD_LOW] = 1350000000,
|
||||
[VDD_LOW_L1] = 1500000000,
|
||||
[VDD_NOMINAL] = 1650000000},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
|
||||
F(32000, P_SLEEP_CLK, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_sleep_clk_src = {
|
||||
.cmd_rcgr = 0x8128,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_3,
|
||||
.freq_tbl = ftbl_video_cc_sleep_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_sleep_clk_src",
|
||||
.parent_data = video_cc_parent_data_3,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_3),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
.clkr.vdd_data = {
|
||||
.vdd_class = &vdd_mm,
|
||||
.num_rate_max = VDD_NUM,
|
||||
.rate_max = (unsigned long[VDD_NUM]) {
|
||||
[VDD_LOWER_D1] = 32000},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg2 video_cc_xo_clk_src = {
|
||||
.cmd_rcgr = 0x810c,
|
||||
.mnd_width = 0,
|
||||
.hid_width = 5,
|
||||
.parent_map = video_cc_parent_map_0,
|
||||
.freq_tbl = ftbl_video_cc_ahb_clk_src,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_xo_clk_src",
|
||||
.parent_data = video_cc_parent_data_0_ao,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
|
||||
.reg = 0x80c4,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "video_cc_mvs0_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
|
||||
.reg = 0x8070,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "video_cc_mvs0c_div2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
|
||||
.reg = 0x80ec,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
|
||||
.reg = 0x809c,
|
||||
.shift = 0,
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "video_cc_mvs1c_div2_div_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_regmap_div_ro_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0_clk = {
|
||||
.halt_reg = 0x80b8,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.hwcg_reg = 0x80b8,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0x80b8,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_mvs0_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs0_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0c_clk = {
|
||||
.halt_reg = 0x8064,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8064,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_mvs0c_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1_clk = {
|
||||
.halt_reg = 0x80e0,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.hwcg_reg = 0x80e0,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0x80e0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_mvs1_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs1c_clk = {
|
||||
.halt_reg = 0x8090,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8090,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_mvs1c_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_sleep_clk = {
|
||||
.halt_reg = 0x8140,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8140,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_sleep_clk",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&video_cc_sleep_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_kalama_clocks[] = {
|
||||
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
|
||||
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
|
||||
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
|
||||
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
|
||||
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
|
||||
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
|
||||
[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
|
||||
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
|
||||
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map video_cc_kalama_resets[] = {
|
||||
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
|
||||
[CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
|
||||
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
|
||||
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
|
||||
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
|
||||
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
|
||||
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
|
||||
};
|
||||
|
||||
static const struct regmap_config video_cc_kalama_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x9f4c,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct qcom_cc_desc video_cc_kalama_desc = {
|
||||
.config = &video_cc_kalama_regmap_config,
|
||||
.clks = video_cc_kalama_clocks,
|
||||
.num_clks = ARRAY_SIZE(video_cc_kalama_clocks),
|
||||
.resets = video_cc_kalama_resets,
|
||||
.num_resets = ARRAY_SIZE(video_cc_kalama_resets),
|
||||
.clk_regulators = video_cc_kalama_regulators,
|
||||
.num_clk_regulators = ARRAY_SIZE(video_cc_kalama_regulators),
|
||||
};
|
||||
|
||||
static const struct of_device_id video_cc_kalama_match_table[] = {
|
||||
{ .compatible = "qcom,kalama-videocc" },
|
||||
{ .compatible = "qcom,kalama-videocc-v2" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, video_cc_kalama_match_table);
|
||||
|
||||
static void video_cc_kalama_fixup_kalamav2(struct regmap *regmap)
|
||||
{
|
||||
clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config_kalama_v2);
|
||||
clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config_kalama_v2);
|
||||
video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_kalama_v2;
|
||||
video_cc_mvs0_clk_src.clkr.vdd_data.rate_max[VDD_LOWER_D1] = 0;
|
||||
video_cc_mvs0_clk_src.clkr.vdd_data.rate_max[VDD_HIGH] = 1600000000;
|
||||
video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_kalama_v2;
|
||||
video_cc_mvs1_clk_src.clkr.vdd_data.rate_max[VDD_LOWER_D1] = 0;
|
||||
video_cc_sleep_clk_src.clkr.vdd_data.rate_max[VDD_LOWER_D1] = 0;
|
||||
video_cc_sleep_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] = 32000;
|
||||
}
|
||||
|
||||
static int video_cc_kalama_fixup(struct platform_device *pdev, struct regmap *regmap)
|
||||
{
|
||||
const char *compat = NULL;
|
||||
int compatlen = 0;
|
||||
|
||||
compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);
|
||||
if (!compat || compatlen <= 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (!strcmp(compat, "qcom,kalama-videocc-v2"))
|
||||
video_cc_kalama_fixup_kalamav2(regmap);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int video_cc_kalama_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &video_cc_kalama_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
ret = qcom_cc_runtime_init(pdev, &video_cc_kalama_desc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
|
||||
clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
|
||||
|
||||
ret = video_cc_kalama_fixup(pdev, regmap);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Keep clocks always enabled:
|
||||
* video_cc_ahb_clk
|
||||
* video_cc_xo_clk
|
||||
*/
|
||||
regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &video_cc_kalama_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void video_cc_kalama_sync_state(struct device *dev)
|
||||
{
|
||||
qcom_cc_sync_state(dev, &video_cc_kalama_desc);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops video_cc_kalama_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver video_cc_kalama_driver = {
|
||||
.probe = video_cc_kalama_probe,
|
||||
.driver = {
|
||||
.name = "video_cc-kalama",
|
||||
.of_match_table = video_cc_kalama_match_table,
|
||||
.sync_state = video_cc_kalama_sync_state,
|
||||
.pm = &video_cc_kalama_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init video_cc_kalama_init(void)
|
||||
{
|
||||
return platform_driver_register(&video_cc_kalama_driver);
|
||||
}
|
||||
subsys_initcall(video_cc_kalama_init);
|
||||
|
||||
static void __exit video_cc_kalama_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&video_cc_kalama_driver);
|
||||
}
|
||||
module_exit(video_cc_kalama_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI VIDEO_CC KALAMA Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user