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mmc: mmci: stm32: manage block gap hardware flow control
In stm32 sdmmc variant revision v3.0, a block gap hardware flow control should be used with bus speed modes SDR104 and HS200. It is enabled by writing a non-null value to the new added register MMCI_STM32_FIFOTHRR. The threshold will be 2^(N-1) bytes, so we can use the ffs() function to compute the value N to be written to the register. The threshold used should be the data block size, but must not be bigger than the FIFO size. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Link: https://lore.kernel.org/r/20230619115120.64474-5-yann.gautier@foss.st.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -218,6 +218,11 @@
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#define MCI_STM32_BUSYD0ENDMASK BIT(21)
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#define MMCIMASK1 0x040
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/* STM32 sdmmc data FIFO threshold register */
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#define MMCI_STM32_FIFOTHRR 0x044
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#define MMCI_STM32_THR_MASK GENMASK(3, 0)
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#define MMCIFIFOCNT 0x048
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#define MMCIFIFO 0x080 /* to 0x0bc */
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@ -361,6 +361,19 @@ static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
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datactrl = mmci_dctrl_blksz(host);
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if (host->hw_revision >= 3) {
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u32 thr = 0;
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if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
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host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
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thr = ffs(min_t(unsigned int, host->data->blksz,
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host->variant->fifosize));
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thr = min_t(u32, thr, MMCI_STM32_THR_MASK);
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}
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writel_relaxed(thr, host->base + MMCI_STM32_FIFOTHRR);
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}
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if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
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host->data->blocks == 1)
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datactrl |= MCI_DPSM_STM32_MODE_SDIO;
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