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Merge branch 'pci/dt-bindings'

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- Add qcom DT binding for 'global' interrupt (PCIe controller and
  link-specific events) for ipq8074, ipq8074-gen3, ipq6018, sa8775p,
  sc7280, sc8180x sdm845, sm8150, sm8250, sm8350 (Manivannan Sadhasivam)

- Add qcom DT binding for 8 MSI SPI interrupts for msm8998, ipq8074,
  ipq8074-gen3, ipq6018 (Manivannan Sadhasivam)

- Add dw rockchip DT binding for rk3576 and rk3562 (Kever Yang)

- Correct indentation and style of examples in brcm,stb-pcie,
  cdns,cdns-pcie-ep, intel,keembay-pcie-ep, intel,keembay-pcie,
  microchip,pcie-host, rcar-pci-ep, rcar-pci-host, xilinx-versal-cpm
  (Krzysztof Kozlowski)

- Fix include placement in sifive,fu740-pcie example (Krzysztof Kozlowski)

- Convert Marvell EBU (dove, kirkwood, armada-370, armada-xp) and armada8k
  from text to schema DT bindings (Rob Herring)

- Remove obsolete .txt DT bindings for content that has been moved to
  schemas (Rob Herring)

- Add qcom DT binding for MHI registers in IPQ5332, IPQ6018, IPQ8074 and
  IPQ9574 (Varadarajan Narayanan)

- Convert v3,v360epc-pci from text to DT schema binding (Rob Herring)

- Change microchip,pcie-host DT binding to be 'dma-noncoherent' since
  PolarFire may be configured that way (Conor Dooley)

* pci/dt-bindings:
  dt-bindings: PCI: microchip,pcie-host: Fix DMA coherency property
  dt-bindings: PCI: Convert v3,v360epc-pci to DT schema
  dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
  dt-bindings: PCI: Remove obsolete .txt docs
  dt-bindings: PCI: Convert marvell,armada8k-pcie to schema
  dt-bindings: PCI: Convert Marvell EBU to schema
  dt-bindings: PCI: sifive,fu740-pcie: Fix include placement in DTS example
  dt-bindings: PCI: Correct indentation and style in DTS example
  dt-bindings: PCI: dwc: rockchip: Add rk3562 support
  dt-bindings: PCI: dw: rockchip: Add rk3576 support
  dt-bindings: PCI: qcom,pcie-sc8180x: Add 'global' interrupt
  dt-bindings: PCI: qcom: Allow IPQ6018 to use 8 MSI and one 'global' interrupt
  dt-bindings: PCI: qcom: Allow IPQ8074 to use 8 MSI and one 'global' interrupt
  dt-bindings: PCI: qcom: Allow MSM8998 to use 8 MSI and one 'global' interrupt
  dt-bindings: PCI: qcom: Add 'global' interrupt for SDM845 SoC
  dt-bindings: PCI: qcom,pcie-sc7280: Add 'global' interrupt
  dt-bindings: PCI: qcom,pcie-sa8775p: Add 'global' interrupt
  dt-bindings: PCI: qcom,pcie-sm8350: Add 'global' interrupt
  dt-bindings: PCI: qcom,pcie-sm8250: Add 'global' interrupt
  dt-bindings: PCI: qcom,pcie-sm8150: Add 'global' interrupt
This commit is contained in:
Bjorn Helgaas 2025-06-04 10:50:45 -05:00
commit 27b1aac553
31 changed files with 799 additions and 1152 deletions
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81
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
View File

@ -186,49 +186,48 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
scb {
#address-cells = <2>;
#size-cells = <1>;
pcie0: pcie@7d500000 {
compatible = "brcm,bcm2711-pcie";
reg = <0x0 0x7d500000 0x9310>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <1>;
pcie0: pcie@7d500000 {
compatible = "brcm,bcm2711-pcie";
reg = <0x0 0x7d500000 0x9310>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie0>;
msi-controller;
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
brcm,enable-ssc;
brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
msi-parent = <&pcie0>;
msi-controller;
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
brcm,enable-ssc;
brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
/* PCIe bridge, Root Port */
pci@0,0 {
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x0 0x0 0x0 0x0>;
compatible = "pciclass,0604";
device_type = "pci";
vpcie3v3-supply = <&vreg7>;
ranges;
/* PCIe bridge, Root Port */
pci@0,0 {
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x0 0x0 0x0 0x0>;
compatible = "pciclass,0604";
device_type = "pci";
vpcie3v3-supply = <&vreg7>;
ranges;
/* PCIe endpoint */
pci-ep@0,0 {
assigned-addresses =
<0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
reg = <0x0 0x0 0x0 0x0 0x0>;
compatible = "pci14e4,1688";
};
};
/* PCIe endpoint */
pci-ep@0,0 {
assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
reg = <0x0 0x0 0x0 0x0 0x0>;
compatible = "pci14e4,1688";
};
};
};
};

16
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
View File

@ -37,14 +37,14 @@ examples:
#size-cells = <2>;
pcie-ep@fc000000 {
compatible = "cdns,cdns-pcie-ep";
reg = <0x0 0xfc000000 0x0 0x01000000>,
<0x0 0x80000000 0x0 0x40000000>;
reg-names = "reg", "mem";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <8>;
phys = <&pcie_phy0>;
phy-names = "pcie-phy";
compatible = "cdns,cdns-pcie-ep";
reg = <0x0 0xfc000000 0x0 0x01000000>,
<0x0 0x80000000 0x0 0x40000000>;
reg-names = "reg", "mem";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <8>;
phys = <&pcie_phy0>;
phy-names = "pcie-phy";
};
};
...

26
Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml
View File

@ -53,17 +53,17 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
pcie-ep@37000000 {
compatible = "intel,keembay-pcie-ep";
reg = <0x37000000 0x00001000>,
<0x37100000 0x00001000>,
<0x37300000 0x00001000>,
<0x36000000 0x01000000>,
<0x37800000 0x00000200>;
reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
num-lanes = <2>;
compatible = "intel,keembay-pcie-ep";
reg = <0x37000000 0x00001000>,
<0x37100000 0x00001000>,
<0x37300000 0x00001000>,
<0x36000000 0x01000000>,
<0x37800000 0x00000200>;
reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
num-lanes = <2>;
};

38
Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
View File

@ -75,23 +75,23 @@ examples:
#define KEEM_BAY_A53_PCIE
#define KEEM_BAY_A53_AUX_PCIE
pcie@37000000 {
compatible = "intel,keembay-pcie";
reg = <0x37000000 0x00001000>,
<0x37300000 0x00001000>,
<0x36e00000 0x00200000>,
<0x37800000 0x00000200>;
reg-names = "dbi", "atu", "config", "apb";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "pcie_ev", "pcie_err";
clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
clock-names = "master", "aux";
reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
num-lanes = <2>;
compatible = "intel,keembay-pcie";
reg = <0x37000000 0x00001000>,
<0x37300000 0x00001000>,
<0x36e00000 0x00200000>,
<0x37800000 0x00000200>;
reg-names = "dbi", "atu", "config", "apb";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "pcie_ev", "pcie_err";
clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
clock-names = "master", "aux";
reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
num-lanes = <2>;
};

100
Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml Normal file
View File

@ -0,0 +1,100 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 7K/8K PCIe interface
maintainers:
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
description:
This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
select:
properties:
compatible:
contains:
enum:
- marvell,armada8k-pcie
required:
- compatible
allOf:
- $ref: snps,dw-pcie.yaml#
properties:
compatible:
items:
- enum:
- marvell,armada8k-pcie
- const: snps,dw-pcie
reg:
maxItems: 2
reg-names:
items:
- const: ctrl
- const: config
clocks:
minItems: 1
maxItems: 2
clock-names:
items:
- const: core
- const: reg
interrupts:
maxItems: 1
msi-parent:
maxItems: 1
phys:
minItems: 1
maxItems: 4
phy-names:
minItems: 1
maxItems: 4
marvell,reset-gpio:
maxItems: 1
deprecated: true
required:
- interrupt-map
- clocks
- msi-parent
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
pcie@f2600000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0xf2600000 0x10000>, <0xf6f00000 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
ranges = <0x81000000 0 0xf9000000 0xf9000000 0 0x10000>, /* downstream I/O */
<0x82000000 0 0xf6000000 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 13>;
};
...

277
Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml Normal file
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@ -0,0 +1,277 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell EBU PCIe interfaces
maintainers:
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
- Pali Rohár <pali@kernel.org>
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:
enum:
- marvell,armada-370-pcie
- marvell,armada-xp-pcie
- marvell,dove-pcie
- marvell,kirkwood-pcie
ranges:
description: >
The ranges describing the MMIO registers have the following layout:
0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
where:
* r is a 32-bits value that gives the offset of the MMIO registers of
this PCIe interface, from the base of the internal registers.
* s is a 32-bits value that give the size of this MMIO registers area.
This range entry translates the '0x82000000 0 r' PCI address into the
'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal
register window (as identified by MBUS_ID(0xf0, 0x01)).
The ranges describing the MBus windows have the following layout:
0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
where:
* t is the type of the MBus window (as defined by the standard PCI DT
bindings), 1 for I/O and 2 for memory.
* s is the PCI slot that corresponds to this PCIe interface
* w is the 'target ID' value for the MBus window
* a the 'attribute' value for the MBus window.
Since the location and size of the different MBus windows is not fixed in
hardware, and only determined in runtime, those ranges cover the full first
4 GB of the physical address space, and do not translate into a valid CPU
address.
msi-parent:
maxItems: 1
patternProperties:
'^pcie@':
type: object
allOf:
- $ref: /schemas/pci/pci-bus-common.yaml#
- $ref: /schemas/pci/pci-device.yaml#
unevaluatedProperties: false
properties:
clocks:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
minItems: 1
items:
- const: intx
- const: error
reset-delay-us:
default: 100000
description: todo
marvell,pcie-port:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
description: todo
marvell,pcie-lane:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
description: todo
interrupt-controller:
type: object
additionalProperties: false
properties:
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- assigned-addresses
- clocks
- interrupt-map
- marvell,pcie-port
unevaluatedProperties: false
examples:
- |
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie@f001000000000000 {
compatible = "marvell,armada-xp-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
msi-parent = <&mpic>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
num-lanes = <1>;
/* low-active PERST# reset on GPIO 25 */
reset-gpios = <&gpio0 25 1>;
/* wait 20ms for device settle after reset deassertion */
reset-delay-us = <20000>;
clocks = <&gateclk 5>;
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
num-lanes = <1>;
clocks = <&gateclk 6>;
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
num-lanes = <1>;
clocks = <&gateclk 7>;
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
num-lanes = <1>;
clocks = <&gateclk 8>;
};
pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
num-lanes = <1>;
clocks = <&gateclk 9>;
};
pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
num-lanes = <1>;
clocks = <&gateclk 10>;
};
};
};
...

56
Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
View File

@ -50,7 +50,7 @@ properties:
items:
pattern: '^fic[0-3]$'
dma-coherent: true
dma-noncoherent: true
ranges:
minItems: 1
@ -65,33 +65,33 @@ unevaluatedProperties: false
examples:
- |
soc {
#address-cells = <2>;
#address-cells = <2>;
#size-cells = <2>;
pcie0: pcie@2030000000 {
compatible = "microchip,pcie-host-1.0";
reg = <0x0 0x70000000 0x0 0x08000000>,
<0x0 0x43008000 0x0 0x00002000>,
<0x0 0x4300a000 0x0 0x00002000>;
reg-names = "cfg", "bridge", "ctrl";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
pcie0: pcie@2030000000 {
compatible = "microchip,pcie-host-1.0";
reg = <0x0 0x70000000 0x0 0x08000000>,
<0x0 0x43008000 0x0 0x00002000>,
<0x0 0x4300a000 0x0 0x00002000>;
reg-names = "cfg", "bridge", "ctrl";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupts = <119>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
interrupt-parent = <&plic0>;
msi-parent = <&pcie0>;
msi-controller;
bus-range = <0x00 0x7f>;
ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
#interrupt-cells = <1>;
interrupts = <119>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
interrupt-parent = <&plic0>;
msi-parent = <&pcie0>;
msi-controller;
bus-range = <0x00 0x7f>;
ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};

310
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@ -1,310 +0,0 @@
* Marvell EBU PCIe interfaces
Mandatory properties:
- compatible: one of the following values:
marvell,armada-370-pcie
marvell,armada-xp-pcie
marvell,dove-pcie
marvell,kirkwood-pcie
- #address-cells, set to <3>
- #size-cells, set to <2>
- #interrupt-cells, set to <1>
- bus-range: PCI bus numbers covered
- device_type, set to "pci"
- ranges: ranges describing the MMIO registers to control the PCIe
interfaces, and ranges describing the MBus windows needed to access
the memory and I/O regions of each PCIe interface.
- msi-parent: Link to the hardware entity that serves as the Message
Signaled Interrupt controller for this PCI controller.
The ranges describing the MMIO registers have the following layout:
0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
where:
* r is a 32-bits value that gives the offset of the MMIO
registers of this PCIe interface, from the base of the internal
registers.
* s is a 32-bits value that give the size of this MMIO
registers area. This range entry translates the '0x82000000 0 r' PCI
address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
of the internal register window (as identified by MBUS_ID(0xf0,
0x01)).
The ranges describing the MBus windows have the following layout:
0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
where:
* t is the type of the MBus window (as defined by the standard PCI DT
bindings), 1 for I/O and 2 for memory.
* s is the PCI slot that corresponds to this PCIe interface
* w is the 'target ID' value for the MBus window
* a the 'attribute' value for the MBus window.
Since the location and size of the different MBus windows is not fixed in
hardware, and only determined in runtime, those ranges cover the full first
4 GB of the physical address space, and do not translate into a valid CPU
address.
In addition, the device tree node must have sub-nodes describing each
PCIe interface, having the following mandatory properties:
- reg: used only for interrupt mapping, so only the first four bytes
are used to refer to the correct bus number and device number.
- assigned-addresses: reference to the MMIO registers used to control
this PCIe interface.
- clocks: the clock associated to this PCIe interface
- marvell,pcie-port: the physical PCIe port number
- status: either "disabled" or "okay"
- device_type, set to "pci"
- #address-cells, set to <3>
- #size-cells, set to <2>
- #interrupt-cells, set to <1>
- ranges, translating the MBus windows ranges of the parent node into
standard PCI addresses.
- interrupt-map-mask and interrupt-map, standard PCI properties to
define the mapping of the PCIe interface to interrupt numbers.
and the following optional properties:
- marvell,pcie-lane: the physical PCIe lane number, for ports having
multiple lanes. If this property is not found, we assume that the
value is 0.
- num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
- reset-gpios: optional GPIO to PERST#
- reset-delay-us: delay in us to wait after reset de-assertion, if not
specified will default to 100ms, as required by the PCIe specification.
- interrupt-names: list of interrupt names, supported are:
- "intx" - interrupt line triggered by one of the legacy interrupt
- interrupts or interrupts-extended: List of the interrupt sources which
corresponding to the "interrupt-names". If non-empty then also additional
'interrupt-controller' subnode must be defined.
Example:
pcie-controller {
compatible = "marvell,armada-xp-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
msi-parent = <&mpic>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
num-lanes = <1>;
/* low-active PERST# reset on GPIO 25 */
reset-gpios = <&gpio0 25 1>;
/* wait 20ms for device settle after reset deassertion */
reset-delay-us = <20000>;
clocks = <&gateclk 5>;
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
num-lanes = <1>;
clocks = <&gateclk 6>;
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
num-lanes = <1>;
clocks = <&gateclk 7>;
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
num-lanes = <1>;
clocks = <&gateclk 8>;
};
pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
num-lanes = <1>;
clocks = <&gateclk 9>;
};
pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
num-lanes = <1>;
clocks = <&gateclk 10>;
};
pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
num-lanes = <1>;
clocks = <&gateclk 11>;
};
pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
num-lanes = <1>;
clocks = <&gateclk 12>;
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
num-lanes = <1>;
clocks = <&gateclk 26>;
};
pcie@a,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
num-lanes = <1>;
clocks = <&gateclk 27>;
};
};

2
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
View File

@ -74,7 +74,7 @@ properties:
reset-gpios:
description: Must contain a phandle to a GPIO controller followed by GPIO
that is being used as PERST input signal. Please refer to pci.txt.
that is being used as PERST input signal.
phys:
minItems: 1

48
Documentation/devicetree/bindings/pci/pci-armada8k.txt
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@ -1,48 +0,0 @@
* Marvell Armada 7K/8K PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties:
- compatible: "marvell,armada8k-pcie"
- reg: must contain two register regions
- the control register region
- the config space region
- reg-names:
- "ctrl" for the control register region
- "config" for the config space region
- interrupts: Interrupt specifier for the PCIe controller
- clocks: reference to the PCIe controller clocks
- clock-names: mandatory if there is a second clock, in this case the
name must be "core" for the first clock and "reg" for the second
one
Optional properties:
- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
Either 1, 2 or 4 PHYs might be needed depending on the number of
PCIe lanes.
- phy-names: names of the PHYs corresponding to the number of lanes.
Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
2 PHYs.
Example:
pcie@f2600000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
bus-range = <0 0xff>;
ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 13>;
};

171
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@ -1,171 +0,0 @@
This document describes the generic device tree binding for describing the
relationship between PCI(e) devices and IOMMU(s).
Each PCI(e) device under a root complex is uniquely identified by its Requester
ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
Function number.
For the purpose of this document, when treated as a numeric value, a RID is
formatted such that:
* Bits [15:8] are the Bus number.
* Bits [7:3] are the Device number.
* Bits [2:0] are the Function number.
* Any other bits required for padding must be zero.
IOMMUs may distinguish PCI devices through sideband data derived from the
Requester ID. While a given PCI device can only master through one IOMMU, a
root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
bus).
The generic 'iommus' property is insufficient to describe this relationship,
and a mechanism is required to map from a PCI device to its IOMMU and sideband
data.
For generic IOMMU bindings, see
Documentation/devicetree/bindings/iommu/iommu.txt.
PCI root complex
================
Optional properties
-------------------
- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
data.
The property is an arbitrary number of tuples of
(rid-base,iommu,iommu-base,length).
Any RID r in the interval [rid-base, rid-base + length) is associated with
the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
- iommu-map-mask: A mask to be applied to each Requester ID prior to being
mapped to an IOMMU specifier per the iommu-map property.
Example (1)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
iommu: iommu@a {
reg = <0xa 0x1>;
compatible = "vendor,some-iommu";
#iommu-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* The sideband data provided to the IOMMU is the RID,
* identity-mapped.
*/
iommu-map = <0x0 &iommu 0x0 0x10000>;
};
};
Example (2)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
iommu: iommu@a {
reg = <0xa 0x1>;
compatible = "vendor,some-iommu";
#iommu-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* The sideband data provided to the IOMMU is the RID with the
* function bits masked out.
*/
iommu-map = <0x0 &iommu 0x0 0x10000>;
iommu-map-mask = <0xfff8>;
};
};
Example (3)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
iommu: iommu@a {
reg = <0xa 0x1>;
compatible = "vendor,some-iommu";
#iommu-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* The sideband data provided to the IOMMU is the RID,
* but the high bits of the bus number are flipped.
*/
iommu-map = <0x0000 &iommu 0x8000 0x8000>,
<0x8000 &iommu 0x0000 0x8000>;
};
};
Example (4)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
iommu_a: iommu@a {
reg = <0xa 0x1>;
compatible = "vendor,some-iommu";
#iommu-cells = <1>;
};
iommu_b: iommu@b {
reg = <0xb 0x1>;
compatible = "vendor,some-iommu";
#iommu-cells = <1>;
};
iommu_c: iommu@c {
reg = <0xc 0x1>;
compatible = "vendor,some-iommu";
#iommu-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* Devices with bus number 0-127 are mastered via IOMMU
* a, with sideband data being RID[14:0].
* Devices with bus number 128-255 are mastered via
* IOMMU b, with sideband data being RID[14:0].
* No devices master via IOMMU c.
*/
iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
<0x8000 &iommu_b 0x0000 0x8000>;
};
};

220
Documentation/devicetree/bindings/pci/pci-msi.txt
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@ -1,220 +0,0 @@
This document describes the generic device tree binding for describing the
relationship between PCI devices and MSI controllers.
Each PCI device under a root complex is uniquely identified by its Requester ID
(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
Function number.
For the purpose of this document, when treated as a numeric value, a RID is
formatted such that:
* Bits [15:8] are the Bus number.
* Bits [7:3] are the Device number.
* Bits [2:0] are the Function number.
* Any other bits required for padding must be zero.
MSIs may be distinguished in part through the use of sideband data accompanying
writes. In the case of PCI devices, this sideband data may be derived from the
Requester ID. A mechanism is required to associate a device with both the MSI
controllers it can address, and the sideband data that will be associated with
its writes to those controllers.
For generic MSI bindings, see
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
PCI root complex
================
Optional properties
-------------------
- msi-map: Maps a Requester ID to an MSI controller and associated
msi-specifier data. The property is an arbitrary number of tuples of
(rid-base,msi-controller,msi-base,length), where:
* rid-base is a single cell describing the first RID matched by the entry.
* msi-controller is a single phandle to an MSI controller
* msi-base is an msi-specifier describing the msi-specifier produced for the
first RID matched by the entry.
* length is a single cell describing how many consecutive RIDs are matched
following the rid-base.
Any RID r in the interval [rid-base, rid-base + length) is associated with
the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped
to an msi-specifier per the msi-map property.
- msi-parent: Describes the MSI parent of the root complex itself. Where
the root complex and MSI controller do not pass sideband data with MSI
writes, this property may be used to describe the MSI controller(s)
used by PCI devices under the root complex, if defined as such in the
binding for the root complex.
Example (1)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
msi: msi-controller@a {
reg = <0xa 0x1>;
compatible = "vendor,some-controller";
msi-controller;
#msi-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* The sideband data provided to the MSI controller is
* the RID, identity-mapped.
*/
msi-map = <0x0 &msi_a 0x0 0x10000>,
};
};
Example (2)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
msi: msi-controller@a {
reg = <0xa 0x1>;
compatible = "vendor,some-controller";
msi-controller;
#msi-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* The sideband data provided to the MSI controller is
* the RID, masked to only the device and function bits.
*/
msi-map = <0x0 &msi_a 0x0 0x100>,
msi-map-mask = <0xff>
};
};
Example (3)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
msi: msi-controller@a {
reg = <0xa 0x1>;
compatible = "vendor,some-controller";
msi-controller;
#msi-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* The sideband data provided to the MSI controller is
* the RID, but the high bit of the bus number is
* ignored.
*/
msi-map = <0x0000 &msi 0x0000 0x8000>,
<0x8000 &msi 0x0000 0x8000>;
};
};
Example (4)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
msi: msi-controller@a {
reg = <0xa 0x1>;
compatible = "vendor,some-controller";
msi-controller;
#msi-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* The sideband data provided to the MSI controller is
* the RID, but the high bit of the bus number is
* negated.
*/
msi-map = <0x0000 &msi 0x8000 0x8000>,
<0x8000 &msi 0x0000 0x8000>;
};
};
Example (5)
===========
/ {
#address-cells = <1>;
#size-cells = <1>;
msi_a: msi-controller@a {
reg = <0xa 0x1>;
compatible = "vendor,some-controller";
msi-controller;
#msi-cells = <1>;
};
msi_b: msi-controller@b {
reg = <0xb 0x1>;
compatible = "vendor,some-controller";
msi-controller;
#msi-cells = <1>;
};
msi_c: msi-controller@c {
reg = <0xc 0x1>;
compatible = "vendor,some-controller";
msi-controller;
#msi-cells = <1>;
};
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";
/*
* The sideband data provided to MSI controller a is the
* RID, but the high bit of the bus number is negated.
* The sideband data provided to MSI controller b is the
* RID, identity-mapped.
* MSI controller c is not addressable.
*/
msi-map = <0x0000 &msi_a 0x8000 0x08000>,
<0x8000 &msi_a 0x0000 0x08000>,
<0x0000 &msi_b 0x0000 0x10000>;
};
};

84
Documentation/devicetree/bindings/pci/pci.txt
View File

@ -1,84 +0,0 @@
PCI bus bridges have standardized Device Tree bindings:
PCI Bus Binding to: IEEE Std 1275-1994
https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
And for the interrupt mapping part:
Open Firmware Recommended Practice: Interrupt Mapping
https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
Additionally to the properties specified in the above standards a host bridge
driver implementation may support the following properties:
- linux,pci-domain:
If present this property assigns a fixed PCI domain number to a host bridge,
otherwise an unstable (across boots) unique number will be assigned.
It is required to either not set this property at all or set it for all
host bridges in the system, otherwise potentially conflicting domain numbers
may be assigned to root buses behind different host bridges. The domain
number for each host bridge in the system must be unique.
- max-link-speed:
If present this property specifies PCI gen for link capability. Host
drivers could add this as a strategy to avoid unnecessary operation for
unsupported link speed, for instance, trying to do training for
unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
for gen2, and '1' for gen1. Any other values are invalid.
- reset-gpios:
If present this property specifies PERST# GPIO. Host drivers can parse the
GPIO and apply fundamental reset to endpoints.
- supports-clkreq:
If present this property specifies that CLKREQ signal routing exists from
root port to downstream device and host bridge drivers can do programming
which depends on CLKREQ signal existence. For example, programming root port
not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
PCI-PCI Bridge properties
-------------------------
PCIe root ports and switch ports may be described explicitly in the device
tree, as children of the host bridge node. Even though those devices are
discoverable by probing, it might be necessary to describe properties that
aren't provided by standard PCIe capabilities.
Required properties:
- reg:
Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
document, it is a five-cell address encoded as (phys.hi phys.mid
phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
The bus number is defined by firmware, through the standard bridge
configuration mechanism. If this port is a switch port, then firmware
allocates the bus number and writes it into the Secondary Bus Number
register of the bridge directly above this port. Otherwise, the bus
number of a root port is the first number in the bus-range property,
defaulting to zero.
If firmware leaves the ARI Forwarding Enable bit set in the bridge
above this port, then phys.hi contains the 8-bit function number as
0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
recommends that firmware only leaves ARI enabled when it knows that the
OS is ARI-aware.
Optional properties:
- external-facing:
When present, the port is external-facing. All bridges and endpoints
downstream of this port are external to the machine. The OS can, for
example, use this information to identify devices that cannot be
trusted with relaxed DMA protection, as users could easily attach
malicious devices to this port.
Example:
pcie@10000000 {
compatible = "pci-host-ecam-generic";
...
pcie@0008 {
/* Root port 00:01.0 is external-facing */
reg = <0x00000800 0 0 0 0>;
external-facing;
};
};

10
Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
View File

@ -45,9 +45,10 @@ properties:
interrupts:
minItems: 8
maxItems: 8
maxItems: 9
interrupt-names:
minItems: 8
items:
- const: msi0
- const: msi1
@ -57,6 +58,7 @@ properties:
- const: msi5
- const: msi6
- const: msi7
- const: global
resets:
maxItems: 1
@ -129,7 +131,8 @@ examples:
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -137,7 +140,8 @@ examples:
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,

9
Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml
View File

@ -54,9 +54,10 @@ properties:
interrupts:
minItems: 8
maxItems: 8
maxItems: 9
interrupt-names:
minItems: 8
items:
- const: msi0
- const: msi1
@ -66,6 +67,7 @@ properties:
- const: msi5
- const: msi6
- const: msi7
- const: global
resets:
maxItems: 1
@ -149,9 +151,10 @@ examples:
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
"msi4", "msi5", "msi6", "msi7", "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,

10
Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml
View File

@ -49,9 +49,10 @@ properties:
interrupts:
minItems: 8
maxItems: 8
maxItems: 9
interrupt-names:
minItems: 8
items:
- const: msi0
- const: msi1
@ -61,6 +62,7 @@ properties:
- const: msi5
- const: msi6
- const: msi7
- const: global
resets:
maxItems: 1
@ -136,7 +138,8 @@ examples:
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -144,7 +147,8 @@ examples:
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

9
Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
View File

@ -49,9 +49,10 @@ properties:
interrupts:
minItems: 8
maxItems: 8
maxItems: 9
interrupt-names:
minItems: 8
items:
- const: msi0
- const: msi1
@ -61,6 +62,7 @@ properties:
- const: msi5
- const: msi6
- const: msi7
- const: global
resets:
maxItems: 1
@ -128,9 +130,10 @@ examples:
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
"msi4", "msi5", "msi6", "msi7", "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

9
Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml
View File

@ -61,9 +61,10 @@ properties:
interrupts:
minItems: 8
maxItems: 8
maxItems: 9
interrupt-names:
minItems: 8
items:
- const: msi0
- const: msi1
@ -73,6 +74,7 @@ properties:
- const: msi5
- const: msi6
- const: msi7
- const: global
resets:
maxItems: 1
@ -143,9 +145,10 @@ examples:
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
"msi4", "msi5", "msi6", "msi7", "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

9
Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml
View File

@ -51,9 +51,10 @@ properties:
interrupts:
minItems: 8
maxItems: 8
maxItems: 9
interrupt-names:
minItems: 8
items:
- const: msi0
- const: msi1
@ -63,6 +64,7 @@ properties:
- const: msi5
- const: msi6
- const: msi7
- const: global
resets:
maxItems: 1
@ -132,9 +134,10 @@ examples:
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
"msi4", "msi5", "msi6", "msi7", "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

15
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
View File

@ -177,14 +177,16 @@ allOf:
properties:
reg:
minItems: 5
maxItems: 5
maxItems: 6
reg-names:
minItems: 5
items:
- const: dbi # DesignWare PCIe registers
- const: elbi # External local bus interface registers
- const: atu # ATU address space
- const: parf # Qualcomm specific registers
- const: config # PCIe configuration space
- const: mhi # MHI registers
- if:
properties:
@ -639,7 +641,11 @@ allOf:
compatible:
contains:
enum:
- qcom,pcie-ipq6018
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
- qcom,pcie-msm8996
- qcom,pcie-msm8998
- qcom,pcie-sdm845
then:
oneOf:
@ -652,8 +658,9 @@ allOf:
- properties:
interrupts:
minItems: 8
maxItems: 8
maxItems: 9
interrupt-names:
minItems: 8
items:
- const: msi0
- const: msi1
@ -663,6 +670,7 @@ allOf:
- const: msi5
- const: msi6
- const: msi7
- const: global
- if:
properties:
@ -672,11 +680,8 @@ allOf:
- qcom,pcie-apq8064
- qcom,pcie-apq8084
- qcom,pcie-ipq4019
- qcom,pcie-ipq6018
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064-v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
- qcom,pcie-qcs404
then:
properties:

34
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
View File

@ -73,21 +73,21 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a774c0-sysc.h>
pcie0_ep: pcie-ep@fe000000 {
compatible = "renesas,r8a774c0-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0xfe000000 0x80000>,
<0xfe100000 0x100000>,
<0xfe200000 0x200000>,
<0x30000000 0x8000000>,
<0x38000000 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cpg 319>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
clocks = <&cpg CPG_MOD 319>;
clock-names = "pcie";
max-functions = /bits/ 8 <1>;
pcie0_ep: pcie-ep@fe000000 {
compatible = "renesas,r8a774c0-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0xfe000000 0x80000>,
<0xfe100000 0x100000>,
<0xfe200000 0x200000>,
<0x30000000 0x8000000>,
<0x38000000 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cpg 319>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
clocks = <&cpg CPG_MOD 319>;
clock-names = "pcie";
max-functions = /bits/ 8 <1>;
};

46
Documentation/devicetree/bindings/pci/rcar-pci-host.yaml
View File

@ -113,27 +113,27 @@ examples:
pcie: pcie@fe000000 {
compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 319>;
vpcie3v3-supply = <&pcie_3v3>;
vpcie12v-supply = <&pcie_12v>;
};
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 319>;
vpcie3v3-supply = <&pcie_3v3>;
vpcie12v-supply = <&pcie_12v>;
};
};

10
Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
View File

@ -65,7 +65,11 @@ properties:
tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
nf_err_rx, f_err_rx, radm_qoverflow
- description:
eDMA write channel 0 interrupt
If the matching interrupt name is "msi", then this is the combined
MSI line interrupt, which is to support MSI interrupts output to GIC
controller via GIC SPI interrupt instead of GIC ITS interrupt.
If the matching interrupt name is "dma0", then this is the eDMA write
channel 0 interrupt.
- description:
eDMA write channel 1 interrupt
- description:
@ -81,7 +85,9 @@ properties:
- const: msg
- const: legacy
- const: err
- const: dma0
- enum:
- msi
- dma0
- const: dma1
- const: dma2
- const: dma3

60
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
View File

@ -16,16 +16,14 @@ description: |+
PCIe IP and thus inherits all the common properties defined in
snps,dw-pcie.yaml.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
properties:
compatible:
oneOf:
- const: rockchip,rk3568-pcie
- items:
- enum:
- rockchip,rk3562-pcie
- rockchip,rk3576-pcie
- rockchip,rk3588-pcie
- const: rockchip,rk3568-pcie
@ -71,8 +69,58 @@ properties:
vpcie3v3-supply: true
required:
- msi-map
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
- if:
not:
properties:
compatible:
contains:
enum:
- rockchip,rk3562-pcie
- rockchip,rk3576-pcie
then:
required:
- msi-map
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3562-pcie
- rockchip,rk3576-pcie
then:
properties:
interrupts:
minItems: 6
maxItems: 6
interrupt-names:
items:
- const: sys
- const: pmc
- const: msg
- const: legacy
- const: err
- const: msi
else:
properties:
interrupts:
minItems: 5
interrupt-names:
minItems: 5
items:
- const: sys
- const: pmc
- const: msg
- const: legacy
- const: err
- const: dma0
- const: dma1
- const: dma2
- const: dma3
unevaluatedProperties: false

2
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
View File

@ -81,10 +81,10 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/sifive-fu740-prci.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
#include <dt-bindings/clock/sifive-fu740-prci.h>
pcie@e00000000 {
compatible = "sifive,fu740-pcie";

3
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
View File

@ -115,7 +115,7 @@ properties:
above for new bindings.
oneOf:
- description: See native 'dbi' clock for details
enum: [ pcie, pcie_apb_sys, aclk_dbi ]
enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ]
- description: See native 'mstr/slv' clock for details
enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]
- description: See native 'pipe' clock for details
@ -201,6 +201,7 @@ properties:
oneOf:
- pattern: '^pcie(-?phy[0-9]*)?$'
- pattern: '^p2u-[0-7]$'
- pattern: '^cp[01]-pcie[0-2]-x[124](-lane[0-3])?-phy$' # marvell,armada8k-pcie
reset-gpio:
deprecated: true

4
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
View File

@ -105,6 +105,8 @@ properties:
Vendor-specific CSR names. Consider using the generic names above
for new bindings.
oneOf:
- description: See native 'dbi' CSR region for details.
enum: [ ctrl ]
- description: See native 'elbi/app' CSR region for details.
enum: [ apb, mgmt, link, ulreg, appl ]
- description: See native 'atu' CSR region for details.
@ -117,7 +119,7 @@ properties:
const: slcr
allOf:
- contains:
const: dbi
enum: [ dbi, ctrl ]
- contains:
const: config

100
Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml Normal file
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@ -0,0 +1,100 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/v3,v360epc-pci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: V3 Semiconductor V360 EPC PCI bridge
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description:
This bridge is found in the ARM Integrator/AP (Application Platform)
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:
items:
- const: arm,integrator-ap-pci
- const: v3,v360epc-pci
reg:
items:
- description: V3 host bridge controller
- description: Configuration space
clocks:
maxItems: 1
dma-ranges:
maxItems: 2
description:
The inbound ranges must be aligned to a 1MB boundary, and may be 1MB, 2MB,
4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The
memory should be marked as pre-fetchable.
interrupts:
description: Bus Error IRQ
maxItems: 1
ranges:
description:
The non-prefetchable and prefetchable memory windows must each be exactly
256MB (0x10000000) in size. The prefetchable memory window must be
immediately adjacent to the non-prefetchable memory window.
required:
- compatible
- reg
- clocks
- dma-ranges
- "#interrupt-cells"
- interrupt-map
- interrupt-map-mask
unevaluatedProperties: false
examples:
- |
pci@62000000 {
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
device_type = "pci";
interrupt-parent = <&pic>;
interrupts = <17>; /* Bus error IRQ */
clocks = <&pciclk>;
ranges = <0x01000000 0 0x00000000 0x60000000 0 0x01000000>, /* 16 MiB @ LB 60000000 */
<0x02000000 0 0x40000000 0x40000000 0 0x10000000>, /* 256 MiB @ LB 40000000 1:1 */
<0x42000000 0 0x50000000 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
dma-ranges = <0x02000000 0 0x20000000 0x20000000 0 0x20000000>, /* EBI: 512 MB @ LB 20000000 1:1 */
<0x02000000 0 0x80000000 0x80000000 0 0x40000000>; /* CM alias: 1GB @ LB 80000000 */
interrupt-map-mask = <0xf800 0 0 0x7>;
interrupt-map =
/* IDSEL 9 */
<0x4800 0 0 1 &pic 13>, /* INT A on slot 9 is irq 13 */
<0x4800 0 0 2 &pic 14>, /* INT B on slot 9 is irq 14 */
<0x4800 0 0 3 &pic 15>, /* INT C on slot 9 is irq 15 */
<0x4800 0 0 4 &pic 16>, /* INT D on slot 9 is irq 16 */
/* IDSEL 10 */
<0x5000 0 0 1 &pic 14>, /* INT A on slot 10 is irq 14 */
<0x5000 0 0 2 &pic 15>, /* INT B on slot 10 is irq 15 */
<0x5000 0 0 3 &pic 16>, /* INT C on slot 10 is irq 16 */
<0x5000 0 0 4 &pic 13>, /* INT D on slot 10 is irq 13 */
/* IDSEL 11 */
<0x5800 0 0 1 &pic 15>, /* INT A on slot 11 is irq 15 */
<0x5800 0 0 2 &pic 16>, /* INT B on slot 11 is irq 16 */
<0x5800 0 0 3 &pic 13>, /* INT C on slot 11 is irq 13 */
<0x5800 0 0 4 &pic 14>, /* INT D on slot 11 is irq 14 */
/* IDSEL 12 */
<0x6000 0 0 1 &pic 16>, /* INT A on slot 12 is irq 16 */
<0x6000 0 0 2 &pic 13>, /* INT B on slot 12 is irq 13 */
<0x6000 0 0 3 &pic 14>, /* INT C on slot 12 is irq 14 */
<0x6000 0 0 4 &pic 15>; /* INT D on slot 12 is irq 15 */
};
...

76
Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
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@ -1,76 +0,0 @@
V3 Semiconductor V360 EPC PCI bridge
This bridge is found in the ARM Integrator/AP (Application Platform)
Required properties:
- compatible: should be one of:
"v3,v360epc-pci"
"arm,integrator-ap-pci", "v3,v360epc-pci"
- reg: should contain two register areas:
first the base address of the V3 host bridge controller, 64KB
second the configuration area register space, 16MB
- interrupts: should contain a reference to the V3 error interrupt
as routed on the system.
- bus-range: see pci.txt
- ranges: this follows the standard PCI bindings in the IEEE Std
1275-1994 (see pci.txt) with the following restriction:
- The non-prefetchable and prefetchable memory windows must
each be exactly 256MB (0x10000000) in size.
- The prefetchable memory window must be immediately adjacent
to the non-prefetcable memory window
- dma-ranges: three ranges for the inbound memory region. The ranges must
be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
as pre-fetchable. Two ranges are supported by the hardware.
Integrator-specific required properties:
- syscon: should contain a link to the syscon device node, since
on the Integrator, some registers in the syscon are required to
operate the V3 host bridge.
Example:
pci: pciv3@62000000 {
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
interrupt-parent = <&pic>;
interrupts = <17>; /* Bus error IRQ */
clocks = <&pciclk>;
bus-range = <0x00 0xff>;
ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
0x02000000 0 0x80000000 /* Core module alias memory */
0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
interrupt-map-mask = <0xf800 0 0 0x7>;
interrupt-map = <
/* IDSEL 9 */
0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
/* IDSEL 10 */
0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
/* IDSEL 11 */
0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
/* IDSEL 12 */
0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
>;
};

112
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
View File

@ -76,64 +76,62 @@ unevaluatedProperties: false
examples:
- |
versal {
#address-cells = <2>;
#size-cells = <2>;
cpm_pcie: pcie@fca10000 {
compatible = "xlnx,versal-cpm-host-1.00";
device_type = "pci";
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupts = <0 72 4>;
interrupt-parent = <&gic>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
<0 0 0 2 &pcie_intc_0 1>,
<0 0 0 3 &pcie_intc_0 2>,
<0 0 0 4 &pcie_intc_0 3>;
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
msi-map = <0x0 &its_gic 0x0 0x10000>;
reg = <0x0 0xfca10000 0x0 0x1000>,
<0x6 0x00000000 0x0 0x10000000>;
reg-names = "cpm_slcr", "cfg";
pcie_intc_0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
#address-cells = <2>;
#size-cells = <2>;
pcie@fca10000 {
compatible = "xlnx,versal-cpm-host-1.00";
device_type = "pci";
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupts = <0 72 4>;
interrupt-parent = <&gic>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
<0 0 0 2 &pcie_intc_0 1>,
<0 0 0 3 &pcie_intc_0 2>,
<0 0 0 4 &pcie_intc_0 3>;
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
msi-map = <0x0 &its_gic 0x0 0x10000>;
reg = <0x0 0xfca10000 0x0 0x1000>,
<0x6 0x00000000 0x0 0x10000000>;
reg-names = "cpm_slcr", "cfg";
pcie_intc_0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpm5_pcie: pcie@fcdd0000 {
compatible = "xlnx,versal-cpm5-host";
device_type = "pci";
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupts = <0 72 4>;
interrupt-parent = <&gic>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
<0 0 0 2 &pcie_intc_1 1>,
<0 0 0 3 &pcie_intc_1 2>,
<0 0 0 4 &pcie_intc_1 3>;
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
msi-map = <0x0 &its_gic 0x0 0x10000>;
reg = <0x00 0xfcdd0000 0x00 0x1000>,
<0x06 0x00000000 0x00 0x1000000>,
<0x00 0xfce20000 0x00 0x1000000>;
reg-names = "cpm_slcr", "cfg", "cpm_csr";
pcie_intc_1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
pcie@fcdd0000 {
compatible = "xlnx,versal-cpm5-host";
device_type = "pci";
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupts = <0 72 4>;
interrupt-parent = <&gic>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
<0 0 0 2 &pcie_intc_1 1>,
<0 0 0 3 &pcie_intc_1 2>,
<0 0 0 4 &pcie_intc_1 3>;
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
msi-map = <0x0 &its_gic 0x0 0x10000>;
reg = <0x00 0xfcdd0000 0x00 0x1000>,
<0x06 0x00000000 0x00 0x1000000>,
<0x00 0xfce20000 0x00 0x1000000>;
reg-names = "cpm_slcr", "cfg", "cpm_csr";
pcie_intc_1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};

4
MAINTAINERS
View File

@ -18411,7 +18411,7 @@ M: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
L: linux-pci@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/pci/pci-armada8k.txt
F: Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml
F: drivers/pci/controller/dwc/pcie-armada8k.c
PCI DRIVER FOR CADENCE PCIE IP
@ -18569,7 +18569,7 @@ PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
F: Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml
F: drivers/pci/controller/pci-v3-semi.c
PCI DRIVER FOR XILINX VERSAL CPM