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arm64: dts: st: add i2s support to stm32mp251

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Add I2S support to STM32MP25 SoCs.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Olivier Moysan 2024-11-13 09:25:09 +01:00 committed by Alexandre Torgue
parent 40384c840e
commit 279f8c8d30
1 changed files with 45 additions and 0 deletions
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45
arch/arm64/boot/dts/st/stm32mp251.dtsi
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@ -237,6 +237,21 @@ rifsc: bus@42080000 {
#access-controller-cells = <1>;
ranges;
i2s2: audio-controller@400b0000 {
compatible = "st,stm32mp25-i2s";
reg = <0x400b0000 0x400>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
clock-names = "pclk", "i2sclk";
resets = <&rcc SPI2_R>;
dmas = <&hpdma 51 0x43 0x12>,
<&hpdma 52 0x43 0x21>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 23>;
status = "disabled";
};
spi2: spi@400b0000 {
#address-cells = <1>;
#size-cells = <0>;
@ -252,6 +267,21 @@ spi2: spi@400b0000 {
status = "disabled";
};
i2s3: audio-controller@400c0000 {
compatible = "st,stm32mp25-i2s";
reg = <0x400c0000 0x400>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
clock-names = "pclk", "i2sclk";
resets = <&rcc SPI3_R>;
dmas = <&hpdma 53 0x43 0x12>,
<&hpdma 54 0x43 0x21>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 24>;
status = "disabled";
};
spi3: spi@400c0000 {
#address-cells = <1>;
#size-cells = <0>;
@ -439,6 +469,21 @@ usart6: serial@40220000 {
status = "disabled";
};
i2s1: audio-controller@40230000 {
compatible = "st,stm32mp25-i2s";
reg = <0x40230000 0x400>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>;
clock-names = "pclk", "i2sclk";
resets = <&rcc SPI1_R>;
dmas = <&hpdma 49 0x43 0x12>,
<&hpdma 50 0x43 0x21>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 22>;
status = "disabled";
};
spi1: spi@40230000 {
#address-cells = <1>;
#size-cells = <0>;