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dt-bindings: pinctrl: convert fsl,imx7ulp-pinctrl.txt to yaml format
Convert fsl,imx7ulp-pinctrl.txt to yaml format. Additional changes: - remove label in example - fsl,pin direct use hex value instead of macro because macro define in dts local directory. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20250417152158.3570936-1-Frank.Li@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Frank Li
Linus Walleij
parent
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commit
278114ccfd
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx7ulp-iomuxc1.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX7ULP IOMUX Controller
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description: |
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i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
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ports and IOMUXC DDR for DDR interface.
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Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it
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only supports generic pin config.
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Please refer to fsl,imx-pinctrl.txt in this directory for common binding
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part and usage.
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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const: fsl,imx7ulp-iomuxc1
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reg:
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maxItems: 1
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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Each entry consists of 5 integers which represents the mux
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and config setting for one pin. The first 4 integers
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<mux_conf_reg input_reg mux_mode input_val> are specified
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using a PIN_FUNC_ID macro, which can be found in
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imx7ulp-pinfunc.h in the device tree source folder.
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The last integer CONFIG is the pad setting value like
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pull-up on this pin.
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Please refer to i.MX7ULP Reference Manual for detailed
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CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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"mux_conf_reg" indicates the offset of mux register.
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- description: |
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_mode" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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CONFIG bits definition:
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PAD_CTL_OBE (1 << 17)
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PAD_CTL_IBE (1 << 16)
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PAD_CTL_LK (1 << 16)
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PAD_CTL_DSE_HI (1 << 6)
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PAD_CTL_DSE_STD (0 << 6)
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PAD_CTL_ODE (1 << 5)
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PAD_CTL_PUSH_PULL (0 << 5)
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PAD_CTL_SRE_SLOW (1 << 2)
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PAD_CTL_SRE_STD (0 << 2)
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PAD_CTL_PE (1 << 0)
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required:
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- fsl,pins
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additionalProperties: false
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required:
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- compatible
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- reg
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allOf:
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- $ref: pinctrl.yaml#
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unevaluatedProperties: false
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examples:
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- |
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pinctrl@40ac0000 {
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compatible = "fsl,imx7ulp-iomuxc1";
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reg = <0x40ac0000 0x1000>;
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lpuart4grp {
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fsl,pins = <
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0x000c 0x0248 0x4 0x1 0x1
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0x0008 0x024c 0x4 0x1 0x1
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>;
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};
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};
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@ -1,53 +0,0 @@
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* Freescale i.MX7ULP IOMUX Controller
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i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
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ports and IOMUXC DDR for DDR interface.
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Note:
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This binding doc is only for the IOMUXC1 support in A7 Domain and it only
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supports generic pin config.
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Please refer to fsl,imx-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "fsl,imx7ulp-iomuxc1".
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- fsl,pins: Each entry consists of 5 integers which represents the mux
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and config setting for one pin. The first 4 integers
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<mux_conf_reg input_reg mux_mode input_val> are specified
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using a PIN_FUNC_ID macro, which can be found in
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imx7ulp-pinfunc.h in the device tree source folder.
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The last integer CONFIG is the pad setting value like
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pull-up on this pin.
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Please refer to i.MX7ULP Reference Manual for detailed
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CONFIG settings.
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CONFIG bits definition:
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PAD_CTL_OBE (1 << 17)
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PAD_CTL_IBE (1 << 16)
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PAD_CTL_LK (1 << 16)
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PAD_CTL_DSE_HI (1 << 6)
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PAD_CTL_DSE_STD (0 << 6)
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PAD_CTL_ODE (1 << 5)
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PAD_CTL_PUSH_PULL (0 << 5)
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PAD_CTL_SRE_SLOW (1 << 2)
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PAD_CTL_SRE_STD (0 << 2)
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PAD_CTL_PE (1 << 0)
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Examples:
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#include "imx7ulp-pinfunc.h"
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/* Pin Controller Node */
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iomuxc1: pinctrl@40ac0000 {
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compatible = "fsl,imx7ulp-iomuxc1";
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reg = <0x40ac0000 0x1000>;
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/* Pin Configuration Node */
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x1
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x1
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>;
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};
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};
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