From fb4ce97d9c5daafe100a83670c697b92c9d1bb45 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Mon, 20 Jun 2022 14:30:18 +0200 Subject: [PATCH 01/28] ARM: dts: stm32: add fake interrupt propoerty for ASync notif - TEMP/TO REMOVE Current internal optee version enables ASYNc notif and in suche case interrupt is mandatory in optee node. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index dd35a607073d..47dc07abe4e3 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -33,6 +33,8 @@ firmware { optee { method = "smc"; compatible = "linaro,optee-tz"; + interrupt-parent = <&intc>; + interrupts = ; }; scmi: scmi { From ee9b7263a7d0d77198cec510e4a3e759dd85c65c Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 21 Sep 2022 18:03:34 +0200 Subject: [PATCH 02/28] ARM: dts: stm32: add sdmmc cd-gpios for STM32MP135F-DK On STM32MP135F-DK, the SD card detect GPIO is GPIOH4. Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index de341d17e87d..5cdd9e3756a8 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -108,7 +108,7 @@ &sdmmc1 { pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; + cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,neg-edge; bus-width = <4>; From 3b835f1b8acef53c8882b25f40f48d7f5982c938 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 23 Sep 2022 04:37:45 +0200 Subject: [PATCH 03/28] ARM: dts: stm32: Drop stm32mp15xc.dtsi from Avenger96 The Avenger96 is populated with STM32MP157A DHCOR SoM, drop the stm32mp15xc.dtsi which should only be included in DTs of devices which are populated with STM32MP15xC/F SoC as the stm32mp15xc.dtsi enables CRYP block not present in the STM32MP15xA/D SoC . Fixes: 7e76f82acd9e1 ("ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board") Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Reviewed-by: Manivannan Sadhasivam Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts index 2e3c9fbb4eb3..275167f26fd9 100644 --- a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts @@ -13,7 +13,6 @@ /dts-v1/; #include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" #include "stm32mp15xx-dhcor-som.dtsi" #include "stm32mp15xx-dhcor-avenger96.dtsi" From a306d8962a24f4e8385853793fd58f9792c7aa61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 27 Sep 2022 00:44:37 +0200 Subject: [PATCH 04/28] ARM: dts: stm32: Rename mdio0 to mdio Replace "mdio0" node with "mdio" to match mdio.yaml DT schema. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi | 2 +- arch/arm/boot/dts/stm32mp157c-ev1.dts | 2 +- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 2 +- arch/arm/boot/dts/stm32mp157c-odyssey.dts | 2 +- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 2 +- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 2 +- arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi | 2 +- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi index 30156b7546ed..aef02e6421a3 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -173,7 +173,7 @@ ðernet0 { phy-handle = <&phy0>; st,eth-ref-clk-sel; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 050c3c27a420..b72d5e8aa466 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -144,7 +144,7 @@ ðernet0 { max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index e8d2ec41d537..cb00ce7cec8b 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -112,7 +112,7 @@ ðernet0 { phy-handle = <ðphy>; status = "okay"; - mdio0 { + mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts index ed66d25b8bf3..a8b3f7a54703 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -41,7 +41,7 @@ ðernet0 { assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */ st,eth-clk-sel; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 238a611192e7..002f221f1694 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -125,7 +125,7 @@ ðernet0 { max-speed = <100>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 90933077d66d..6f7dbabe3f35 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -151,7 +151,7 @@ ðernet0 { max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi index 27477bb219de..c32c160f97f2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -78,7 +78,7 @@ ðernet0 { max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 8b48d3c89a04..6afff983069b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -141,7 +141,7 @@ ðernet0 { max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; From 5447215589a4bb989388c193e52e9e8abcdc4bde Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 27 Sep 2022 01:34:57 +0200 Subject: [PATCH 05/28] ARM: dts: stm32: Drop linux,default-trigger = "none" from AV96 The default-trigger setting set to none has no impact and triggers DT dtbs_check warning, remove it: " arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dtb: led: led4:linux,default-trigger: 'oneOf' conditional failed, one must be fixed: " Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 6f7dbabe3f35..03ab2cb2b829 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -66,7 +66,6 @@ led3 { led4 { label = "green:user3"; gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; default-state = "off"; panic-indicator; }; From 0a5ebb1f33679b83599af86135631d07c59201cd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 27 Sep 2022 02:20:23 +0200 Subject: [PATCH 06/28] ARM: dts: stm32: Replace SAI format with dai-format DT property The dai-format and format are handled equally by sound-core.c , the later is however the only documented property in audio-graph-port.yaml . Switch to the later. Signed-off-by: Marek Vasut Reviewed-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 4 ++-- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 2 +- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 5f586f024060..4709677151aa 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -242,7 +242,7 @@ sai2a: audio-controller@4400b004 { sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&sgtl5000_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <512>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; @@ -260,7 +260,7 @@ sai2b: audio-controller@4400b024 { sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&sgtl5000_rx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <512>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 03ab2cb2b829..305f9ae2fceb 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -358,7 +358,7 @@ sai2a: audio-controller@4400b004 { sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&adv7513_i2s0>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 6afff983069b..7798a2e17c5c 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -508,7 +508,7 @@ sai2a: audio-controller@4400b004 { sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&cs42l51_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; @@ -526,7 +526,7 @@ sai2b: audio-controller@4400b024 { sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&cs42l51_rx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; From 212972124422948f82b1994ce5c7032d13475827 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Sep 2022 23:29:57 +0200 Subject: [PATCH 07/28] dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR Testbench board Add DT compatible string for DHCOR Testbench board, which is a testbench for testing of DHCOR SoM during manufacturing. This is effectively a trimmed down version of AV96 board with CSI-2 bridge, HDMI bridge, WiFi, Audio and LEDs removed and used as GPIOs instead. Signed-off-by: Marek Vasut Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 4c605bccc474..44f5c5855af8 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -59,6 +59,12 @@ properties: - prt,prtt1s # Protonic PRTT1S - const: st,stm32mp151 + - description: DH STM32MP151 DHCOR SoM based Boards + items: + - const: dh,stm32mp151a-dhcor-testbench + - const: dh,stm32mp151a-dhcor-som + - const: st,stm32mp151 + - description: DH STM32MP153 DHCOM SoM based Boards items: - const: dh,stm32mp153c-dhcom-drc02 From c8ce0dd75515b0b05095b6d272d100b542b510aa Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Sep 2022 23:29:58 +0200 Subject: [PATCH 08/28] ARM: dts: stm32: Add DHCOR based Testbench board Add DT for DHCOR Testbench board, which is a testbench for testing of DHCOR SoM during manufacturing. This is effectively a trimmed down version of AV96 board with CSI-2 bridge, HDMI bridge, WiFi, Audio and LEDs removed and used as GPIOs instead. Furthermore, the PMIC Buck3 is always configured from PMIC NVM to cater for both 1V8 and 3V3 SoM variant. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/stm32mp151a-dhcor-testbench.dts | 17 ++ .../boot/dts/stm32mp15xx-dhcor-testbench.dtsi | 171 ++++++++++++++++++ 3 files changed, 189 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6aa7dc4db2fc..3a4099ad59b4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1214,6 +1214,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151a-prtt1a.dtb \ stm32mp151a-prtt1c.dtb \ stm32mp151a-prtt1s.dtb \ + stm32mp151a-dhcor-testbench.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ stm32mp157a-avenger96.dtb \ diff --git a/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts b/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts new file mode 100644 index 000000000000..e0f828ecc2fa --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + */ + +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-testbench.dtsi" + +/ { + model = "DH electronics STM32MP151A DHCOR Testbench"; + compatible = "dh,stm32mp151a-dhcor-testbench", + "dh,stm32mp151a-dhcor-som", + "st,stm32mp151"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi new file mode 100644 index 000000000000..c7dcee4ee3d1 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + */ + +/ { + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &uart7; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; From ad9591b01d24a72f2770949709eece100fab88f7 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 30 Sep 2022 16:56:43 +0200 Subject: [PATCH 09/28] ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1 Add support for USB2514B onboard hub on stm32mp157c EV1 board. The HUB is supplied by a 3v3 PMIC regulator. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index b72d5e8aa466..23ca0b7024e5 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -370,6 +370,14 @@ &usart3 { &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3>; + }; }; &usbotg_hs { From 43e55d778a6b4e28a126fac28af0889fe2a54c3b Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 30 Sep 2022 17:02:32 +0200 Subject: [PATCH 10/28] ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1 phy-stm32-usbphyc bindings uses a connector node with vbus-supply property. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 23ca0b7024e5..a665189fe621 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -401,6 +401,11 @@ &usbphyc_port0 { st,tune-squelch-level = <3>; st,tune-hs-rx-offset = <2>; st,no-lsfs-sc; + + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; }; &usbphyc_port1 { From 14778e3a8648e4f909bb284e12adde8b5cd0198a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 14 Oct 2022 00:12:42 +0200 Subject: [PATCH 11/28] ARM: dts: stm32: Drop MMCI interrupt-names The pl18x MMCI driver does not use the interrupt-names property, the binding document has been updated to recommend this property be unused, remove it. Reviewed-by: Linus Walleij Reviewed-by: Yann Gautier Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 2 -- arch/arm/boot/dts/stm32mp131.dtsi | 2 -- arch/arm/boot/dts/stm32mp151.dtsi | 3 --- 3 files changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 2059593da21d..28e3deb20e1e 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -375,7 +375,6 @@ sdmmc1: mmc@52007000 { arm,primecell-periphid = <0x10153180>; reg = <0x52007000 0x1000>; interrupts = <49>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; @@ -389,7 +388,6 @@ sdmmc2: mmc@48022400 { arm,primecell-periphid = <0x10153180>; reg = <0x48022400 0x400>; interrupts = <124>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 47dc07abe4e3..4c9e095ed2a8 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -356,7 +356,6 @@ sdmmc1: mmc@58005000 { arm,primecell-periphid = <0x20253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; @@ -371,7 +370,6 @@ sdmmc2: mmc@58007000 { arm,primecell-periphid = <0x20253180>; reg = <0x58007000 0x1000>, <0x58008000 0x1000>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index e02b3f5d44cb..5491b6c4dec2 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1118,7 +1118,6 @@ sdmmc3: mmc@48004000 { arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC3_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC3_R>; @@ -1439,7 +1438,6 @@ sdmmc1: mmc@58005000 { arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; @@ -1454,7 +1452,6 @@ sdmmc2: mmc@58007000 { arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; From ccdab19738a6dccbb8addf05f7d0d121d97abcfa Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Wed, 12 Oct 2022 16:22:02 +0200 Subject: [PATCH 12/28] ARM: dts: stm32: add adc support to stm32mp13 Add ADC1 and ADC2 support to STM32MP13 SoC family. The STM32MP131 provides only ADC2, while other STM32MP13 SoCs provide both ADC1 and ADC2. Internal channels support limitations: - VREFINT internal channel requires calibration data from OTP memory. The nvmem properties used to access OTP are not defined for time being, as OTP support is not yet enabled. - VBAT internal channel is not defined by default in SoC DT, and has be defined in board DT when needed, instead. This avoids unwanted current consumption on battery, when ADC conversions are performed on any other channels. Signed-off-by: Olivier Moysan Reviewed-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 43 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp133.dtsi | 31 ++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 4c9e095ed2a8..c9777a8aea08 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -233,6 +233,49 @@ dmamux1: dma-router@48002000 { dma-channels = <16>; }; + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = ; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + spi4: spi@4c002000 { compatible = "st,stm32h7-spi"; reg = <0x4c002000 0x400>; diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi index 531c263c9f46..df451c3c2a26 100644 --- a/arch/arm/boot/dts/stm32mp133.dtsi +++ b/arch/arm/boot/dts/stm32mp133.dtsi @@ -33,5 +33,36 @@ m_can2: can@4400f000 { bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = ; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@18 { + reg = <18>; + label = "vrefint"; + }; + }; + }; }; }; From 022932ab55fd0181aa3cf52f8c757b74acf01131 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Wed, 12 Oct 2022 16:22:03 +0200 Subject: [PATCH 13/28] ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk Define pins muxing that can be used for ADC on stm32mp135f-dk board (USB Type-C CC1 & CC2 pins). Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index efdd163eba30..50daf5509193 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,13 @@ #include &pinctrl { + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { + pins { + pinmux = , /* ADC1 in6 */ + ; /* ADC1 in12 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ From ab2806ddad9d94e449f962a15035846c80f89738 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Wed, 12 Oct 2022 16:22:04 +0200 Subject: [PATCH 14/28] ARM: dts: stm32: add dummy vdd_adc regulator on stm32mp135f-dk Add a dummy fixed regulator vdd-adc for STM32 ADC, on STM32MP135F-DK board, while SCMI regulators are not available. This patch will have to be removed when SCMI regulator support is added to STM32MP13. This patch intends to allow ADC enabling on STM32MP13. With this patch the ADC can probe but it cannot return valid conversion data, as it's regulator is not actually enabled. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 5cdd9e3756a8..c1c4b5ac8128 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -59,6 +59,14 @@ led-blue { }; }; + vdd_adc: vdd-adc { + compatible = "regulator-fixed"; + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; From e46a180c060f5a025aee783ef10bcb95b767f6f8 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Wed, 12 Oct 2022 16:22:05 +0200 Subject: [PATCH 15/28] ARM: dts: stm32: add adc support on stm32mp135f-dk Configure ADC support on stm32mp135f-dk. ADC can be used for USB Type-C CC1 & CC2 pins wired to in6 & in12. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index c1c4b5ac8128..a87ab067c955 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -76,6 +76,31 @@ vdd_sd: vdd-sd { }; }; +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_usb_cc_pins_a>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + adc1: adc@0 { + status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + */ + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; From d5d577e3d50713ad11d98dbdaa48bb494346c26d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 21 Oct 2022 12:00:57 +0200 Subject: [PATCH 16/28] ARM: dts: stm32: Fix AV96 WLAN regulator gpio property The WLAN regulator uses 'gpios' property instead of 'gpio' to specify regulator enable GPIO. While the former is also currently handled by the Linux kernel regulator-fixed driver, the later is the correct one per DT bindings. Update the DT to use the later. Fixes: 7dd5cbba42c93 ("ARM: dts: stm32: Enable WiFi on AV96") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 305f9ae2fceb..50af4a27d6be 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -99,7 +99,7 @@ wlan_pwr: regulator-wlan { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + gpio = <&gpioz 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; From acdce5cde8fe2a7200d1bf31f73edf08c78c8e26 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 14 Oct 2022 16:15:00 +0200 Subject: [PATCH 17/28] ARM: dts: stm32: add PWR fixed regulators on stm32mp131 Add 1v1, 1v8 and 3v3 PWR regulators on stm32mp131. Temporary add them as fixed regulators, waiting for full SCMI regulators support. This is a precursor patch to enable USB support on STM32MP13. Note: USB support requires these regulators to be enabled before entering kernel. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index c9777a8aea08..d9a713c2e0e8 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -79,6 +79,28 @@ timer { always-on; }; + /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ + reg11: reg11 { + compatible = "regulator-fixed"; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + compatible = "regulator-fixed"; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + compatible = "regulator-fixed"; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; From f54271ff0c694876ed34081f562579b5c25aad88 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 14 Oct 2022 16:15:01 +0200 Subject: [PATCH 18/28] ARM: dts: stm32: add USBPHYC and dual USB HS PHY support on stm32mp131 This patch adds support for USBPHYC and its two USB HS PHY on stm32mp131. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index d9a713c2e0e8..4610af17d554 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -452,6 +452,29 @@ iwdg2: watchdog@5a002000 { status = "disabled"; }; + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; From 4a47f0f3e936496fcf7961ee99a412b06a97ff33 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 14 Oct 2022 16:15:02 +0200 Subject: [PATCH 19/28] ARM: dts: stm32: add UBSH EHCI and OHCI support on stm32mp131 This patch adds USB Host EHCI and OHCI support on stm32mp131. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 4610af17d554..a72170b59d7e 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -444,6 +444,25 @@ sdmmc2: mmc@58007000 { status = "disabled"; }; + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; + }; + + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; + status = "disabled"; + }; + iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; From 2a46bb66c47ff3ef8e4cfd3936cbabca58a546f6 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 14 Oct 2022 16:15:03 +0200 Subject: [PATCH 20/28] ARM: dts: stm32: add USB OTG HS support on stm32mp131 This patch adds USB OTG HS support on stm32mp131. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index a72170b59d7e..2a9b3a5bba83 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -298,6 +298,23 @@ channel@17 { }; }; + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + spi4: spi@4c002000 { compatible = "st,stm32h7-spi"; reg = <0x4c002000 0x400>; From 9ebf215fbae109f617d90ac1754feaeedaed2011 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 14 Oct 2022 16:15:04 +0200 Subject: [PATCH 21/28] ARM: dts: stm32: add fixed regulators to support usb on stm32mp135f-dk Add VDD_USB and 3V3_SW regulators on stm32mp135f-dk. Temporary add them as fixed regulators, waiting for full SCMI regulators support. This is a precursor patch to enable USB support on STM32MP13: - VDD_USB supplies the STM32MP13 USB internals - 3V3_SW supplies various peripherals, including the onboard HUB. Note: USB support requires these regulators to be enabled before entering the kernel. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index a87ab067c955..edf4b3c7c434 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -59,6 +59,14 @@ led-blue { }; }; + v3v3_sw: v3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd_adc: vdd-adc { compatible = "regulator-fixed"; regulator-name = "vdd_adc"; @@ -74,6 +82,14 @@ vdd_sd: vdd-sd { regulator-max-microvolt = <2900000>; regulator-always-on; }; + + vdd_usb: vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &adc_1 { From 16f4ff60519a225860c62932357896be45edd07a Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 14 Oct 2022 16:15:05 +0200 Subject: [PATCH 22/28] ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk USBPHYC manages the two USB High-Speed phys. port0 is used by USBH and port1 is used by USBOTG. Enable and tune both PHYs on stm32mp135f-dk. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index edf4b3c7c434..ae65badd79bb 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -177,3 +177,35 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; status = "okay"; }; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; From c4e7254cf6dce9db7a635f8e79c8399f60e37ff7 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 14 Oct 2022 16:15:06 +0200 Subject: [PATCH 23/28] ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk USBH Host EHCI controller manages the USB High-Speed hub controller IC offering Type-A CN5 & CN6 connectors available on stm32mp135f-dk. USB Host OHCI controller doesn't need to be enabled as Full-Speed and Low-Speed traffic will be managed by the hub. This USB2514B onboard hub is supplied by a 3v3 PMIC regulator. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index ae65badd79bb..364d2c86d546 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -178,6 +178,19 @@ &uart4 { status = "okay"; }; +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3_sw>; + }; +}; + &usbphyc { status = "okay"; }; From 44978e1359168ad0604235f0b36d7df7721ad85f Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 14 Oct 2022 16:15:07 +0200 Subject: [PATCH 24/28] ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13 Add gpio pin configuration to be used with stm32g0 typec controller. Define the PI2 to enable internal pull-up on stm32mp13, used as interrupt pin on stm32mp135f-dk board. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index 50daf5509193..0dda449fd55d 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -172,6 +172,13 @@ pins { }; }; + stm32g0_intn_pins_a: stm32g0-intn-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ From 4f532403b1e5b379e4027448da715567a2b3ff57 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 14 Oct 2022 16:15:08 +0200 Subject: [PATCH 25/28] ARM: dts: stm32: enable USB OTG in dual role mode on stm32mp135f-dk The USB OTG controller provides the USB data available on stm32mp135f-dk, on the Type-C connector. Data role is determined by "usb-role-switch". A STM32G0 provides the USB Type-C and Power Delivery connectivity. It controls dual role power and dual role data through UCSI protocol over I2C. It's wired on I2C1, with an interrupt pin on PI2 GPIO. Its firmware maybe updated over I2C, so use the optional firmware-name to enable firmware update. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 34 ++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 364d2c86d546..b7bf36b802dc 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -128,6 +128,28 @@ &i2c1 { /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; + + typec@53 { + compatible = "st,stm32g0-typec"; + reg = <0x53>; + /* Alert pin on PI2 */ + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + /* Internal pull-up on PI2 */ + pinctrl-names = "default"; + pinctrl-0 = <&stm32g0_intn_pins_a>; + firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + con_usb_c_g0_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; }; &i2c5 { @@ -191,6 +213,18 @@ hub@1 { }; }; +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + status = "okay"; + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usb_c_g0_ep>; + }; + }; +}; + &usbphyc { status = "okay"; }; From e1f15571c96c765891c36651324a74ad9fd872ae Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Mon, 24 Oct 2022 11:46:47 +0200 Subject: [PATCH 26/28] ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13 MCP23017 interrupt line (routed on PG12) requires to be pulled-up. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index 0dda449fd55d..d377d4c0bef5 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -47,6 +47,13 @@ pins { }; }; + mcp23017_pins_a: mcp23017-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = , /* SDMMC1_D0 */ From 6cc71374002e90bd0caadfb1d2c2bfaa8fb7d92a Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Mon, 24 Oct 2022 11:46:48 +0200 Subject: [PATCH 27/28] ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk MCP23017 is an IO expander offering 16 input/output port expander with interrupt output. On stm32mp135f-dk, only INTA is routed (on PG12), but MCP23017 can mirror the bank B interrupts on INTA, that's why the property microchip,irq-mirror is used. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index b7bf36b802dc..9ff5a3eaf55b 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -129,6 +129,20 @@ &i2c1 { /delete-property/dmas; /delete-property/dma-names; + mcp23017: pinctrl@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp23017_pins_a>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,irq-mirror; + }; + typec@53 { compatible = "st,stm32g0-typec"; reg = <0x53>; From d8515330a63eda80ac7ad8423de535b747bb2c46 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Oct 2022 20:38:26 +0200 Subject: [PATCH 28/28] ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench board Replace "mdio0" node with "mdio" to match mdio.yaml DT schema. Fixes: c8ce0dd75515b ("ARM: dts: stm32: Add DHCOR based Testbench board") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi index c7dcee4ee3d1..5fdb74b652ac 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi @@ -62,7 +62,7 @@ ðernet0 { max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio";