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drm/amd/display: fix dcn3.1x mode validation on high bandwidth config

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[why]
1. correct dram_channel_width (was hard coded to 4 for 32bit)
2. use dm's is_hvm_enable status flag for hostvm_en input for dml.
3. add a function to override to all dcn3.1x.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2022-11-02 12:13:43 -04:00 committed by Alex Deucher
parent 5b8f9deaf3
commit 27142312c8
9 changed files with 90 additions and 19 deletions
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4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
View File

@ -609,8 +609,10 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk
}
bw_params->vram_type = bios_info->memory_type;
bw_params->num_channels = bios_info->ma_channel_number;
bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
//bw_params->dram_channel_width_bytes = dc->ctx->asic_id.vram_width;
bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
for (i = 0; i < WM_SET_COUNT; i++) {
bw_params->wm_table.entries[i].wm_inst = i;

1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
View File

@ -553,6 +553,7 @@ static void dcn316_clk_mgr_helper_populate_bw_params(
bw_params->vram_type = bios_info->memory_type;
bw_params->num_channels = bios_info->ma_channel_number;
bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
for (i = 0; i < WM_SET_COUNT; i++) {
bw_params->wm_table.entries[i].wm_inst = i;

33
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
View File

@ -1639,6 +1639,31 @@ static bool is_dual_plane(enum surface_pixel_format format)
return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
}
int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
bool fast_validate)
{
uint32_t pipe_cnt;
int i;
dc_assert_fp_enabled();
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
for (i = 0; i < pipe_cnt; i++) {
pipes[i].pipe.src.gpuvm = 1;
if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {
//pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;
} else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
pipes[i].pipe.src.hostvm = false;
else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
pipes[i].pipe.src.hostvm = true;
}
return pipe_cnt;
}
int dcn31_populate_dml_pipes_from_context(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
@ -1650,7 +1675,7 @@ int dcn31_populate_dml_pipes_from_context(
bool upscaled = false;
DC_FP_START();
dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
DC_FP_END();
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
@ -1680,12 +1705,6 @@ int dcn31_populate_dml_pipes_from_context(
dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
DC_FP_END();
if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)
pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
pipes[pipe_cnt].pipe.src.hostvm = false;
else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
pipes[pipe_cnt].pipe.src.hostvm = true;
if (pipes[pipe_cnt].dout.dsc_enable) {
switch (timing->display_color_depth) {

3
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
View File

@ -1648,7 +1648,7 @@ static int dcn315_populate_dml_pipes_from_context(
const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
DC_FP_START();
dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
DC_FP_END();
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
@ -1667,7 +1667,6 @@ static int dcn315_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.src.immediate_flip = true;
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
pipes[pipe_cnt].pipe.src.gpuvm = true;
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
pipes[pipe_cnt].pipe.src.dcc_rate = 3;
pipes[pipe_cnt].dout.dsc_input_bpc = 0;

3
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
View File

@ -1650,7 +1650,7 @@ static int dcn316_populate_dml_pipes_from_context(
const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
DC_FP_START();
dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
DC_FP_END();
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
@ -1669,7 +1669,6 @@ static int dcn316_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.src.immediate_flip = true;
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
pipes[pipe_cnt].pipe.src.gpuvm = true;
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
pipes[pipe_cnt].pipe.src.dcc_rate = 3;
pipes[pipe_cnt].dout.dsc_input_bpc = 0;

4
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
View File

@ -47,4 +47,8 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
bool fast_validate);
#endif /* __DCN31_FPU_H__*/

54
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
View File

@ -1056,14 +1056,12 @@ static bool CalculatePrefetchSchedule(
prefetch_bw_pr = dml_min(1, myPipe->VRatio) * prefetch_bw_pr;
max_Tsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC;
prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerPlane, prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime));
prefetch_bw_oto = dml_max(prefetch_bw_pr, prefetch_sw_bytes / max_Tsw);
min_Lsw = dml_max(1, dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre);
Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
Tsw_oto = Lsw_oto * LineTime;
prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC) / Tsw_oto;
#ifdef __DML_VBA_DEBUG__
dml_print("DML: HTotal: %d\n", myPipe->HTotal);
@ -5362,6 +5360,58 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
v->ModeSupport[i][j] = true;
} else {
v->ModeSupport[i][j] = false;
#ifdef __DML_VBA_DEBUG__
if (v->ScaleRatioAndTapsSupport == false)
dml_print("DML SUPPORT: ScaleRatioAndTapsSupport failed");
if (v->SourceFormatPixelAndScanSupport == false)
dml_print("DML SUPPORT: SourceFormatPixelAndScanSupport failed");
if (v->ViewportSizeSupport[i][j] == false)
dml_print("DML SUPPORT: ViewportSizeSupport failed");
if (v->LinkCapacitySupport[i] == false)
dml_print("DML SUPPORT: LinkCapacitySupport failed");
if (v->ODMCombine4To1SupportCheckOK[i] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
if (v->NotEnoughDSCUnits[i] == true)
dml_print("DML SUPPORT: NotEnoughDSCUnits");
if (v->DTBCLKRequiredMoreThanSupported[i] == true)
dml_print("DML SUPPORT: DTBCLKRequiredMoreThanSupported");
if (v->ROBSupport[i][j] == false)
dml_print("DML SUPPORT: ROBSupport failed");
if (v->DISPCLK_DPPCLK_Support[i][j] == false)
dml_print("DML SUPPORT: DISPCLK_DPPCLK_Support failed");
if (v->TotalAvailablePipesSupport[i][j] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
if (EnoughWritebackUnits == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
if (v->WritebackLatencySupport == false)
dml_print("DML SUPPORT: WritebackLatencySupport failed");
if (v->WritebackScaleRatioAndTapsSupport == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported ");
if (v->CursorSupport == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
if (v->PitchSupport == false)
dml_print("DML SUPPORT: PitchSupport failed");
if (ViewportExceedsSurface == true)
dml_print("DML SUPPORT: ViewportExceedsSurface failed");
if (v->PrefetchSupported[i][j] == false)
dml_print("DML SUPPORT: PrefetchSupported failed");
if (v->DynamicMetadataSupported[i][j] == false)
dml_print("DML SUPPORT: DSC422NativeNotSupported failed");
if (v->TotalVerticalActiveBandwidthSupport[i][j] == false)
dml_print("DML SUPPORT: TotalVerticalActiveBandwidthSupport failed");
if (v->VRatioInPrefetchSupported[i][j] == false)
dml_print("DML SUPPORT: VRatioInPrefetchSupported failed");
if (v->PTEBufferSizeNotExceeded[i][j] == false)
dml_print("DML SUPPORT: PTEBufferSizeNotExceeded failed");
if (v->NonsupportedDSCInputBPC == true)
dml_print("DML SUPPORT: NonsupportedDSCInputBPC failed");
if (!((v->HostVMEnable == false
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
|| v->ImmediateFlipSupportedForState[i][j] == true))
dml_print("DML SUPPORT: ImmediateFlipRequirement failed");
if (FMTBufferExceeded == true)
dml_print("DML SUPPORT: FMTBufferExceeded failed");
#endif
}
}
}

5
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
View File

@ -29,6 +29,7 @@
#include "dcn31/dcn31_hubbub.h"
#include "dcn314_fpu.h"
#include "dml/dcn20/dcn20_fpu.h"
#include "dml/dcn31/dcn31_fpu.h"
#include "dml/display_mode_vba.h"
struct _vcs_dpi_ip_params_st dcn3_14_ip = {
@ -288,7 +289,7 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c
dc_assert_fp_enabled();
dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
struct dc_crtc_timing *timing;
@ -315,8 +316,6 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c
pipes[pipe_cnt].pipe.src.immediate_flip = true;
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
pipes[pipe_cnt].pipe.src.gpuvm = true;
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

2
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
View File

@ -1078,14 +1078,12 @@ static bool CalculatePrefetchSchedule(
prefetch_bw_pr = dml_min(1, myPipe->VRatio) * prefetch_bw_pr;
max_Tsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC;
prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerPlane, prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime));
prefetch_bw_oto = dml_max(prefetch_bw_pr, prefetch_sw_bytes / max_Tsw);
min_Lsw = dml_max(1, dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre);
Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
Tsw_oto = Lsw_oto * LineTime;
prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC) / Tsw_oto;
#ifdef __DML_VBA_DEBUG__
dml_print("DML: HTotal: %d\n", myPipe->HTotal);