From 270ef04c652dbd473dc437b1ea465e03e848aa5d Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 7 Jun 2018 10:47:25 +0800 Subject: [PATCH] clk: rockchip: rk3308: Add rate table for dpll DPLL isn't the parent clock of ddr, we may need to change dpll rate for other devices. Change-Id: I2b41ccf6df78803980be08e4b82cbfb5c7718b69 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3308.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c index b2655e530505..79f6f98c49ac 100644 --- a/drivers/clk/rockchip/clk-rk3308.c +++ b/drivers/clk/rockchip/clk-rk3308.c @@ -195,7 +195,7 @@ static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = { RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates), [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3308_PLL_CON(8), - RK3308_MODE_CON, 2, 1, 0, NULL), + RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates), [vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, 0, RK3308_PLL_CON(16), RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates),