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arm64: dts: rockchip: Add TS133 variant of the QNAP NAS series
The TS133 is a one-bay NAS mostly similar to the other devices in the series. The main difference is that it is build around the RK3566 SoC instead of the RK3568 variant. The RK3566/RK3568 are mostly similar with only slight variants in both speed and some specific peripherals - the RK3568 has more. The specific for the NAS series stay the same though. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20260104191448.2693309-6-heiko@sntech.de
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@ -114,6 +114,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb20sx.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb30.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rk2023.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
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71
arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts
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71
arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts
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@ -0,0 +1,71 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
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*/
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/dts-v1/;
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#include "rk3566.dtsi"
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#include "rk3568-qnap-tsx33.dtsi"
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/ {
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model = "Qnap TS-133-2G NAS System 1-Bay";
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compatible = "qnap,ts133", "rockchip,rk3566";
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aliases {
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ethernet0 = &gmac1;
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};
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};
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&gmac1 {
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus>;
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status = "okay";
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};
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&mcu {
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compatible = "qnap,ts133-mcu";
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};
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&mdio1 {
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rgmii_phy0: ethernet-phy@3 {
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/* Motorcomm YT8521 phy */
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x3>;
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pinctrl-0 = <ð_phy0_reset_pin>;
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pinctrl-names = "default";
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reset-assert-us = <10000>;
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reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
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};
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};
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&pinctrl {
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gmac1 {
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eth_phy0_reset_pin: eth-phy0-reset-pin {
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rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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/* connected to usb_host1_xhci */
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&usb2phy0_host {
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phy-supply = <&vcc5v0_otg>;
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status = "okay";
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};
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/* USB3 port on backside */
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&usb_host1_xhci {
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dr_mode = "host";
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status = "okay";
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};
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