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drm/amdgpu: Create hqd info structure
Create hung_queue_hqd_info structure and fill in hung queses information passed by MES, including queue type, pipe id, and queue id. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -448,7 +448,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
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{
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struct mes_detect_and_reset_queue_input input;
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u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id];
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int r, i;
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int hqd_info_offset = adev->mes.hung_queue_hqd_info_offset, r, i;
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if (!hung_db_num || !hung_db_array)
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return -EINVAL;
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@ -482,18 +482,13 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
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}
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}
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if (r && !hung_db_num) {
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if (r && !(*hung_db_num)) {
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dev_err(adev->dev, "Failed to detect and reset hung queues\n");
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return r;
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}
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/*
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* TODO: return HQD info for MES scheduled user compute queue reset cases
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* stored in hung_db_array hqd info offset to full array size
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*/
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if (r)
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dev_err(adev->dev, "failed to reset\n");
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for (i = hqd_info_offset; i < hqd_info_offset + *hung_db_num; i++)
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hung_db_array[i] = db_array[i];
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return r;
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}
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@ -170,6 +170,19 @@ struct amdgpu_mes {
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uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
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};
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struct amdgpu_mes_hung_queue_hqd_info {
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union {
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struct {
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u32 queue_type: 3; // queue type
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u32 pipe_index: 4; // pipe index
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u32 queue_index: 8; // queue index
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u32 reserved: 17;
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};
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u32 bit0_31;
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};
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};
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struct amdgpu_mes_gang {
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int gang_id;
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int priority;
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