From bc7b17594a17dbd752c42e203d3669f08bf0a4f9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 3 Jun 2026 16:19:52 +0200 Subject: [PATCH 1/9] arm64: dts: xilinx: drop bias-high-impedance on SDIO CD/WP pins Since commit 9c105255108b ("pinctrl: pinconf-generic: perform basic checks on pincfg properties"), the generic pinconf parser logs an error when a pin configuration node specifies more than one bias mode. Several ZynqMP boards described SDIO card-detect and write-protect pins with both bias-high-impedance and bias-pull-up, which triggers at pinctrl probe: generic pinconfig core: /firmware/zynqmp-firmware/pinctrl/.../conf-cd: cannot have multiple bias configurations On ZynqMP, bias-high-impedance enables tri-state while bias-pull-up enables the internal pull resistor; these are mutually exclusive bias settings and only pull-up is needed for CD/WP inputs. Drop the redundant bias-high-impedance property and keep bias-pull-up. Reported-by: Mikko Rapeli (Linaro) Closes: https://bugzilla.kernel.org/show_bug.cgi?id=221586 Link: https://patch.msgid.link/e01c8e60e1d9ed68c347f1a3741f89149109d8b7.1780496388.git.michal.simek@amd.com Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 - arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 ---- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 2 -- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 -- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 -- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 - 10 files changed, 16 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 923a70d750bf..44834bf1c19c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -374,7 +374,6 @@ conf { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 563e750b0e08..49732de5fa4b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -365,7 +365,6 @@ conf { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 6aff22d43361..f57987dad50f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -270,7 +270,6 @@ mux-cd { conf-cd { groups = "sdio0_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -283,7 +282,6 @@ mux-wp { conf-wp { groups = "sdio0_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -310,7 +308,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -323,7 +320,6 @@ mux-wp { conf-wp { groups = "sdio1_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index 53aa3dca1dca..737d445dc16b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -270,7 +270,6 @@ mux-cd { conf-cd { groups = "sdio0_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -283,7 +282,6 @@ mux-wp { conf-wp { groups = "sdio0_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 4ec8a400494e..41f312a82bb4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -320,7 +320,6 @@ mux-cd { conf-cd { groups = "sdio0_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index e172a30e7b21..a5bc521ab679 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -896,7 +896,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -909,7 +908,6 @@ mux-wp { conf-wp { groups = "sdio1_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index fe8f151ed706..32509083e54f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -359,7 +359,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 3ee8ab224722..96699be8430f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -371,7 +371,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7f6c87d4d77e..52441e5c8739 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -895,7 +895,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -908,7 +907,6 @@ mux-wp { conf-wp { groups = "sdio1_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 428b5558fbba..b34e4c93d249 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -750,7 +750,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; From 568248504d837ce271f44bbbb3810385092b33a2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 3 Jun 2026 16:19:53 +0200 Subject: [PATCH 2/9] arm: dts: xilinx: drop bias-high-impedance on SDIO CD/WP pins Zynq-7000 boards used the same invalid combination of bias-high-impedance and bias-pull-up on SDIO card-detect and write-protect pin groups. Keep only bias-pull-up, as in the arm64 ZynqMP fix. Link: https://patch.msgid.link/f8f0aa0d0a732127b5cb725871d06a7739f0a499.1780496388.git.michal.simek@amd.com Signed-off-by: Michal Simek --- arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts | 1 - arch/arm/boot/dts/xilinx/zynq-zc702.dts | 2 -- arch/arm/boot/dts/xilinx/zynq-zc706.dts | 2 -- 3 files changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts index 14f644156a6f..19b564019502 100644 --- a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts +++ b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts @@ -99,7 +99,6 @@ conf-cd { groups = "gpio0_34_grp"; io-standard = <3>; slew-rate = <0>; - bias-high-impedance; bias-pull-up; }; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts index 6955637c5b1a..36e919aea84c 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc702.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc702.dts @@ -324,7 +324,6 @@ mux-cd { conf-cd { groups = "gpio0_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; @@ -337,7 +336,6 @@ mux-wp { conf-wp { groups = "gpio0_15_grp"; - bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc706.dts b/arch/arm/boot/dts/xilinx/zynq-zc706.dts index 3b803c698473..1ce35eaa607b 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc706.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc706.dts @@ -237,7 +237,6 @@ mux-cd { conf-cd { groups = "gpio0_14_grp"; - bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; @@ -250,7 +249,6 @@ mux-wp { conf-wp { groups = "gpio0_15_grp"; - bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; From b881149621b235b8bd556c407d7cd76f0eeb3954 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:34:05 +0200 Subject: [PATCH 3/9] arm64: dts: xilinx: zynqmp-sck: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 44834bf1c19c..52954761c9f3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -218,23 +218,23 @@ &pinctrl0 { status = "okay"; pinctrl_gpio0_default: gpio0-default { - conf { - groups = "gpio0_38_grp"; - bias-pull-up; - power-source = ; - }; + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; - mux { - groups = "gpio0_38_grp"; - function = "gpio0"; - }; + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; - conf-tx { - pins = "MIO38"; - bias-disable; - output-enable; - }; - }; + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; pinctrl_uart1_default: uart1-default { conf { @@ -392,9 +392,9 @@ mux { }; &gpio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; }; &uart1 { From 50a8e96a1513760418e7f2e5bc51a7e48fc2b82e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 7 Jul 2026 10:32:09 +0200 Subject: [PATCH 4/9] dt-bindings: xilinx: Remove EDK/Ethernet references The latest EDK version was 14.7 released in 2013 that's why remove description for it. Also remove generic description for Ethernet which doesn't bring any value. Reviewed-by: Radhey Shyam Pandey Acked-by: Conor Dooley Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/xilinx.txt | 98 +------------------- 1 file changed, 1 insertion(+), 97 deletions(-) diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt index 0ee9de99b3ae..a1a2cde7b7d8 100644 --- a/Documentation/devicetree/bindings/xilinx.txt +++ b/Documentation/devicetree/bindings/xilinx.txt @@ -1,93 +1,4 @@ - d) Xilinx IP cores - - The Xilinx EDK toolchain ships with a set of IP cores (devices) for use - in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range - of standard device types (network, serial, etc.) and miscellaneous - devices (gpio, LCD, spi, etc). Also, since these devices are - implemented within the fpga fabric every instance of the device can be - synthesised with different options that change the behaviour. - - Each IP-core has a set of parameters which the FPGA designer can use to - control how the core is synthesized. Historically, the EDK tool would - extract the device parameters relevant to device drivers and copy them - into an 'xparameters.h' in the form of #define symbols. This tells the - device drivers how the IP cores are configured, but it requires the kernel - to be recompiled every time the FPGA bitstream is resynthesized. - - The new approach is to export the parameters into the device tree and - generate a new device tree each time the FPGA bitstream changes. The - parameters which used to be exported as #defines will now become - properties of the device node. In general, device nodes for IP-cores - will take the following form: - - (name): (generic-name)@(base-address) { - compatible = "xlnx,(ip-core-name)-(HW_VER)" - [, (list of compatible devices), ...]; - reg = <(baseaddr) (size)>; - interrupt-parent = <&interrupt-controller-phandle>; - interrupts = < ... >; - xlnx,(parameter1) = "(string-value)"; - xlnx,(parameter2) = <(int-value)>; - }; - - (generic-name): an open firmware-style name that describes the - generic class of device. Preferably, this is one word, such - as 'serial' or 'ethernet'. - (ip-core-name): the name of the ip block (given after the BEGIN - directive in system.mhs). Should be in lowercase - and all underscores '_' converted to dashes '-'. - (name): is derived from the "PARAMETER INSTANCE" value. - (parameter#): C_* parameters from system.mhs. The C_ prefix is - dropped from the parameter name, the name is converted - to lowercase and all underscore '_' characters are - converted to dashes '-'. - (baseaddr): the baseaddr parameter value (often named C_BASEADDR). - (HW_VER): from the HW_VER parameter. - (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). - - Typically, the compatible list will include the exact IP core version - followed by an older IP core version which implements the same - interface or any other device with the same interface. - - 'reg' and 'interrupts' are all optional properties. - - For example, the following block from system.mhs: - - BEGIN opb_uartlite - PARAMETER INSTANCE = opb_uartlite_0 - PARAMETER HW_VER = 1.00.b - PARAMETER C_BAUDRATE = 115200 - PARAMETER C_DATA_BITS = 8 - PARAMETER C_ODD_PARITY = 0 - PARAMETER C_USE_PARITY = 0 - PARAMETER C_CLK_FREQ = 50000000 - PARAMETER C_BASEADDR = 0xEC100000 - PARAMETER C_HIGHADDR = 0xEC10FFFF - BUS_INTERFACE SOPB = opb_7 - PORT OPB_Clk = CLK_50MHz - PORT Interrupt = opb_uartlite_0_Interrupt - PORT RX = opb_uartlite_0_RX - PORT TX = opb_uartlite_0_TX - PORT OPB_Rst = sys_bus_reset_0 - END - - becomes the following device tree node: - - opb_uartlite_0: serial@ec100000 { - device_type = "serial"; - compatible = "xlnx,opb-uartlite-1.00.b"; - reg = ; - interrupt-parent = <&opb_intc_0>; - interrupts = <1 0>; // got this from the opb_intc parameters - current-speed = ; // standard serial device prop - clock-frequency = ; // standard serial device prop - xlnx,data-bits = <8>; - xlnx,odd-parity = <0>; - xlnx,use-parity = <0>; - }; - - That covers the general approach to binding xilinx IP cores into the - device tree. The following are bindings for specific devices: + Bindings for specific devices: i) Xilinx ML300 Framebuffer @@ -102,13 +13,6 @@ Default is . - rotate-display (empty) : rotate display 180 degrees. - iii) Xilinx EMAC and Xilinx TEMAC - - Xilinx Ethernet devices. In addition to general xilinx properties - listed above, nodes for these devices should include a phy-handle - property, and may include other common network device properties - like local-mac-address. - v) Xilinx hwicap Xilinx hwicap devices provide access to the configuration logic From 959393e81cf1fe7f2a75d639b90cd7c816103f25 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:22 +0200 Subject: [PATCH 5/9] dt-bindings: firmware: xilinx: Add missing example for ZynqMP Document clock-controller under zynqmp-firmware in the binding example so ZynqMP DTs validate against xlnx,versal-clk.yaml (Versal example already did). Acked-by: Conor Dooley Link: https://patch.msgid.link/12dba601a8b631e565dd98e52a89b0ec18fcdce2.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index d50438b0fca8..680082c29f01 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -132,6 +132,14 @@ examples: zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; + clock-controller { + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells = <1>; + }; soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; nvmem-layout { From 6e32cb10cf32e60cf40ad0baa37c54969f10101f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:23 +0200 Subject: [PATCH 6/9] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern The clock-names pattern "^mio_clk[00-77]+.*$" was intended to constrain the MIO index to the valid range 00..77 (ZynqMP has 78 MIO pins), but a regex character class cannot express a multi-digit decimal range. Replace the bogus character class with an explicit alternation that enumerates the two-digit decimal values 00..77. Fixes: 03d4a1004053 ("dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml") Acked-by: Conor Dooley Link: https://patch.msgid.link/e742b7da70c2bf10650a81e537f1b90d76799416.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index bef109d163a8..b1623c2ab0f6 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -116,7 +116,7 @@ allOf: - const: pss_alt_ref_clk - const: aux_ref_clk - const: gt_crx_ref_clk - - pattern: "^mio_clk[00-77]+.*$" + - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" - pattern: "gem[0-3]+_emio_clk.*$" - pattern: "swdt[0-1]+_ext_clk.*$" From d0d3f0f8aed45c93802e79e8a0dd959d538a49fa Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:24 +0200 Subject: [PATCH 7/9] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema The ZynqMP clock controller binding shares only #clock-cells with the Versal bindings. Move it to a dedicated xlnx,zynqmp-clk.yaml schema. Also remove "(Optional clock)" from clock description because it is visible from schema itself. Also update versal-firmware example to match changes in xlnx,zynqmp-firmware.yaml. Suggested-by: Rob Herring Acked-by: Conor Dooley Link: https://patch.msgid.link/973a8a5441cf13622594b95dd0dd20a5f42ccece.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../bindings/clock/xlnx,versal-clk.yaml | 54 ++------------- .../bindings/clock/xlnx,zynqmp-clk.yaml | 68 +++++++++++++++++++ .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +- 3 files changed, 78 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index b1623c2ab0f6..7b6d9ec83863 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -17,9 +17,7 @@ description: | properties: compatible: oneOf: - - enum: - - xlnx,versal-clk - - xlnx,zynqmp-clk + - const: xlnx,versal-clk - items: - enum: - xlnx,versal-net-clk @@ -32,11 +30,11 @@ properties: description: List of clock specifiers which are external input clocks to the given clock controller. minItems: 2 - maxItems: 8 + maxItems: 3 clock-names: minItems: 2 - maxItems: 8 + maxItems: 3 required: - compatible @@ -87,44 +85,11 @@ allOf: - const: pl_alt_ref - const: alt_ref - - if: - properties: - compatible: - contains: - enum: - - xlnx,zynqmp-clk - - then: - properties: - clocks: - minItems: 5 - items: - - description: PS reference clock - - description: reference clock for video system - - description: alternative PS reference clock - - description: auxiliary reference clock - - description: transceiver reference clock - - description: (E)MIO clock source (Optional clock) - - description: GEM emio clock (Optional clock) - - description: Watchdog external clock (Optional clock) - - clock-names: - minItems: 5 - items: - - const: pss_ref_clk - - const: video_clk - - const: pss_alt_ref_clk - - const: aux_ref_clk - - const: gt_crx_ref_clk - - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" - - pattern: "gem[0-3]+_emio_clk.*$" - - pattern: "swdt[0-1]+_ext_clk.*$" - examples: - | firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; + versal-firmware { + compatible = "xlnx,versal-firmware"; method = "smc"; versal_clk: clock-controller { #clock-cells = <1>; @@ -134,13 +99,4 @@ examples: }; }; }; - - clock-controller { - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, - <&aux_ref_clk>, <>_crx_ref_clk>; - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", - "aux_ref_clk", "gt_crx_ref_clk"; - }; ... diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml new file mode 100644 index 000000000000..c64550471581 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP clock controller + +maintainers: + - Michal Simek + +description: + The clock controller is a hardware block of Xilinx ZynqMP clock tree. It + reads required input clock frequencies from the devicetree and acts as clock + provider for all clock consumers of PS clocks. + +properties: + compatible: + const: xlnx,zynqmp-clk + + "#clock-cells": + const: 1 + + clocks: + description: List of clock specifiers which are external input + clocks to the given clock controller. + minItems: 5 + items: + - description: PS reference clock + - description: reference clock for video system + - description: alternative PS reference clock + - description: auxiliary reference clock + - description: transceiver reference clock + - description: (E)MIO clock source + - description: GEM emio clock + - description: Watchdog external clock + + clock-names: + minItems: 5 + items: + - const: pss_ref_clk + - const: video_clk + - const: pss_alt_ref_clk + - const: aux_ref_clk + - const: gt_crx_ref_clk + - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" + - pattern: "gem[0-3]+_emio_clk.*$" + - pattern: "swdt[0-1]+_ext_clk.*$" + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index 680082c29f01..72af37cdb103 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -48,8 +48,7 @@ properties: const: 1 clock-controller: - $ref: /schemas/clock/xlnx,versal-clk.yaml# - description: The clock controller is a hardware block of Xilinx versal + description: The clock controller is a hardware block of Xilinx SoC clock tree. It reads required input clock frequencies from the devicetree and acts as clock provider for all clock consumers of PS clocks.list of clock specifiers which are external input clocks to the given clock @@ -113,10 +112,14 @@ allOf: const: xlnx,zynqmp-firmware then: properties: + clock-controller: + $ref: /schemas/clock/xlnx,zynqmp-clk.yaml# pinctrl: $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# else: properties: + clock-controller: + $ref: /schemas/clock/xlnx,versal-clk.yaml# pinctrl: $ref: /schemas/pinctrl/xlnx,versal-pinctrl.yaml# From 7dc3776a5f98463e6c332d3a62d5021ffa3a4004 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:25 +0200 Subject: [PATCH 8/9] dt-bindings: clock: versal-clk: Fix Versal NET clock validation The Versal NET clock controller compatible is specified as: compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; with xlnx,versal-clk listed as fallback. The original binding had two separate if/then blocks - one matching xlnx,versal-clk (2 clocks) and another matching xlnx,versal-net-clk (3 clocks). Since both compatible strings are present, both conditions matched simultaneously and JSON Schema applied the more restrictive 2-clock constraint, causing false "too long" validation errors for Versal NET. Define clock-names at the top-level and use if/then only to constrain the clock count (2 for Versal, 3 for Versal NET). Add a dedicated example for the Versal NET 3-clock configuration. Fixes: 39118392d19a ("dt-bindings: Remove alt_ref from versal") Acked-by: Conor Dooley Link: https://patch.msgid.link/202e448e57cf979e1b5be61da0bad7778defdd4e.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../bindings/clock/xlnx,versal-clk.yaml | 55 ++++++++----------- 1 file changed, 24 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 7b6d9ec83863..1f36ccc4cde1 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -30,11 +30,17 @@ properties: description: List of clock specifiers which are external input clocks to the given clock controller. minItems: 2 - maxItems: 3 + items: + - description: reference clock + - description: alternate reference clock for programmable logic + - description: alternate reference clock clock-names: minItems: 2 - maxItems: 3 + items: + - const: ref + - const: pl_alt_ref + - const: alt_ref required: - compatible @@ -45,45 +51,24 @@ required: additionalProperties: false allOf: - - if: - properties: - compatible: - contains: - enum: - - xlnx,versal-clk - - then: - properties: - clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - clock-names: - items: - - const: ref - - const: pl_alt_ref - - if: properties: compatible: contains: enum: - xlnx,versal-net-clk - then: properties: clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - description: alternate reference clock - + minItems: 3 clock-names: - items: - - const: ref - - const: pl_alt_ref - - const: alt_ref + minItems: 3 + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 examples: - | @@ -99,4 +84,12 @@ examples: }; }; }; + + - | + clock-controller { + compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; + clocks = <&ref>, <&pl_alt_ref>, <&alt_ref>; + clock-names = "ref", "pl_alt_ref", "alt_ref"; + #clock-cells = <1>; + }; ... From e1ab33a3b2892f56102ce90b20d2445847e758a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:26 +0200 Subject: [PATCH 9/9] arm64: versal-net: Switch Versal NET to firmware clock interface Switch Versal NET from using fixed clocks to the firmware-based clock interface (versal-net-clk.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions. Add DT macro headers for Versal NET and base Versal clocks, power domains and mandatory resets required by the clock dtsi. Link: https://patch.msgid.link/77e6234f6cef3f78fb1c6c97142fa8055982e14e.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../arm64/boot/dts/xilinx/versal-net-clk.dtsi | 351 +++++++++++++----- arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h | 123 ++++++ .../boot/dts/xilinx/xlnx-versal-net-clk.h | 74 ++++ .../boot/dts/xilinx/xlnx-versal-net-power.h | 38 ++ .../boot/dts/xilinx/xlnx-versal-net-resets.h | 53 +++ .../arm64/boot/dts/xilinx/xlnx-versal-power.h | 55 +++ .../boot/dts/xilinx/xlnx-versal-resets.h | 106 ++++++ 7 files changed, 698 insertions(+), 102 deletions(-) create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h diff --git a/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi index b7a8a1a512cb..d3a27da90090 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi @@ -1,72 +1,52 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx Versal NET fixed clock + * dts file for Xilinx Versal NET with PM * - * (C) Copyright 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ +#include +#include +#include "xlnx-versal-net-clk.h" +#include "xlnx-versal-net-power.h" +#include "xlnx-versal-net-resets.h" + / { - clk60: clk60 { + ref_clk: clock-33333333 { compatible = "fixed-clock"; + bootph-all; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; #clock-cells = <0>; - clock-frequency = <60000000>; }; - clk100: clk100 { + rtc_clk: clock-32768 { compatible = "fixed-clock"; + bootph-all; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; #clock-cells = <0>; - clock-frequency = <100000000>; }; - clk125: clk125 { - compatible = "fixed-clock"; + can0_clk: can0-clk { + compatible = "fixed-factor-clock"; + clocks = <&versal_net_clk CAN0_REF_2X>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "can0_clk"; #clock-cells = <0>; - clock-frequency = <125000000>; }; - clk150: clk150 { - compatible = "fixed-clock"; + can1_clk: can1-clk { + compatible = "fixed-factor-clock"; + clocks = <&versal_net_clk CAN1_REF_2X>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "can1_clk"; #clock-cells = <0>; - clock-frequency = <150000000>; - }; - - clk160: clk160 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <160000000>; - }; - - clk200: clk200 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - clk250: clk250 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - - clk300: clk300 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000000>; - }; - - clk450: clk450 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <450000000>; - }; - - clk1200: clk1200 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1200000000>; }; firmware { @@ -74,158 +54,325 @@ versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; bootph-all; method = "smc"; + #power-domain-cells = <1>; + + versal_net_reset: reset-controller { + compatible = "xlnx,versal-net-reset"; + #reset-cells = <1>; + }; + + versal_net_clk: clock-controller { + compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; + bootph-all; + clocks = <&ref_clk>, <&ref_clk>, <&ref_clk>; + clock-names = "ref", "pl_alt_ref", "alt_ref"; + #clock-cells = <1>; + }; + + versal_net_power: power-management { + compatible = "xlnx,zynqmp-power"; + mboxes = <&ipi_mailbox_pmu1 0>, + <&ipi_mailbox_pmu1 1>; + mbox-names = "tx", "rx"; + }; + }; + }; + + zynqmp-ipi { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = ; + xlnx,ipi-id = <2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipi_mailbox_pmu1: mailbox@eb3f0440 { + compatible = "xlnx,zynqmp-ipi-dest-mailbox"; + reg = <0 0xeb3f0440 0 0x20>, + <0 0xeb3f0460 0 0x20>, + <0 0xeb3f0280 0 0x20>, + <0 0xeb3f02a0 0 0x20>; + reg-names = "local_request_region", "local_response_region", + "remote_request_region", "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <1>; }; }; }; -&adma0 { - clocks = <&clk450>, <&clk450>; +&cpu0 { + clocks = <&versal_net_clk ACPU_0>; }; -&adma1 { - clocks = <&clk450>, <&clk450>; +&cpu100 { + clocks = <&versal_net_clk ACPU_0>; }; -&adma2 { - clocks = <&clk450>, <&clk450>; +&cpu200 { + clocks = <&versal_net_clk ACPU_0>; }; -&adma3 { - clocks = <&clk450>, <&clk450>; +&cpu300 { + clocks = <&versal_net_clk ACPU_0>; }; -&adma4 { - clocks = <&clk450>, <&clk450>; +&cpu10000 { + clocks = <&versal_net_clk ACPU_1>; }; -&adma5 { - clocks = <&clk450>, <&clk450>; +&cpu10100 { + clocks = <&versal_net_clk ACPU_1>; }; -&adma6 { - clocks = <&clk450>, <&clk450>; +&cpu10200 { + clocks = <&versal_net_clk ACPU_1>; }; -&adma7 { - clocks = <&clk450>, <&clk450>; +&cpu10300 { + clocks = <&versal_net_clk ACPU_1>; +}; + +&cpu20000 { + clocks = <&versal_net_clk ACPU_2>; +}; + +&cpu20100 { + clocks = <&versal_net_clk ACPU_2>; +}; + +&cpu20200 { + clocks = <&versal_net_clk ACPU_2>; +}; + +&cpu20300 { + clocks = <&versal_net_clk ACPU_2>; +}; + +&cpu30000 { + clocks = <&versal_net_clk ACPU_3>; +}; + +&cpu30100 { + clocks = <&versal_net_clk ACPU_3>; +}; + +&cpu30200 { + clocks = <&versal_net_clk ACPU_3>; +}; + +&cpu30300 { + clocks = <&versal_net_clk ACPU_3>; }; &can0 { - clocks = <&clk160>, <&clk160>; + clocks = <&can0_clk>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; &can1 { - clocks = <&clk160>, <&clk160>; + clocks = <&can1_clk>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; &gem0 { - clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; + clocks = <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, + <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; + power-domains = <&versal_net_firmware PM_DEV_GEM_0>; }; &gem1 { - clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; + clocks = <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, + <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; + power-domains = <&versal_net_firmware PM_DEV_GEM_1>; }; &gpio0 { - clocks = <&clk100>; + clocks = <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; &gpio1 { - clocks = <&clk100>; + clocks = <&versal_net_clk PMC_LSBUS_REF>; + power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { - clocks = <&clk100>; + clocks = <&versal_net_clk I3C0_REF>; + power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i2c1 { - clocks = <&clk100>; + clocks = <&versal_net_clk I3C1_REF>; + power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &i3c0 { - clocks = <&clk100>; + clocks = <&versal_net_clk I3C0_REF>; + power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i3c1 { - clocks = <&clk100>; + clocks = <&versal_net_clk I3C1_REF>; + power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; -&ospi { - clocks = <&clk200>; +&adma0 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; +}; + +&adma1 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; +}; + +&adma2 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; +}; + +&adma3 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; +}; + +&adma4 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; +}; + +&adma5 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; +}; + +&adma6 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; +}; + +&adma7 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; &qspi { - clocks = <&clk300>, <&clk300>; + clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_QSPI>; +}; + +&ospi { + clocks = <&versal_net_clk OSPI_REF>; + power-domains = <&versal_net_firmware PM_DEV_OSPI>; }; &rtc { - /* Nothing */ -}; - -&sdhci0 { - clocks = <&clk200>, <&clk200>, <&clk1200>; -}; - -&sdhci1 { - clocks = <&clk200>, <&clk200>, <&clk1200>; + clocks = <&rtc_clk>; + clock-names = "rtc"; + power-domains = <&versal_net_firmware PM_DEV_RTC>; }; &serial0 { - clocks = <&clk100>, <&clk100>; + clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_UART_0>; }; &serial1 { - clocks = <&clk100>, <&clk100>; + clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_UART_1>; +}; + +&sdhci0 { + clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk SD_DLL_REF>; + power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; +}; + +&sdhci1 { + clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk SD_DLL_REF>; + power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; &spi0 { - clocks = <&clk200>, <&clk200>; + clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_SPI_0>; }; &spi1 { - clocks = <&clk200>, <&clk200>; + clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_SPI_1>; }; &ttc0 { - clocks = <&clk150>; + clocks = <&versal_net_clk TTC0>; + power-domains = <&versal_net_firmware PM_DEV_TTC_0>; +}; + +&ttc1 { + clocks = <&versal_net_clk TTC1>; + power-domains = <&versal_net_firmware PM_DEV_TTC_1>; +}; + +&ttc2 { + clocks = <&versal_net_clk TTC2>; + power-domains = <&versal_net_firmware PM_DEV_TTC_2>; +}; + +&ttc3 { + clocks = <&versal_net_clk TTC3>; + power-domains = <&versal_net_firmware PM_DEV_TTC_3>; }; &usb0 { - clocks = <&clk60>, <&clk60>; + clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; + power-domains = <&versal_net_firmware PM_DEV_USB_0>; + resets = <&versal_net_reset VERSAL_RST_USB_0>; }; &dwc3_0 { - clocks = <&clk60>; + clocks = <&versal_net_clk USB0_BUS_REF>; }; &usb1 { - clocks = <&clk60>, <&clk60>; + clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; + power-domains = <&versal_net_firmware PM_DEV_USB_1>; + resets = <&versal_net_reset VERSAL_RST_USB_1>; }; &dwc3_1 { - clocks = <&clk60>; + clocks = <&versal_net_clk USB1_BUS_REF>; }; &wwdt0 { - clocks = <&clk150>; + clocks = <&versal_net_clk FPD_WWDT0>; + power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; &wwdt1 { - clocks = <&clk150>; + clocks = <&versal_net_clk FPD_WWDT1>; + power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; &wwdt2 { - clocks = <&clk150>; + clocks = <&versal_net_clk FPD_WWDT2>; + power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; &wwdt3 { - clocks = <&clk150>; + clocks = <&versal_net_clk FPD_WWDT3>; + power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; &lpd_wwdt0 { - clocks = <&clk150>; + clocks = <&versal_net_clk LPD_WWDT0>; + power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>; }; &lpd_wwdt1 { - clocks = <&clk150>; + clocks = <&versal_net_clk LPD_WWDT1>; + power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>; }; diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h new file mode 100644 index 000000000000..d0c4abf78f30 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_CLK_H +#define _XLNX_VERSAL_CLK_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h new file mode 100644 index 000000000000..4a6add03c173 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_CLK_H +#define _XLNX_VERSAL_NET_CLK_H + +#include "xlnx-versal-clk.h" + +#define CAN0_REF_2X 0x9e +#define CAN1_REF_2X 0xac +#define FPD_WWDT0 0xb5 +#define FPD_WWDT1 0xb6 +#define FPD_WWDT2 0xb7 +#define FPD_WWDT3 0xb8 +#define LPD_WWDT0 0xb9 +#define LPD_WWDT1 0xba +#define ACPU_0 0x98 +#define ACPU_1 0x9b +#define ACPU_2 0x9a +#define ACPU_3 0x99 +#define I3C0_REF 0x9d +#define I3C1_REF 0x9f +#define USB1_BUS_REF 0xae +#define LPD_WWDT 0xad + +/* Remove Versal specific node IDs */ +#undef APU_PLL +#undef RPU_PLL +#undef CPM_PLL +#undef APU_PRESRC +#undef APU_POSTCLK +#undef APU_PLL_OUT +#undef APLL +#undef RPU_PRESRC +#undef RPU_POSTCLK +#undef RPU_PLL_OUT +#undef RPLL +#undef CPM_PRESRC +#undef CPM_POSTCLK +#undef CPM_PLL_OUT +#undef CPLL +#undef APLL_TO_XPD +#undef RPLL_TO_XPD +#undef RCLK_PMC +#undef RCLK_LPD +#undef WDT +#undef MUXED_IRO_DIV2 +#undef MUXED_IRO_DIV4 +#undef PSM_REF +#undef CPM_CORE_REF +#undef CPM_LSBUS_REF +#undef CPM_DBG_REF +#undef CPM_AUX0_REF +#undef CPM_AUX1_REF +#undef CPU_R5 +#undef CPU_R5_CORE +#undef CPU_R5_OCM +#undef CPU_R5_OCM2 +#undef CAN0_REF +#undef CAN1_REF +#undef I2C0_REF +#undef I2C1_REF +#undef CPM_TOPSW_REF +#undef USB3_DUAL_REF +#undef MUXED_IRO +#undef PL_EXT +#undef PL_LB +#undef MIO_50_OR_51 +#undef MIO_24_OR_25 + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h new file mode 100644 index 000000000000..4f73593c966b --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_POWER_H +#define _XLNX_VERSAL_NET_POWER_H + +#include "xlnx-versal-power.h" + +#define PM_DEV_USB_1 (0x182240d7U) +#define PM_DEV_FPD_SWDT_0 (0x182240dbU) +#define PM_DEV_FPD_SWDT_1 (0x182240dcU) +#define PM_DEV_FPD_SWDT_2 (0x182240ddU) +#define PM_DEV_FPD_SWDT_3 (0x182240deU) +#define PM_DEV_TCM_A_0A (0x183180cbU) +#define PM_DEV_TCM_A_0B (0x183180ccU) +#define PM_DEV_TCM_A_0C (0x183180cdU) +#define PM_DEV_RPU_A_0 (0x181100bfU) +#define PM_DEV_LPD_SWDT_0 (0x182240d9U) +#define PM_DEV_LPD_SWDT_1 (0x182240daU) + +/* Remove Versal specific node IDs */ +#undef PM_DEV_RPU0_0 +#undef PM_DEV_RPU0_1 +#undef PM_DEV_OCM_0 +#undef PM_DEV_OCM_1 +#undef PM_DEV_OCM_2 +#undef PM_DEV_OCM_3 +#undef PM_DEV_TCM_0_A +#undef PM_DEV_TCM_1_A +#undef PM_DEV_TCM_0_B +#undef PM_DEV_TCM_1_B +#undef PM_DEV_SWDT_FPD +#undef PM_DEV_AI + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h new file mode 100644 index 000000000000..edc5841df214 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_RESETS_H +#define _XLNX_VERSAL_NET_RESETS_H + +#include "xlnx-versal-resets.h" + +#define VERSAL_RST_USB_1 (0xc1040c6U) + +/* Remove Versal specific reset IDs */ +#undef VERSAL_RST_ACPU_0_POR +#undef VERSAL_RST_ACPU_1_POR +#undef VERSAL_RST_OCM2_POR +#undef VERSAL_RST_APU +#undef VERSAL_RST_ACPU_0 +#undef VERSAL_RST_ACPU_1 +#undef VERSAL_RST_ACPU_L2 +#undef VERSAL_RST_RPU_ISLAND +#undef VERSAL_RST_RPU_AMBA +#undef VERSAL_RST_R5_0 +#undef VERSAL_RST_R5_1 +#undef VERSAL_RST_OCM2_RST +#undef VERSAL_RST_I2C_PMC +#undef VERSAL_RST_I2C_0 +#undef VERSAL_RST_I2C_1 +#undef VERSAL_RST_SWDT_FPD +#undef VERSAL_RST_SWDT_LPD +#undef VERSAL_RST_USB +#undef VERSAL_RST_DPC +#undef VERSAL_RST_DBG_TRACE +#undef VERSAL_RST_DBG_TSTMP +#undef VERSAL_RST_RPU0_DBG +#undef VERSAL_RST_RPU1_DBG +#undef VERSAL_RST_HSDP +#undef VERSAL_RST_CPMDBG +#undef VERSAL_RST_PCIE_CFG +#undef VERSAL_RST_PCIE_CORE0 +#undef VERSAL_RST_PCIE_CORE1 +#undef VERSAL_RST_PCIE_DMA +#undef VERSAL_RST_L2_0 +#undef VERSAL_RST_L2_1 +#undef VERSAL_RST_ADDR_REMAP +#undef VERSAL_RST_CPI0 +#undef VERSAL_RST_CPI1 +#undef VERSAL_RST_XRAM +#undef VERSAL_RST_AIE_ARRAY +#undef VERSAL_RST_AIE_SHIM + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h new file mode 100644 index 000000000000..c3450675658a --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_POWER_H +#define _XLNX_VERSAL_POWER_H + +#define PM_DEV_RPU0_0 (0x18110005U) +#define PM_DEV_RPU0_1 (0x18110006U) +#define PM_DEV_OCM_0 (0x18314007U) +#define PM_DEV_OCM_1 (0x18314008U) +#define PM_DEV_OCM_2 (0x18314009U) +#define PM_DEV_OCM_3 (0x1831400aU) +#define PM_DEV_TCM_0_A (0x1831800bU) +#define PM_DEV_TCM_0_B (0x1831800cU) +#define PM_DEV_TCM_1_A (0x1831800dU) +#define PM_DEV_TCM_1_B (0x1831800eU) +#define PM_DEV_USB_0 (0x18224018U) +#define PM_DEV_GEM_0 (0x18224019U) +#define PM_DEV_GEM_1 (0x1822401aU) +#define PM_DEV_SPI_0 (0x1822401bU) +#define PM_DEV_SPI_1 (0x1822401cU) +#define PM_DEV_I2C_0 (0x1822401dU) +#define PM_DEV_I2C_1 (0x1822401eU) +#define PM_DEV_CAN_FD_0 (0x1822401fU) +#define PM_DEV_CAN_FD_1 (0x18224020U) +#define PM_DEV_UART_0 (0x18224021U) +#define PM_DEV_UART_1 (0x18224022U) +#define PM_DEV_GPIO (0x18224023U) +#define PM_DEV_TTC_0 (0x18224024U) +#define PM_DEV_TTC_1 (0x18224025U) +#define PM_DEV_TTC_2 (0x18224026U) +#define PM_DEV_TTC_3 (0x18224027U) +#define PM_DEV_SWDT_LPD (0x18224028U) +#define PM_DEV_SWDT_FPD (0x18224029U) +#define PM_DEV_OSPI (0x1822402aU) +#define PM_DEV_QSPI (0x1822402bU) +#define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_I2C_PMC (0x1822402dU) +#define PM_DEV_SDIO_0 (0x1822402eU) +#define PM_DEV_SDIO_1 (0x1822402fU) +#define PM_DEV_RTC (0x18224034U) +#define PM_DEV_ADMA_0 (0x18224035U) +#define PM_DEV_ADMA_1 (0x18224036U) +#define PM_DEV_ADMA_2 (0x18224037U) +#define PM_DEV_ADMA_3 (0x18224038U) +#define PM_DEV_ADMA_4 (0x18224039U) +#define PM_DEV_ADMA_5 (0x1822403aU) +#define PM_DEV_ADMA_6 (0x1822403bU) +#define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_AI (0x18224072U) + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h new file mode 100644 index 000000000000..fe00f4a0ba65 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_RESETS_H +#define _XLNX_VERSAL_RESETS_H + +#define VERSAL_RST_PMC_POR (0xc30c001U) +#define VERSAL_RST_PMC (0xc410002U) +#define VERSAL_RST_PS_POR (0xc30c003U) +#define VERSAL_RST_PL_POR (0xc30c004U) +#define VERSAL_RST_NOC_POR (0xc30c005U) +#define VERSAL_RST_FPD_POR (0xc30c006U) +#define VERSAL_RST_ACPU_0_POR (0xc30c007U) +#define VERSAL_RST_ACPU_1_POR (0xc30c008U) +#define VERSAL_RST_OCM2_POR (0xc30c009U) +#define VERSAL_RST_PS_SRST (0xc41000aU) +#define VERSAL_RST_PL_SRST (0xc41000bU) +#define VERSAL_RST_NOC (0xc41000cU) +#define VERSAL_RST_NPI (0xc41000dU) +#define VERSAL_RST_SYS_RST_1 (0xc41000eU) +#define VERSAL_RST_SYS_RST_2 (0xc41000fU) +#define VERSAL_RST_SYS_RST_3 (0xc410010U) +#define VERSAL_RST_FPD (0xc410011U) +#define VERSAL_RST_PL0 (0xc410012U) +#define VERSAL_RST_PL1 (0xc410013U) +#define VERSAL_RST_PL2 (0xc410014U) +#define VERSAL_RST_PL3 (0xc410015U) +#define VERSAL_RST_APU (0xc410016U) +#define VERSAL_RST_ACPU_0 (0xc410017U) +#define VERSAL_RST_ACPU_1 (0xc410018U) +#define VERSAL_RST_ACPU_L2 (0xc410019U) +#define VERSAL_RST_ACPU_GIC (0xc41001aU) +#define VERSAL_RST_RPU_ISLAND (0xc41001bU) +#define VERSAL_RST_RPU_AMBA (0xc41001cU) +#define VERSAL_RST_R5_0 (0xc41001dU) +#define VERSAL_RST_R5_1 (0xc41001eU) +#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) +#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) +#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +#define VERSAL_RST_SYSMON_LPD (0xc410023U) +#define VERSAL_RST_PDMA_RST1 (0xc410024U) +#define VERSAL_RST_PDMA_RST0 (0xc410025U) +#define VERSAL_RST_ADMA (0xc410026U) +#define VERSAL_RST_TIMESTAMP (0xc410027U) +#define VERSAL_RST_OCM (0xc410028U) +#define VERSAL_RST_OCM2_RST (0xc410029U) +#define VERSAL_RST_IPI (0xc41002aU) +#define VERSAL_RST_SBI (0xc41002bU) +#define VERSAL_RST_LPD (0xc41002cU) +#define VERSAL_RST_QSPI (0xc10402dU) +#define VERSAL_RST_OSPI (0xc10402eU) +#define VERSAL_RST_SDIO_0 (0xc10402fU) +#define VERSAL_RST_SDIO_1 (0xc104030U) +#define VERSAL_RST_I2C_PMC (0xc104031U) +#define VERSAL_RST_GPIO_PMC (0xc104032U) +#define VERSAL_RST_GEM_0 (0xc104033U) +#define VERSAL_RST_GEM_1 (0xc104034U) +#define VERSAL_RST_SPARE (0xc104035U) +#define VERSAL_RST_USB_0 (0xc104036U) +#define VERSAL_RST_UART_0 (0xc104037U) +#define VERSAL_RST_UART_1 (0xc104038U) +#define VERSAL_RST_SPI_0 (0xc104039U) +#define VERSAL_RST_SPI_1 (0xc10403aU) +#define VERSAL_RST_CAN_FD_0 (0xc10403bU) +#define VERSAL_RST_CAN_FD_1 (0xc10403cU) +#define VERSAL_RST_I2C_0 (0xc10403dU) +#define VERSAL_RST_I2C_1 (0xc10403eU) +#define VERSAL_RST_GPIO_LPD (0xc10403fU) +#define VERSAL_RST_TTC_0 (0xc104040U) +#define VERSAL_RST_TTC_1 (0xc104041U) +#define VERSAL_RST_TTC_2 (0xc104042U) +#define VERSAL_RST_TTC_3 (0xc104043U) +#define VERSAL_RST_SWDT_FPD (0xc104044U) +#define VERSAL_RST_SWDT_LPD (0xc104045U) +#define VERSAL_RST_USB (0xc104046U) +#define VERSAL_RST_DPC (0xc208047U) +#define VERSAL_RST_PMCDBG (0xc208048U) +#define VERSAL_RST_DBG_TRACE (0xc208049U) +#define VERSAL_RST_DBG_FPD (0xc20804aU) +#define VERSAL_RST_DBG_TSTMP (0xc20804bU) +#define VERSAL_RST_RPU0_DBG (0xc20804cU) +#define VERSAL_RST_RPU1_DBG (0xc20804dU) +#define VERSAL_RST_HSDP (0xc20804eU) +#define VERSAL_RST_DBG_LPD (0xc20804fU) +#define VERSAL_RST_CPM_POR (0xc30c050U) +#define VERSAL_RST_CPM (0xc410051U) +#define VERSAL_RST_CPMDBG (0xc208052U) +#define VERSAL_RST_PCIE_CFG (0xc410053U) +#define VERSAL_RST_PCIE_CORE0 (0xc410054U) +#define VERSAL_RST_PCIE_CORE1 (0xc410055U) +#define VERSAL_RST_PCIE_DMA (0xc410056U) +#define VERSAL_RST_CMN (0xc410057U) +#define VERSAL_RST_L2_0 (0xc410058U) +#define VERSAL_RST_L2_1 (0xc410059U) +#define VERSAL_RST_ADDR_REMAP (0xc41005aU) +#define VERSAL_RST_CPI0 (0xc41005bU) +#define VERSAL_RST_CPI1 (0xc41005cU) +#define VERSAL_RST_XRAM (0xc30c05dU) +#define VERSAL_RST_AIE_ARRAY (0xc10405eU) +#define VERSAL_RST_AIE_SHIM (0xc10405fU) + +#endif