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scsi: ufs: ufs-qcom: Implement vops get_rx_fom()
On some platforms, host's M-PHY RX_FOM Attribute always reads 0, meaning SW cannot rely on Figure of Merit (FOM) to identify the optimal TX Equalization settings for device's TX Lanes. Implement the vops ufs_qcom_get_rx_fom() such that SW can utilize the UFS Eye Opening Monitor (EOM) to evaluate the TX Equalization settings for device's TX Lanes. Reviewed-by: Bean Huo <beanhuo@micron.com> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Can Guo <can.guo@oss.qualcomm.com> Reviewed-by: Peter Wang <peter.wang@mediatek.com> Link: https://patch.msgid.link/20260325152154.1604082-11-can.guo@oss.qualcomm.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Can Guo
Martin K. Petersen
parent
385b95893e
commit
26605db760
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@ -232,9 +232,8 @@ ufshcd_compose_tx_eq_setting(struct ufshcd_tx_eq_settings *settings,
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*
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* Returns 0 on success, negative error code otherwise
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*/
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static int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba,
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struct ufshcd_tx_eq_params *params,
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u32 gear)
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int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba,
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struct ufshcd_tx_eq_params *params, u32 gear)
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{
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struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
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u32 setting;
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@ -263,6 +262,7 @@ static int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba,
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return 0;
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}
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EXPORT_SYMBOL_GPL(ufshcd_apply_tx_eq_settings);
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/**
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* ufshcd_evaluate_tx_eqtr_fom - Evaluate TX EQTR FOM results
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@ -2505,6 +2505,317 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq)
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return min_t(u32, gear, hba->max_pwr_info.info.gear_rx);
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}
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static int ufs_qcom_host_eom_config(struct ufs_hba *hba, int lane,
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const struct ufs_eom_coord *eom_coord,
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u32 target_test_count)
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{
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enum ufs_eom_eye_mask eye_mask = eom_coord->eye_mask;
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int v_step = eom_coord->v_step;
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int t_step = eom_coord->t_step;
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u32 volt_step, timing_step;
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int ret;
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if (abs(v_step) > UFS_QCOM_EOM_VOLTAGE_STEPS_MAX) {
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dev_err(hba->dev, "Invalid EOM Voltage Step: %d\n", v_step);
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return -ERANGE;
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}
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if (abs(t_step) > UFS_QCOM_EOM_TIMING_STEPS_MAX) {
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dev_err(hba->dev, "Invalid EOM Timing Step: %d\n", t_step);
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return -ERANGE;
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}
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if (v_step < 0)
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volt_step = RX_EYEMON_NEGATIVE_STEP_BIT | (u32)(-v_step);
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else
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volt_step = (u32)v_step;
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if (t_step < 0)
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timing_step = RX_EYEMON_NEGATIVE_STEP_BIT | (u32)(-t_step);
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else
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timing_step = (u32)t_step;
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ENABLE,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)),
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BIT(eye_mask) | RX_EYEMON_EXTENDED_VRANGE_BIT);
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if (ret) {
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dev_err(hba->dev, "Failed to enable Host EOM on Lane %d: %d\n",
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lane, ret);
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return ret;
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}
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TIMING_STEPS,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)),
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timing_step);
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if (ret) {
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dev_err(hba->dev, "Failed to set Host EOM timing step on Lane %d: %d\n",
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lane, ret);
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return ret;
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}
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_VOLTAGE_STEPS,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)),
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volt_step);
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if (ret) {
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dev_err(hba->dev, "Failed to set Host EOM voltage step on Lane %d: %d\n",
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lane, ret);
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return ret;
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}
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TARGET_TEST_COUNT,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)),
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target_test_count);
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if (ret)
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dev_err(hba->dev, "Failed to set Host EOM target test count on Lane %d: %d\n",
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lane, ret);
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return ret;
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}
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static int ufs_qcom_host_eom_may_stop(struct ufs_hba *hba, int lane,
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u32 target_test_count, u32 *err_count)
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{
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u32 start, tested_count, error_count;
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int ret;
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_START,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)),
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&start);
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if (ret) {
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dev_err(hba->dev, "Failed to get Host EOM start status on Lane %d: %d\n",
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lane, ret);
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return ret;
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}
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if (start & 0x1)
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return -EAGAIN;
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TESTED_COUNT,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)),
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&tested_count);
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if (ret) {
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dev_err(hba->dev, "Failed to get Host EOM tested count on Lane %d: %d\n",
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lane, ret);
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return ret;
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}
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ERROR_COUNT,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)),
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&error_count);
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if (ret) {
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dev_err(hba->dev, "Failed to get Host EOM error count on Lane %d: %d\n",
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lane, ret);
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return ret;
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}
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/* EOM can stop */
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if ((tested_count >= target_test_count - 3) || error_count > 0) {
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*err_count = error_count;
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/* Disable EOM */
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ENABLE,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)),
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0x0);
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if (ret) {
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dev_err(hba->dev, "Failed to disable Host EOM on Lane %d: %d\n",
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lane, ret);
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return ret;
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}
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} else {
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return -EAGAIN;
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}
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return 0;
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}
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static int ufs_qcom_host_eom_scan(struct ufs_hba *hba, int num_lanes,
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const struct ufs_eom_coord *eom_coord,
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u32 target_test_count, u32 *err_count)
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{
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bool eom_stopped[PA_MAXDATALANES] = { 0 };
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int lane, ret;
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u32 setting;
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if (!err_count || !eom_coord)
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return -EINVAL;
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if (target_test_count < UFS_QCOM_EOM_TARGET_TEST_COUNT_MIN) {
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dev_err(hba->dev, "Target test count (%u) too small for Host EOM\n",
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target_test_count);
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return -ERANGE;
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}
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for (lane = 0; lane < num_lanes; lane++) {
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ret = ufs_qcom_host_eom_config(hba, lane, eom_coord,
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target_test_count);
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if (ret) {
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dev_err(hba->dev, "Failed to config Host RX EOM: %d\n", ret);
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return ret;
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}
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}
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/*
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* Trigger a PACP_PWR_req to kick start EOM, but not to really change
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* the Power Mode.
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*/
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ret = ufshcd_uic_change_pwr_mode(hba, FAST_MODE << 4 | FAST_MODE);
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if (ret) {
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dev_err(hba->dev, "Failed to change power mode to kick start Host EOM: %d\n",
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ret);
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return ret;
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}
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more_burst:
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/* Create burst on Host RX Lane. */
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ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &setting);
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for (lane = 0; lane < num_lanes; lane++) {
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if (eom_stopped[lane])
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continue;
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ret = ufs_qcom_host_eom_may_stop(hba, lane, target_test_count,
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&err_count[lane]);
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if (!ret) {
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eom_stopped[lane] = true;
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} else if (ret == -EAGAIN) {
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/* Need more burst to excercise EOM */
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goto more_burst;
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} else {
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dev_err(hba->dev, "Failed to stop Host EOM: %d\n", ret);
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return ret;
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}
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dev_dbg(hba->dev, "Host RX Lane %d EOM, v_step %d, t_step %d, error count %u\n",
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lane, eom_coord->v_step, eom_coord->t_step,
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err_count[lane]);
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}
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return 0;
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}
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static int ufs_qcom_host_sw_rx_fom(struct ufs_hba *hba, int num_lanes, u32 *fom)
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{
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const struct ufs_eom_coord *eom_coord = sw_rx_fom_eom_coords_g6;
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u32 eom_err_count[PA_MAXDATALANES] = { 0 };
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u32 curr_ahit;
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int lane, i, ret;
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if (!fom)
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return -EINVAL;
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/* Stop the auto hibernate idle timer */
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curr_ahit = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
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if (curr_ahit)
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ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), PA_NO_ADAPT);
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if (ret) {
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dev_err(hba->dev, "Failed to select NO_ADAPT before starting Host EOM: %d\n", ret);
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goto out;
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}
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for (i = 0; i < SW_RX_FOM_EOM_COORDS; i++, eom_coord++) {
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ret = ufs_qcom_host_eom_scan(hba, num_lanes, eom_coord,
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UFS_QCOM_EOM_TARGET_TEST_COUNT_G6,
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eom_err_count);
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if (ret) {
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dev_err(hba->dev, "Failed to run Host EOM scan: %d\n", ret);
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break;
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}
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for (lane = 0; lane < num_lanes; lane++) {
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/* Bad coordinates have no weights */
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if (eom_err_count[lane])
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continue;
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fom[lane] += SW_RX_FOM_EOM_COORDS_WEIGHT;
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}
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}
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out:
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/* Restore the auto hibernate idle timer */
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if (curr_ahit)
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ufshcd_writel(hba, curr_ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
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return ret;
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}
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static int ufs_qcom_get_rx_fom(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *pwr_mode,
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struct tx_eqtr_iter *h_iter,
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struct tx_eqtr_iter *d_iter)
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{
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struct ufshcd_tx_eq_params *params __free(kfree) =
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kzalloc(sizeof(*params), GFP_KERNEL);
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struct ufs_qcom_host *host = ufshcd_get_variant(hba);
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struct ufs_pa_layer_attr old_pwr_info;
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u32 fom[PA_MAXDATALANES] = { 0 };
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u32 gear = pwr_mode->gear_tx;
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u32 rate = pwr_mode->hs_rate;
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int lane, ret;
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if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1 ||
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gear <= UFS_HS_G5 || !d_iter || !d_iter->is_updated)
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return 0;
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if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX)
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return -ERANGE;
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if (!params)
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return -ENOMEM;
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memcpy(&old_pwr_info, &hba->pwr_info, sizeof(struct ufs_pa_layer_attr));
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memcpy(params, &hba->tx_eq_params[gear - 1], sizeof(struct ufshcd_tx_eq_params));
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for (lane = 0; lane < pwr_mode->lane_rx; lane++) {
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params->device[lane].preshoot = d_iter->preshoot;
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params->device[lane].deemphasis = d_iter->deemphasis;
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}
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/* Use TX EQTR settings as Device's TX Equalization settings. */
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ret = ufshcd_apply_tx_eq_settings(hba, params, gear);
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if (ret) {
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dev_err(hba->dev, "%s: Failed to apply TX EQ settings for HS-G%u: %d\n",
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__func__, gear, ret);
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return ret;
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}
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/* Force PMC to target HS Gear to use new TX Equalization settings. */
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ret = ufshcd_change_power_mode(hba, pwr_mode, UFSHCD_PMC_POLICY_FORCE);
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if (ret) {
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dev_err(hba->dev, "%s: Failed to change power mode to HS-G%u, Rate-%s: %d\n",
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__func__, gear, ufs_hs_rate_to_str(rate), ret);
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return ret;
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}
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ret = ufs_qcom_host_sw_rx_fom(hba, pwr_mode->lane_rx, fom);
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if (ret) {
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dev_err(hba->dev, "Failed to get SW FOM of TX (PreShoot: %u, DeEmphasis: %u): %d\n",
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d_iter->preshoot, d_iter->deemphasis, ret);
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return ret;
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}
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/* Restore Device's TX Equalization settings. */
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ret = ufshcd_apply_tx_eq_settings(hba, &hba->tx_eq_params[gear - 1], gear);
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if (ret) {
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dev_err(hba->dev, "%s: Failed to apply TX EQ settings for HS-G%u: %d\n",
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__func__, gear, ret);
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return ret;
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}
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/* Restore Power Mode. */
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ret = ufshcd_change_power_mode(hba, &old_pwr_info, UFSHCD_PMC_POLICY_FORCE);
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if (ret) {
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dev_err(hba->dev, "%s: Failed to retore power mode to HS-G%u: %d\n",
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__func__, old_pwr_info.gear_tx, ret);
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return ret;
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}
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for (lane = 0; lane < pwr_mode->lane_rx; lane++)
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d_iter->fom[lane] = fom[lane];
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return 0;
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}
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static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status,
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struct ufs_pa_layer_attr *pwr_mode)
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@ -2575,6 +2886,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
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.get_outstanding_cqs = ufs_qcom_get_outstanding_cqs,
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.config_esi = ufs_qcom_config_esi,
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.freq_to_gear_speed = ufs_qcom_freq_to_gear_speed,
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.get_rx_fom = ufs_qcom_get_rx_fom,
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.tx_eqtr_notify = ufs_qcom_tx_eqtr_notify,
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};
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@ -33,6 +33,46 @@
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#define DL_VS_CLK_CFG_MASK GENMASK(9, 0)
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#define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9)
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#define UFS_QCOM_EOM_VOLTAGE_STEPS_MAX 127
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#define UFS_QCOM_EOM_TIMING_STEPS_MAX 63
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#define UFS_QCOM_EOM_TARGET_TEST_COUNT_MIN 8
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#define UFS_QCOM_EOM_TARGET_TEST_COUNT_G6 0x3F
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#define SW_RX_FOM_EOM_COORDS 23
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#define SW_RX_FOM_EOM_COORDS_WEIGHT (127 / SW_RX_FOM_EOM_COORDS)
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struct ufs_eom_coord {
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int t_step;
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int v_step;
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u8 eye_mask;
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};
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static const struct ufs_eom_coord sw_rx_fom_eom_coords_g6[SW_RX_FOM_EOM_COORDS] = {
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[0] = { -2, -15, UFS_EOM_EYE_MASK_M },
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[1] = { 0, -15, UFS_EOM_EYE_MASK_M },
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[2] = { 2, -15, UFS_EOM_EYE_MASK_M },
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[3] = { -4, -10, UFS_EOM_EYE_MASK_M },
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[4] = { -2, -10, UFS_EOM_EYE_MASK_M },
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[5] = { 0, -10, UFS_EOM_EYE_MASK_M },
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[6] = { 2, -10, UFS_EOM_EYE_MASK_M },
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[7] = { 4, -10, UFS_EOM_EYE_MASK_M },
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[8] = { -6, 0, UFS_EOM_EYE_MASK_M },
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[9] = { -4, 0, UFS_EOM_EYE_MASK_M },
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[10] = { -2, 0, UFS_EOM_EYE_MASK_M },
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[11] = { 0, 0, UFS_EOM_EYE_MASK_M },
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[12] = { 2, 0, UFS_EOM_EYE_MASK_M },
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[13] = { 4, 0, UFS_EOM_EYE_MASK_M },
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[14] = { 6, 0, UFS_EOM_EYE_MASK_M },
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[15] = { -4, 10, UFS_EOM_EYE_MASK_M },
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[16] = { -2, 10, UFS_EOM_EYE_MASK_M },
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[17] = { 0, 10, UFS_EOM_EYE_MASK_M },
|
||||
[18] = { 2, 10, UFS_EOM_EYE_MASK_M },
|
||||
[19] = { 4, 10, UFS_EOM_EYE_MASK_M },
|
||||
[20] = { -2, 15, UFS_EOM_EYE_MASK_M },
|
||||
[21] = { 0, 15, UFS_EOM_EYE_MASK_M },
|
||||
[22] = { 2, 15, UFS_EOM_EYE_MASK_M },
|
||||
};
|
||||
|
||||
/* Qualcomm MCQ Configuration */
|
||||
#define UFS_QCOM_MCQCAP_QCFGPTR 224 /* 0xE0 in hex */
|
||||
#define UFS_QCOM_MCQ_CONFIG_OFFSET (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) /* 0x1C000 */
|
||||
|
|
|
|||
|
|
@ -1515,6 +1515,9 @@ extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
|
|||
struct ufs_pa_layer_attr *desired_pwr_mode,
|
||||
enum ufshcd_pmc_policy pmc_policy);
|
||||
extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
|
||||
extern int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba,
|
||||
struct ufshcd_tx_eq_params *params,
|
||||
u32 gear);
|
||||
|
||||
/* UIC command interfaces for DME primitives */
|
||||
#define DME_LOCAL 0
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@
|
|||
#define TX_LCC_SEQUENCER 0x0032
|
||||
#define TX_MIN_ACTIVATETIME 0x0033
|
||||
#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
|
||||
#define TX_HS_DEEMPHASIS_SETTING 0x0037
|
||||
#define TX_HS_PRESHOOT_SETTING 0x003B
|
||||
#define TX_REFCLKFREQ 0x00EB
|
||||
#define TX_CFGCLKFREQVAL 0x00EC
|
||||
#define CFGEXTRATTR 0x00F0
|
||||
|
|
@ -76,10 +78,27 @@
|
|||
#define RX_REFCLKFREQ 0x00EB
|
||||
#define RX_CFGCLKFREQVAL 0x00EC
|
||||
#define CFGWIDEINLN 0x00F0
|
||||
#define RX_EYEMON_CAP 0x00F1
|
||||
#define RX_EYEMON_TIMING_MAX_STEPS_CAP 0x00F2
|
||||
#define RX_EYEMON_TIMING_MAX_OFFSET_CAP 0x00F3
|
||||
#define RX_EYEMON_VOLTAGE_MAX_STEPS_CAP 0x00F4
|
||||
#define RX_EYEMON_VOLTAGE_MAX_OFFSET_CAP 0x00F5
|
||||
#define RX_EYEMON_ENABLE 0x00F6
|
||||
#define RX_EYEMON_TIMING_STEPS 0x00F7
|
||||
#define RX_EYEMON_VOLTAGE_STEPS 0x00F8
|
||||
#define RX_EYEMON_TARGET_TEST_COUNT 0x00F9
|
||||
#define RX_EYEMON_TESTED_COUNT 0x00FA
|
||||
#define RX_EYEMON_ERROR_COUNT 0x00FB
|
||||
#define RX_EYEMON_START 0x00FC
|
||||
#define RX_EYEMON_EXTENDED_ERROR_COUNT 0x00FD
|
||||
|
||||
#define ENARXDIRECTCFG4 0x00F2
|
||||
#define ENARXDIRECTCFG3 0x00F3
|
||||
#define ENARXDIRECTCFG2 0x00F4
|
||||
|
||||
#define RX_EYEMON_NEGATIVE_STEP_BIT BIT(6)
|
||||
#define RX_EYEMON_EXTENDED_VRANGE_BIT BIT(6)
|
||||
|
||||
#define is_mphy_tx_attr(attr) (attr < RX_MODE)
|
||||
#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
|
||||
#define SYNC_LEN_FINE(x) ((x) & 0x3F)
|
||||
|
|
@ -297,6 +316,12 @@ enum ufs_tx_hs_deemphasis {
|
|||
UFS_TX_HS_DEEMPHASIS_DB_7P6,
|
||||
};
|
||||
|
||||
enum ufs_eom_eye_mask {
|
||||
UFS_EOM_EYE_MASK_M,
|
||||
UFS_EOM_EYE_MASK_L,
|
||||
UFS_EOM_EYE_MASK_U,
|
||||
};
|
||||
|
||||
#define DL_FC0ProtectionTimeOutVal_Default 8191
|
||||
#define DL_TC0ReplayTimeOutVal_Default 65535
|
||||
#define DL_AFC0ReqTimeOutVal_Default 32767
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user