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riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers

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SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
so the kernel uses coherent DMA mappings instead of non-coherent bounce
buffering.

Cc: stable@vger.kernel.org
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Link: https://patch.msgid.link/20260331171248.973014-3-gaohan@iscas.ac.cn
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This commit is contained in:
Han Gao 2026-04-01 01:12:48 +08:00 committed by Inochi Amaoto
parent 972e8823d9
commit 2647eabde8
1 changed files with 4 additions and 0 deletions
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4
arch/riscv/boot/dts/sophgo/sg2042.dtsi
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@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 {
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
dma-coherent;
msi-parent = <&msi>;
status = "disabled";
};
@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 {
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
dma-coherent;
msi-parent = <&msi>;
status = "disabled";
};
@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 {
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
dma-coherent;
msi-parent = <&msi>;
status = "disabled";
};
@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 {
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
dma-coherent;
msi-parent = <&msi>;
status = "disabled";
};