github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-24 15:12:13 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/i915/display: convert power wells to struct intel_display

Browse Source 
Going forward, struct intel_display is the main device data structure
for display. Switch the power well code over to it.

v2: Fix parenthesis alignment

Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b8c0ff5502a5df55ec7a160d90257c6f2befc0b6.1732808222.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2024-11-28 17:38:21 +02:00
parent a92152f2c7
commit 263e827292
7 changed files with 321 additions and 332 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/display/intel_display_debugfs.c
View File

@ -730,11 +730,12 @@ static bool
intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
enum i915_power_well_id power_well_id)
{
struct intel_display *display = &i915->display;
intel_wakeref_t wakeref;
bool is_enabled;
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
is_enabled = intel_display_power_well_is_enabled(i915,
is_enabled = intel_display_power_well_is_enabled(display,
power_well_id);
intel_runtime_pm_put(&i915->runtime_pm, wakeref);

71
drivers/gpu/drm/i915/display/intel_display_power.c
View File

@ -293,12 +293,13 @@ sanitize_target_dc_state(struct drm_i915_private *i915,
void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
u32 state)
{
struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
bool dc_off_enabled;
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
if (drm_WARN_ON(&dev_priv->drm, !power_well))
goto unlock;
@ -308,18 +309,18 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
if (state == power_domains->target_dc_state)
goto unlock;
dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
dc_off_enabled = intel_power_well_is_enabled(display, power_well);
/*
* If DC off power well is disabled, need to enable and disable the
* DC off power well to effect target DC state.
*/
if (!dc_off_enabled)
intel_power_well_enable(dev_priv, power_well);
intel_power_well_enable(display, power_well);
power_domains->target_dc_state = state;
if (!dc_off_enabled)
intel_power_well_disable(dev_priv, power_well);
intel_power_well_disable(display, power_well);
unlock:
mutex_unlock(&power_domains->lock);
@ -495,7 +496,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
return;
for_each_power_domain_well(display, power_well, domain)
intel_power_well_get(dev_priv, power_well);
intel_power_well_get(display, power_well);
power_domains->domain_use_count[domain]++;
}
@ -592,7 +593,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
power_domains->domain_use_count[domain]--;
for_each_power_domain_well_reverse(display, power_well, domain)
intel_power_well_put(dev_priv, power_well);
intel_power_well_put(display, power_well);
}
static void __intel_display_power_put(struct drm_i915_private *dev_priv,
@ -1037,7 +1038,7 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
mutex_lock(&power_domains->lock);
for_each_power_well(display, power_well)
intel_power_well_sync_hw(dev_priv, power_well);
intel_power_well_sync_hw(display, power_well);
mutex_unlock(&power_domains->lock);
}
@ -1437,11 +1438,11 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
/* enable PG1 and Misc I/O */
mutex_lock(&power_domains->lock);
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
intel_power_well_enable(dev_priv, well);
well = lookup_power_well(display, SKL_DISP_PW_1);
intel_power_well_enable(display, well);
well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
intel_power_well_enable(dev_priv, well);
well = lookup_power_well(display, SKL_DISP_PW_MISC_IO);
intel_power_well_enable(display, well);
mutex_unlock(&power_domains->lock);
@ -1480,8 +1481,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
* Note that even though the driver's request is removed power well 1
* may stay enabled after this due to DMC's own request on it.
*/
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
intel_power_well_disable(dev_priv, well);
well = lookup_power_well(display, SKL_DISP_PW_1);
intel_power_well_disable(display, well);
mutex_unlock(&power_domains->lock);
@ -1510,8 +1511,8 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* Enable PG1 */
mutex_lock(&power_domains->lock);
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
intel_power_well_enable(dev_priv, well);
well = lookup_power_well(display, SKL_DISP_PW_1);
intel_power_well_enable(display, well);
mutex_unlock(&power_domains->lock);
@ -1548,8 +1549,8 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
*/
mutex_lock(&power_domains->lock);
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
intel_power_well_disable(dev_priv, well);
well = lookup_power_well(display, SKL_DISP_PW_1);
intel_power_well_disable(display, well);
mutex_unlock(&power_domains->lock);
@ -1659,8 +1660,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
* The AUX IO power wells will be enabled on demand.
*/
mutex_lock(&power_domains->lock);
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
intel_power_well_enable(dev_priv, well);
well = lookup_power_well(display, SKL_DISP_PW_1);
intel_power_well_enable(display, well);
mutex_unlock(&power_domains->lock);
if (DISPLAY_VER(dev_priv) == 14)
@ -1743,8 +1744,8 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
* disabled at this point.
*/
mutex_lock(&power_domains->lock);
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
intel_power_well_disable(dev_priv, well);
well = lookup_power_well(display, SKL_DISP_PW_1);
intel_power_well_disable(display, well);
mutex_unlock(&power_domains->lock);
/* 5. */
@ -1753,10 +1754,11 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
static void chv_phy_control_init(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct i915_power_well *cmn_bc =
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);
/*
* DISPLAY_PHY_CONTROL can get corrupted if read. As a
@ -1779,7 +1781,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* override and set the lane powerdown bits accding to the
* current lane status.
*/
if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
if (intel_power_well_is_enabled(display, cmn_bc)) {
u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A));
unsigned int mask;
@ -1810,7 +1812,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
}
if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
if (intel_power_well_is_enabled(display, cmn_d)) {
u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
unsigned int mask;
@ -1840,21 +1842,22 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct i915_power_well *cmn =
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *disp2d =
lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
lookup_power_well(display, VLV_DISP_PW_DISP2D);
/* If the display might be already active skip this */
if (intel_power_well_is_enabled(dev_priv, cmn) &&
intel_power_well_is_enabled(dev_priv, disp2d) &&
if (intel_power_well_is_enabled(display, cmn) &&
intel_power_well_is_enabled(display, disp2d) &&
intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
return;
drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n");
/* cmnlane needs DPLL registers */
intel_power_well_enable(dev_priv, disp2d);
intel_power_well_enable(display, disp2d);
/*
* From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
@ -1863,7 +1866,7 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
* Simply ungating isn't enough to reset the PHY enough to get
* ports and lanes running.
*/
intel_power_well_disable(dev_priv, cmn);
intel_power_well_disable(display, cmn);
}
static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0)
@ -2015,13 +2018,13 @@ void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
for_each_power_well_reverse(display, power_well) {
if (power_well->desc->always_on || power_well->count ||
!intel_power_well_is_enabled(i915, power_well))
!intel_power_well_is_enabled(display, power_well))
continue;
drm_dbg_kms(&i915->drm,
"BIOS left unused %s power well enabled, disabling it\n",
intel_power_well_name(power_well));
intel_power_well_disable(i915, power_well);
intel_power_well_disable(display, power_well);
}
mutex_unlock(&power_domains->lock);
@ -2195,7 +2198,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
int domains_count;
bool enabled;
enabled = intel_power_well_is_enabled(i915, power_well);
enabled = intel_power_well_is_enabled(display, power_well);
if ((intel_power_well_refcount(power_well) ||
intel_power_well_is_always_on(power_well)) !=
enabled)

547
drivers/gpu/drm/i915/display/intel_display_power_well.c
View File

File diff suppressed because it is too large Load Diff

19
drivers/gpu/drm/i915/display/intel_display_power_well.h
View File

@ -10,7 +10,6 @@
#include "intel_display_power.h"
#include "intel_dpio_phy.h"
struct drm_i915_private;
struct i915_power_well_ops;
struct intel_display;
struct intel_encoder;
@ -127,23 +126,23 @@ struct i915_power_well {
u8 instance_idx;
};
struct i915_power_well *lookup_power_well(struct drm_i915_private *i915,
struct i915_power_well *lookup_power_well(struct intel_display *display,
enum i915_power_well_id id);
void intel_power_well_enable(struct drm_i915_private *i915,
void intel_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well);
void intel_power_well_disable(struct drm_i915_private *i915,
void intel_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well);
void intel_power_well_sync_hw(struct drm_i915_private *i915,
void intel_power_well_sync_hw(struct intel_display *display,
struct i915_power_well *power_well);
void intel_power_well_get(struct drm_i915_private *i915,
void intel_power_well_get(struct intel_display *display,
struct i915_power_well *power_well);
void intel_power_well_put(struct drm_i915_private *i915,
void intel_power_well_put(struct intel_display *display,
struct i915_power_well *power_well);
bool intel_power_well_is_enabled(struct drm_i915_private *i915,
bool intel_power_well_is_enabled(struct intel_display *display,
struct i915_power_well *power_well);
bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well);
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
bool intel_display_power_well_is_enabled(struct intel_display *display,
enum i915_power_well_id power_well_id);
bool intel_power_well_is_always_on(struct i915_power_well *power_well);
const char *intel_power_well_name(struct i915_power_well *power_well);
@ -152,7 +151,7 @@ int intel_power_well_refcount(struct i915_power_well *power_well);
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask);
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,
enum dpio_channel ch, bool override);
void gen9_enable_dc5(struct intel_display *display);

7
drivers/gpu/drm/i915/display/intel_dpio_phy.c
View File

@ -855,6 +855,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@ -871,7 +872,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
*/
if (ch == DPIO_CH0 && pipe == PIPE_B)
dig_port->release_cl2_override =
!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
!chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true);
chv_phy_powergate_lanes(encoder, true, lane_mask);
@ -1013,11 +1014,11 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
void chv_phy_release_cl2_override(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (dig_port->release_cl2_override) {
chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false);
dig_port->release_cl2_override = false;
}
}

2
drivers/gpu/drm/i915/display/intel_hdcp.c
View File

@ -349,7 +349,7 @@ static bool hdcp_key_loadable(struct intel_display *display)
/* PG1 (power well #1) needs to be enabled */
with_intel_runtime_pm(&i915->runtime_pm, wakeref)
enabled = intel_display_power_well_is_enabled(i915, id);
enabled = intel_display_power_well_is_enabled(display, id);
/*
* Another req for hdcp key loadability is enabled state of pll for

4
drivers/gpu/drm/i915/display/intel_pps.c
View File

@ -134,7 +134,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
*/
if (!pll_enabled) {
release_cl_override = display->platform.cherryview &&
!chv_phy_powergate_ch(dev_priv, phy, ch, true);
!chv_phy_powergate_ch(display, phy, ch, true);
if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
drm_err(display->drm,
@ -163,7 +163,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
vlv_force_pll_off(dev_priv, pipe);
if (release_cl_override)
chv_phy_powergate_ch(dev_priv, phy, ch, false);
chv_phy_powergate_ch(display, phy, ch, false);
}
}