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dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
Add WPSS PIL loading support for SC7280 SoCs. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1643712724-12436-3-git-send-email-quic_mpubbise@quicinc.com
This commit is contained in:
Rakesh Pillai
Bjorn Andersson
parent
841fdd0ac0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC7280 WPSS Peripheral Image Loader
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description:
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This document defines the binding for a component that loads and boots firmware
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on the Qualcomm Technology Inc. WPSS.
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properties:
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compatible:
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enum:
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- qcom,sc7280-wpss-pil
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reg:
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maxItems: 1
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description:
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The base address and size of the qdsp6ss register
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interrupts:
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items:
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- description: Watchdog interrupt
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- description: Fatal interrupt
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- description: Ready interrupt
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- description: Handover interrupt
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- description: Stop acknowledge interrupt
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- description: Shutdown acknowledge interrupt
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interrupt-names:
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items:
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- const: wdog
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- const: fatal
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- const: ready
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- const: handover
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- const: stop-ack
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- const: shutdown-ack
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clocks:
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items:
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- description: GCC WPSS AHB BDG Master clock
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- description: GCC WPSS AHB clock
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- description: GCC WPSS RSCP clock
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- description: XO clock
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clock-names:
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items:
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- const: ahb_bdg
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- const: ahb
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- const: rscp
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- const: xo
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power-domains:
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items:
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- description: CX power domain
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- description: MX power domain
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power-domain-names:
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items:
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- const: cx
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- const: mx
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resets:
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items:
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- description: AOSS restart
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- description: PDC SYNC
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reset-names:
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items:
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- const: restart
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- const: pdc_sync
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memory-region:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Reference to the reserved-memory for the Hexagon core
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firmware-name:
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$ref: /schemas/types.yaml#/definitions/string
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description:
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The name of the firmware which should be loaded for this remote
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processor.
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qcom,halt-regs:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Phandle reference to a syscon representing TCSR followed by the
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three offsets within syscon for q6, modem and nc halt registers.
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qcom,qmp:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Reference to the AOSS side-channel message RAM.
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qcom,smem-states:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: States used by the AP to signal the Hexagon core
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items:
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- description: Stop the modem
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qcom,smem-state-names:
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$ref: /schemas/types.yaml#/definitions/string
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description: The names of the state bits used for SMP2P output
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items:
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- const: stop
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glink-edge:
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type: object
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description: |
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Qualcomm G-Link subnode which represents communication edge, channels
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and devices related to the ADSP.
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properties:
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interrupts:
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items:
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- description: IRQ from WPSS to GLINK
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mboxes:
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items:
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- description: Mailbox for communication between APPS and WPSS
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label:
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description: The names of the state bits used for SMP2P output
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items:
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- const: wpss
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qcom,remote-pid:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: ID of the shared memory used by GLINK for communication with WPSS
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maxItems: 1
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required:
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- interrupts
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- mboxes
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- label
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- qcom,remote-pid
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- power-domains
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- power-domain-names
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- resets
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- reset-names
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- qcom,halt-regs
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- memory-region
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- qcom,qmp
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- qcom,smem-states
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- qcom,smem-state-names
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- glink-edge
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/reset/qcom,sdm845-aoss.h>
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#include <dt-bindings/reset/qcom,sdm845-pdc.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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remoteproc@8a00000 {
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compatible = "qcom,sc7280-wpss-pil";
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reg = <0x08a00000 0x10000>;
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interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
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<&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
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<&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready", "handover",
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"stop-ack", "shutdown-ack";
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clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
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<&gcc GCC_WPSS_AHB_CLK>,
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<&gcc GCC_WPSS_RSCP_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ahb_bdg", "ahb",
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"rscp", "xo";
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power-domains = <&rpmhpd SC7280_CX>,
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<&rpmhpd SC7280_MX>;
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power-domain-names = "cx", "mx";
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memory-region = <&wpss_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&wpss_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
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<&pdc_reset PDC_WPSS_SYNC_RESET>;
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reset-names = "restart", "pdc_sync";
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qcom,halt-regs = <&tcsr_mutex 0x37000>;
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_WPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "wpss";
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qcom,remote-pid = <13>;
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};
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};
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