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drm/amd/display: add missing reg defs for DCN3x HUBBUB

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[Why&How]
The omitted register definition caused call traces like:

[    3.811215] WARNING: CPU: 7 PID: 794 at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:120 set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu]
[    3.811406] Modules linked in: amdgpu(+) drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm i2c_piix4 drm_panel_orientation_quirks
[    3.811419] CPU: 7 PID: 794 Comm: systemd-udevd Not tainted 5.16.0-kfd+ #132
[    3.811422] Hardware name: System manufacturer System Product Name/ROG STRIX B450-F GAMING, BIOS 3003 12/09/2019
[    3.811425] RIP: 0010:set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu]
[    3.811615] Code: 08 49 89 51 08 8b 08 48 8d 42 08 49 89 41 08 44 8b 02 48 8d 50 08 0f b6 c9 49 89 51 08 8b 00 45 85 c0 75 b3 0f 0b eb af 5d c3 <0f> 0b e9 48 ff ff ff 49 8b 51 08 eb d0 49 8b 41 08 eb d5 66 0f 1f
[    3.811619] RSP: 0018:ffffb8c1c04cf640 EFLAGS: 00010246
[    3.811621] RAX: 0000000000000000 RBX: ffff96f2100d8800 RCX: 0000000000000000
[    3.811623] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffffb8c1c04cf650
[    3.811625] RBP: ffffb8c1c04cf640 R08: 000000000000047f R09: ffffb8c1c04cf658
[    3.811627] R10: ffff96f5161ff000 R11: ffff96f5161ff000 R12: ffff96f204afb9c0
[    3.811629] R13: 0000000000000000 R14: ffff96f202b94c00 R15: ffffb8c1c04cf718
[    3.811631] FS:  00007fe07c2e2880(0000) GS:ffff96f5059c0000(0000) knlGS:0000000000000000
[    3.811634] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    3.811636] CR2: 0000559634ab57b8 CR3: 0000000120674000 CR4: 00000000003506e0
[    3.811637] Call Trace:
[    3.811640]  <TASK>
[    3.811642]  generic_reg_update_ex+0x69/0x200 [amdgpu]
[    3.811831]  ? _printk+0x58/0x6f
[    3.811836]  dcn32_init_crb+0x18f/0x1b0 [amdgpu]
[    3.812031]  dcn32_init_hw+0x379/0x6a0 [amdgpu]
[    3.812223]  dc_hardware_init+0xba/0x100 [amdgpu]
[    3.812415]  amdgpu_dm_init.isra.0.cold+0x166/0x1867 [amdgpu]
[    3.812616]  ? dev_vprintk_emit+0x139/0x15d
[    3.812621]  ? dev_printk_emit+0x4e/0x65
[    3.812624]  dm_hw_init+0x12/0x30 [amdgpu]
[    3.812820]  amdgpu_device_init.cold+0x130d/0x178c [amdgpu]
[    3.813017]  ? pci_read_config_word+0x25/0x40
[    3.813021]  amdgpu_driver_load_kms+0x1a/0x130 [amdgpu]
[    3.813178]  amdgpu_pci_probe+0x130/0x330 [amdgpu]

Fixes: 4f29f9cf09 ("drm/amd: add register headers for DCN32/321")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai 2022-06-16 16:44:55 -04:00 committed by Alex Deucher
parent 1320d6c7b0
commit 262236b4f5
5 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
View File

@ -65,6 +65,7 @@
SR(DCHUBBUB_DET3_CTRL),\
SR(DCHUBBUB_COMPBUF_CTRL),\
SR(COMPBUF_RESERVED_SPACE),\
SR(DCHUBBUB_DEBUG_CTRL_0),\
SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\
@ -118,6 +119,7 @@
HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\
HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\
HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\
HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\

2
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
View File

@ -1807,6 +1807,8 @@
#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2
#define regDCHUBBUB_DET3_CTRL 0x04be
#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2
#define regDCHUBBUB_DEBUG_CTRL_0 0x04c5
#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0
#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2
#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1

3
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
View File

@ -6348,6 +6348,9 @@
#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL
#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L
//DCHUBBUB_DEBUG_CTRL_0
#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x07FF0000L
// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec
//DCN_VM_CONTEXT0_CNTL

2
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
View File

@ -1817,6 +1817,8 @@
#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
#define regCOMPBUF_RESERVED_SPACE 0x04c4
#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2
#define regDCHUBBUB_DEBUG_CTRL_0 0x04c5
#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec

4
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
View File

@ -6350,6 +6350,10 @@
#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL
#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L
//DCHUBBUB_DEBUG_CTRL_0
#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x07FF0000L
// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
//DCN_VM_CONTEXT0_CNTL