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drm/amdgpu: correct ih cg programming for vega10 ih block

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vega10/12 and RAVEN don't support soft override
ih_buffer_mem_clk.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2020-11-30 22:49:40 +08:00 committed by Alex Deucher
parent 554bdbf6de
commit 2601fa6464
1 changed files with 2 additions and 6 deletions
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8
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
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@ -640,15 +640,11 @@ static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
field_val = enable ? 0 : 1;
/**
* Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE
* and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.
* Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.
*/
if (adev->asic_type > CHIP_VEGA10) {
data = REG_SET_FIELD(data, IH_CLK_CTRL,
IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
if (adev->asic_type == CHIP_RENOIR)
data = REG_SET_FIELD(data, IH_CLK_CTRL,
IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
}
data = REG_SET_FIELD(data, IH_CLK_CTRL,
DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);